Update Firmware with features:

* Shellmatta implemented using UART
* Version string implemented
* Increased heap size
* Add shellmatta printf support
This commit is contained in:
2020-02-09 19:13:37 +01:00
parent 07793fb490
commit 8bbc2e60f8
10 changed files with 448 additions and 59 deletions

View File

@@ -1,2 +1,93 @@
#include <uart/dma-ring-buffer.h>
#include <clock-enable-manager.h>
int dma_ring_buffer_initialize(struct dma_ring_buffer *dma_buffer, uint8_t base_dma_id, DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count, char *data_buffer, void* src_reg, uint8_t dma_trigger_channel)
{
if (!dma_buffer || !dma_stream || !data_buffer || !src_reg)
return -1;
if (dma_trigger_channel > 7)
return -3;
dma_buffer->base_dma_id = base_dma_id;
switch (base_dma_id) {
case 1:
rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA1EN));
break;
case 2:
rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA2EN));
break;
default:
return -2;
break;
}
dma_buffer->dma = dma_stream;
dma_buffer->get_idx = 0;
dma_buffer->buffer_count = buffer_element_count;
dma_buffer->data_ptr = data_buffer;
dma_stream->PAR = (uint32_t)src_reg;
dma_stream->M0AR = (uint32_t)data_buffer;
dma_stream->NDTR = buffer_element_count;
dma_stream->NDTR = buffer_element_count;
dma_stream->CR |= (dma_trigger_channel<<25) | DMA_SxCR_MINC | DMA_SxCR_CIRC | DMA_SxCR_EN;
return 0;
}
int dma_ring_buffer_get_data(struct dma_ring_buffer *buff, const char **data_buff, size_t *len)
{
int ret_code = 0;
uint32_t ndtr;
size_t put_idx;
if (!buff || !data_buff || !len)
return -1;
ndtr = buff->dma->NDTR;
put_idx = buff->buffer_count - ndtr;
/* Check if wrap around */
if (put_idx < buff->get_idx) {
*data_buff = &(buff->data_ptr[buff->get_idx]);
*len = buff->buffer_count - buff->get_idx;
buff->get_idx = 0;
ret_code = 1;
} else if (put_idx > buff->get_idx) {
*data_buff = &(buff->data_ptr[buff->get_idx]);
*len = put_idx - buff->get_idx;
buff->get_idx += *len;
} else {
/* No new data */
*len = 0;
}
return ret_code;
}
void dma_ring_buffer_stop(struct dma_ring_buffer *buff)
{
if (!buff || !buff->dma)
return;
buff->dma->CR = 0;
buff->dma->NDTR = 0;
buff->dma->M1AR = 0;
buff->dma->FCR = 0;
switch (buff->base_dma_id) {
case 1:
rcc_manager_disable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA1EN));
break;
case 2:
rcc_manager_disable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA2EN));
break;
default:
break;
}
}

View File

@@ -1,44 +1,114 @@
/*
* uart.c
*
* Created on: Dec 15, 2014
* Author: shino-chan
*/
//USART2
//PA2 => TX
//PA3 => RX
//Alternate Function 7
#include <uart/uart.h>
#include <stm32f4xx.h>
void initUART() {
__DSB();
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
__DSB();
GPIOA->MODER |= (1<<5);
GPIOA->AFR[0] |= (7<<8); //Enable Clock
GPIOA->MODER |= (1<<5);
GPIOA->AFR[0] |= (7<<8);
asm("nop");
asm("nop");
asm("nop");
USART2->BRR = 0x1117; //Baudrate 273.4375=>0x1117 9600baud bei 42MHz Periph
USART2->CR1 = USART_CR1_UE | USART_CR1_TE;
}
void sendChar(char c) {
while(!(USART2->SR & USART_SR_TXE));
USART2->DR = c;
}
void sendString(char* s, int count) {
int i = 0;
for (i = 0; i < count; i++,s++)
{
if (!(*s))
break;
sendChar(*s);
}
}
/*
* uart.c
*
* Created on: Dec 15, 2014
* Author: shino-chan
*/
//USART2
//PA2 => TX
//PA3 => RX
//Alternate Function 7
#include <uart/uart.h>
#include <stm32f4xx.h>
#include <clock-enable-manager.h>
#include <stm32-gpio-macros.h>
#include <uart/dma-ring-buffer.h>
static struct dma_ring_buffer ring_buff;
static char uart_rx_buffer[64];
void initUART() {
__DSB();
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
__DSB();
GPIOA->MODER |= (1<<5);
GPIOA->AFR[0] |= (7<<8); //Enable Clock
GPIOA->MODER |= (1<<5);
GPIOA->AFR[0] |= (7<<8);
asm("nop");
asm("nop");
asm("nop");
USART2->BRR = 0x1117; //Baudrate 273.4375=>0x1117 9600baud bei 42MHz Periph
USART2->CR1 = USART_CR1_UE | USART_CR1_TE;
}
void sendChar(char c) {
while(!(USART2->SR & USART_SR_TXE));
USART2->DR = c;
}
void sendString(char* s, int count) {
int i = 0;
for (i = 0; i < count; i++,s++)
{
if (!(*s))
break;
sendChar(*s);
}
}
static inline void uart_gpio_config()
{
rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(UART_PORT_RCC_MASK));
UART_PORT->MODER &= MODER_DELETE(UART_TX_PIN) & MODER_DELETE(UART_RX_PIN);
UART_PORT->MODER |= ALTFUNC(UART_RX_PIN) | ALTFUNC(UART_TX_PIN);
SETAF(UART_PORT, UART_RX_PIN, UART_RX_PIN_ALTFUNC);
SETAF(UART_PORT, UART_TX_PIN, UART_TX_PIN_ALTFUNC);
}
void uart_init_with_dma()
{
rcc_manager_enable_clock(&RCC->APB2ENR, BITMASK_TO_BITNO(UART_RCC_MASK));
uart_gpio_config();
UART_PERIPH->BRR = UART_BRR_REG_VALUE;
UART_PERIPH->CR3 = USART_CR3_DMAR | USART_CR3_DMAT;
UART_PERIPH->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE;
dma_ring_buffer_initialize(&ring_buff, 2, DMA2_Stream5, sizeof(uart_rx_buffer), uart_rx_buffer, (char *)&UART_PERIPH->DR, 4);
}
void uart_disable()
{
UART_PERIPH->CR1 = 0;
UART_PERIPH->CR2 = 0;
UART_PERIPH->CR3 = 0;
dma_ring_buffer_stop(&ring_buff);
rcc_manager_disable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(UART_PORT_RCC_MASK));
rcc_manager_disable_clock(&RCC->APB2ENR, BITMASK_TO_BITNO(UART_RCC_MASK));
}
void uart_send_char(char c)
{
while(!(UART_PERIPH->SR & USART_SR_TXE));
UART_PERIPH->DR = c;
}
void uart_send_array(const char *data, uint32_t len)
{
uint32_t i;
for (i = 0; i < len; i++)
uart_send_char(data[i]);
}
void uart_send_string(char *string)
{
int i;
for (i = 0; string[i] != '\0'; i++)
uart_send_char(string[i]);
}
void uart_send_array_with_dma(char *data, uint32_t len);
void uart_send_string_with_dma(char *string);
int uart_receive_data_with_dma(const char **data, size_t *len)
{
return dma_ring_buffer_get_data(&ring_buff, data, len);
}