Issue #18: Implement driver for backup RAM
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@ -23,29 +23,31 @@
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/**
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* @brief Init the backup ram and make it accesible
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*/
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void backup_ram_init();
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void backup_ram_init(void);
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/**
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* @brief Disable access to the backup RAM. This saves power
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*/
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void backup_ram_disable();
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void backup_ram_disable(void);
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/**
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* @brief Whis function overwrites the backup RAM with 0x00
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* @brief Whis function overwrites the backup RAM with 0x00000000
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*/
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void backup_ram_wipe();
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void backup_ram_wipe(void);
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/**
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* @brief Read data from the backup RAM
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* @param addr Address offset inside memory
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* @param data read 32bit data
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* @param data Read data
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* @param count amount of 32 bit words to read
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* @return 0 if successful
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*/
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int backup_ram_get_data(uint32_t addr, uint32_t *data);
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int backup_ram_get_data(uint32_t addr, uint32_t *data, uint32_t count);
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/**
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* @brief Write data structure to backup RAM
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* @param data
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* @return
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* @param[in] data Data to write.
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* @param count Count of 32 bit words to write
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* @return 0 if successful
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*/
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int backup_ram_write_data(uint32_t addr, uint32_t data);
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int backup_ram_write_data(uint32_t addr, const uint32_t *data, uint32_t count);
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@ -21,34 +21,82 @@
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#include <stm-periph/backup-ram.h>
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#include <stm-periph/clock-enable-manager.h>
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#include <stm32/stm32f4xx.h>
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#include <helper-macros/helper-macros.h>
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void backup_ram_init()
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#define BACKUP_RAM_BASE BKPSRAM_BASE
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#define BACKUP_RAM_SIZE 4096U
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#define BACKUP_RAM_SIZE_WORDS (BACKUP_RAM_SIZE / 4U)
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#define BACKUP_RAM_END_ADDR (BACKUP_RAM_BASE + BACKUP_RAM_SIZE - 1U)
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#define backup_ram ((volatile uint32_t *)BACKUP_RAM_BASE)
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#if !is_power_of_two(BACKUP_RAM_SIZE)
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#error "Backup RAM size ahs to be a power of two!"
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#endif
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void backup_ram_init(void)
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{
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rcc_manager_enable_clock(&RCC->APB1ENR, BITMASK_TO_BITNO(RCC_APB1ENR_PWREN));
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/* Enable access to backup RAM register set */
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PWR->CR |= PWR_CR_DBP;
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/* Enable the backup regulator */
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PWR->CSR |= PWR_CSR_BRE;
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/* Wait until regulator is ready */
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while (!(PWR->CSR & PWR_CSR_BRR));
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/* Enable clock for backup ram interface */
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rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_BKPSRAMEN));
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}
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void backup_ram_disable()
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void backup_ram_disable(void)
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{
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/* Disable access to backup RAM register set */
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PWR->CR &= ~PWR_CR_DBP;
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rcc_manager_disable_clock(&RCC->APB1ENR, BITMASK_TO_BITNO(RCC_APB1ENR_PWREN));
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rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_BKPSRAMEN));
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}
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void backup_ram_wipe()
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void backup_ram_wipe(void)
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{
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uint32_t i;
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for (i = 0; i < BACKUP_RAM_SIZE_WORDS; i++)
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backup_ram[i] = 0UL;
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}
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int backup_ram_get_data(uint32_t addr, uint32_t *data)
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int backup_ram_get_data(uint32_t addr, uint32_t *data, uint32_t count)
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{
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volatile uint32_t *ptr;
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if (!data)
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return -1002;
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if (addr >= BACKUP_RAM_SIZE_WORDS)
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return -1001;
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ptr = &backup_ram[addr];
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for (; count > 0; count--)
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*(data++) = *(ptr++);
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return 0;
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}
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int backup_ram_write_data(uint32_t addr, uint32_t data)
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int backup_ram_write_data(uint32_t addr, const uint32_t *data, uint32_t count)
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{
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volatile uint32_t *ptr;
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if (!data)
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return -1002;
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if (addr >= BACKUP_RAM_SIZE_WORDS)
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return -1001;
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ptr = &backup_ram[addr];
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for (; count > 0; count--)
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*(ptr++) = *(data++);
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return 0;
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}
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