Change linker script and startup code.
This is my own code from my template. It is much cleaner than the old code.
This commit is contained in:
314
stm-firmware/boot/startup_stm32f407vx.c
Normal file
314
stm-firmware/boot/startup_stm32f407vx.c
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@@ -0,0 +1,314 @@
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/*
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* STM32F4 Startup Code for STM32F407 devices
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* Copyright (C) 2017 Mario Hüttel <mario.huettel@gmx.net>
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*
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* This file is part of 'STM32F4 code template'.
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*
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* It is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 2 of the License.
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*
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* This code is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this template. If not, see <http://www.gnu.org/licenses/>.
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* ------------------------------------------------------------------------
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*/
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/* C++ library init */
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# if defined(__cplusplus)
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extern "C" {
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extern void __libc_init_array(void);
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}
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#endif
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/* Defines for weak default handlers */
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#define WEAK __attribute__((weak))
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#define ALIAS(func) __attribute__ ((weak, alias (#func)))
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/* Define for section mapping */
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#define SECTION(sec) __attribute__((section(sec)))
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/* Handler prototypes */
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#if defined(_cplusplus)
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extern "C" {
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#endif
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/* Interrupt Defualt handler */
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WEAK void __int_default_handler(void);
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/* Core Interrupts */
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void Reset_Handler(void);
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void NMI_Handler(void) ALIAS(__int_default_handler);
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void HardFault_Handler(void) ALIAS(__int_default_handler);
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void MemManage_Handler(void) ALIAS(__int_default_handler);
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void BusFault_Handler(void) ALIAS(__int_default_handler);
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void UsageFault_Handler(void) ALIAS(__int_default_handler);
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void SVC_Handler(void) ALIAS(__int_default_handler);
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void DebugMon_Handler(void) ALIAS(__int_default_handler);
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void PendSV_Handler(void) ALIAS(__int_default_handler);
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void SysTick_Handler(void) ALIAS(__int_default_handler);
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/* Peripheral Interrupts (by default mapped onto Default Handler) */
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void WWDG_IRQHandler(void) ALIAS(__int_default_handler);
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void PVD_IRQHandler(void) ALIAS(__int_default_handler);
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void TAMP_STAMP_IRQHandler(void) ALIAS(__int_default_handler);
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void RTC_WKUP_IRQHandler(void) ALIAS(__int_default_handler);
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void FLASH_IRQHandler(void) ALIAS(__int_default_handler);
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void RCC_IRQHandler(void) ALIAS(__int_default_handler);
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void EXTI0_IRQHandler(void) ALIAS(__int_default_handler);
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void EXTI1_IRQHandler(void) ALIAS(__int_default_handler);
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void EXTI2_IRQHandler(void) ALIAS(__int_default_handler);
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void EXTI3_IRQHandler(void) ALIAS(__int_default_handler);
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void EXTI4_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA1_Stream0_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA1_Stream1_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA1_Stream2_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA1_Stream3_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA1_Stream4_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA1_Stream5_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA1_Stream6_IRQHandler(void) ALIAS(__int_default_handler);
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void ADC_IRQHandler(void) ALIAS(__int_default_handler);
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void CAN1_TX_IRQHandler(void) ALIAS(__int_default_handler);
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void CAN1_RX0_IRQHandler(void) ALIAS(__int_default_handler);
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void CAN1_RX1_IRQHandler(void) ALIAS(__int_default_handler);
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void CAN1_SCE_IRQHandler(void) ALIAS(__int_default_handler);
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void EXTI9_5_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM1_BRK_TIM9_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM1_UP_TIM10_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM1_TRG_COM_TIM11_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM1_CC_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM2_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM3_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM4_IRQHandler(void) ALIAS(__int_default_handler);
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void I2C1_EV_IRQHandler(void) ALIAS(__int_default_handler);
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void I2C1_ER_IRQHandler(void) ALIAS(__int_default_handler);
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void I2C2_EV_IRQHandler(void) ALIAS(__int_default_handler);
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void I2C2_ER_IRQHandler(void) ALIAS(__int_default_handler);
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void SPI1_IRQHandler(void) ALIAS(__int_default_handler);
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void SPI2_IRQHandler(void) ALIAS(__int_default_handler);
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void USART1_IRQHandler(void) ALIAS(__int_default_handler);
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void USART2_IRQHandler(void) ALIAS(__int_default_handler);
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void USART3_IRQHandler(void) ALIAS(__int_default_handler);
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void EXTI15_10_IRQHandler(void) ALIAS(__int_default_handler);
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void RTC_Alarm_IRQHandler(void) ALIAS(__int_default_handler);
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void OTG_FS_WKUP_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM8_BRK_TIM12_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM8_UP_TIM13_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM8_TRG_COM_TIM14_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM8_CC_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA1_Stream7_IRQHandler(void) ALIAS(__int_default_handler);
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void FSMC_IRQHandler(void) ALIAS(__int_default_handler);
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void SDIO_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM5_IRQHandler(void) ALIAS(__int_default_handler);
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void SPI3_IRQHandler(void) ALIAS(__int_default_handler);
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void UART4_IRQHandler(void) ALIAS(__int_default_handler);
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void UART5_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM6_DAC_IRQHandler(void) ALIAS(__int_default_handler);
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void TIM7_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA2_Stream0_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA2_Stream1_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA2_Stream2_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA2_Stream3_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA2_Stream4_IRQHandler(void) ALIAS(__int_default_handler);
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void ETH_IRQHandler(void) ALIAS(__int_default_handler);
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void ETH_WKUP_IRQHandler(void) ALIAS(__int_default_handler);
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void CAN2_TX_IRQHandler(void) ALIAS(__int_default_handler);
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void CAN2_RX0_IRQHandler(void) ALIAS(__int_default_handler);
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void CAN2_RX1_IRQHandler(void) ALIAS(__int_default_handler);
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void CAN2_SCE_IRQHandler(void) ALIAS(__int_default_handler);
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void OTG_FS_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA2_Stream5_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA2_Stream6_IRQHandler(void) ALIAS(__int_default_handler);
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void DMA2_Stream7_IRQHandler(void) ALIAS(__int_default_handler);
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void USART6_IRQHandler(void) ALIAS(__int_default_handler);
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void I2C3_EV_IRQHandler(void) ALIAS(__int_default_handler);
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void I2C3_ER_IRQHandler(void) ALIAS(__int_default_handler);
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void OTG_HS_EP1_OUT_IRQHandler(void) ALIAS(__int_default_handler);
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void OTG_HS_EP1_IN_IRQHandler(void) ALIAS(__int_default_handler);
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void OTG_HS_WKUP_IRQHandler(void) ALIAS(__int_default_handler);
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void OTG_HS_IRQHandler(void) ALIAS(__int_default_handler);
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void DCMI_IRQHandler(void) ALIAS(__int_default_handler);
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void CRYP_IRQHandler(void) ALIAS(__int_default_handler);
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void HASH_RNG_IRQHandler(void) ALIAS(__int_default_handler);
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void FPU_IRQHandler(void) ALIAS(__int_default_handler);
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extern int main(void);
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extern void SystemInit(void);
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extern void __ld_top_of_stack(void);
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#if defined(_cplusplus)
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extern "C" }
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#endif
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void (* const vector_table[])(void) SECTION(".vectors") = {
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&__ld_top_of_stack,
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/* Core Interrupts */
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Reset_Handler,
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NMI_Handler,
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HardFault_Handler,
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MemManage_Handler,
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BusFault_Handler,
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UsageFault_Handler,
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0,
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0,
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0,
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0,
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SVC_Handler,
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DebugMon_Handler,
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0,
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PendSV_Handler,
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SysTick_Handler,
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/* Peripheral Interrupts */
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WWDG_IRQHandler,
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PVD_IRQHandler,
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TAMP_STAMP_IRQHandler,
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RTC_WKUP_IRQHandler,
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FLASH_IRQHandler,
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RCC_IRQHandler,
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EXTI0_IRQHandler,
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EXTI1_IRQHandler,
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EXTI2_IRQHandler,
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EXTI3_IRQHandler,
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EXTI4_IRQHandler,
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DMA1_Stream0_IRQHandler,
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DMA1_Stream1_IRQHandler,
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DMA1_Stream2_IRQHandler,
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DMA1_Stream3_IRQHandler,
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DMA1_Stream4_IRQHandler,
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DMA1_Stream5_IRQHandler,
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DMA1_Stream6_IRQHandler,
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ADC_IRQHandler,
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CAN1_TX_IRQHandler,
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CAN1_RX0_IRQHandler,
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CAN1_RX1_IRQHandler,
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CAN1_SCE_IRQHandler,
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EXTI9_5_IRQHandler,
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TIM1_BRK_TIM9_IRQHandler,
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TIM1_UP_TIM10_IRQHandler,
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TIM1_TRG_COM_TIM11_IRQHandler,
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TIM1_CC_IRQHandler,
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TIM2_IRQHandler,
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TIM3_IRQHandler,
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TIM4_IRQHandler,
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I2C1_EV_IRQHandler,
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I2C1_ER_IRQHandler,
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I2C2_EV_IRQHandler,
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I2C2_ER_IRQHandler,
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SPI1_IRQHandler,
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SPI2_IRQHandler,
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USART1_IRQHandler,
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USART2_IRQHandler,
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USART3_IRQHandler,
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EXTI15_10_IRQHandler,
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RTC_Alarm_IRQHandler,
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OTG_FS_WKUP_IRQHandler,
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TIM8_BRK_TIM12_IRQHandler,
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TIM8_UP_TIM13_IRQHandler,
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TIM8_TRG_COM_TIM14_IRQHandler,
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TIM8_CC_IRQHandler,
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DMA1_Stream7_IRQHandler,
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FSMC_IRQHandler,
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SDIO_IRQHandler,
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TIM5_IRQHandler,
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SPI3_IRQHandler,
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UART4_IRQHandler,
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UART5_IRQHandler,
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TIM6_DAC_IRQHandler,
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TIM7_IRQHandler,
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DMA2_Stream0_IRQHandler,
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DMA2_Stream1_IRQHandler,
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DMA2_Stream2_IRQHandler,
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DMA2_Stream3_IRQHandler,
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DMA2_Stream4_IRQHandler,
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ETH_IRQHandler,
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ETH_WKUP_IRQHandler,
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CAN2_TX_IRQHandler,
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CAN2_RX0_IRQHandler,
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CAN2_RX1_IRQHandler,
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CAN2_SCE_IRQHandler,
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OTG_FS_IRQHandler,
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DMA2_Stream5_IRQHandler,
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DMA2_Stream6_IRQHandler,
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DMA2_Stream7_IRQHandler,
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USART6_IRQHandler,
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I2C3_EV_IRQHandler,
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I2C3_ER_IRQHandler,
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OTG_HS_EP1_OUT_IRQHandler,
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OTG_HS_EP1_IN_IRQHandler,
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OTG_HS_WKUP_IRQHandler,
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OTG_HS_IRQHandler,
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DCMI_IRQHandler,
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CRYP_IRQHandler,
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HASH_RNG_IRQHandler,
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FPU_IRQHandler
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};
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static void __init_section(unsigned int *src_start, unsigned int *dest_start, unsigned int *dest_end) {
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unsigned int *get, *put;
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put = dest_start;
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get = src_start;
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while ((unsigned int)put < (unsigned int)dest_end) {
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*(put++) = *(get++);
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}
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}
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static void __fill_zero(unsigned int *start, unsigned int *end) {
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while ((unsigned int) start < (unsigned int)end) {
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*(start++) = 0x00000000;
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}
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}
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extern unsigned int __ld_load_data;
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extern unsigned int __ld_sdata_ccm;
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extern unsigned int __ld_edata_ccm;
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extern unsigned int __ld_load_ccm_data;
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extern unsigned int __ld_sdata_ccm;
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extern unsigned int __ld_edata_ccm;
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extern unsigned int __ld_sbss_ccm;
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extern unsigned int __ld_ebss_ccm;
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extern unsigned int __ld_sdata;
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extern unsigned int __ld_edata;
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extern unsigned int __ld_sbss;
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extern unsigned int __ld_ebss;
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extern unsigned int __ld_sheap;
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extern unsigned int __ld_eheap;
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void Reset_Handler(void) {
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/* Stack is already initialized by hardware */
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/* Copy .data section */
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__init_section(&__ld_load_data, &__ld_sdata, &__ld_edata);
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/* Fill bss with zero */
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__fill_zero(&__ld_sbss, &__ld_ebss);
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/* Fill Heap with zero */
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__fill_zero(&__ld_sheap, &__ld_eheap);
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/* Fill static CCM memory with zeroes */
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__fill_zero(&__ld_sbss_ccm, &__ld_ebss_ccm);
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/* Init CCM RAM data section */
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__init_section(&__ld_load_ccm_data, &__ld_sdata_ccm, &__ld_edata_ccm);
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/* Set clocks, waitstates, ART operation etc. */
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SystemInit();
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/* C++ init function */
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#if defined(__cplusplus)
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__libc_init_array();
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#endif
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/* Call main */
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main();
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/* Catch return from main() */
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while(1);
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}
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WEAK void __int_default_handler(void)
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{
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while(1);
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}
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@@ -1,519 +0,0 @@
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/**
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******************************************************************************
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* @file startup_stm32f4xx.s
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* @author MCD Application Team
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* @version V1.0.0
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* @date 30-September-2011
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* @brief STM32F4xx Devices vector table for Atollic TrueSTUDIO toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Configure the clock system and the external SRAM mounted on
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* STM324xG-EVAL board to be used as data memory (optional,
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* to be enabled by user)
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m4
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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||||
|
||||
LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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||||
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||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
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||||
/* Call static constructors */
|
||||
//bl __libc_init_array
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||||
/* Call the application's entry point.*/
|
||||
|
||||
/* Enable FPU hard */
|
||||
LDR.W R0, =0xE000ED88
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||||
LDR R1, [R0]
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ORR R1, R1, #(0xF << 20)
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STR R1, [R0]
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||||
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||||
bl main
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||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window WatchDog */
|
||||
.word PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||
.word FLASH_IRQHandler /* FLASH */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||
.word CAN1_TX_IRQHandler /* CAN1 TX */
|
||||
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
||||
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
||||
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
.word FSMC_IRQHandler /* FSMC */
|
||||
.word SDIO_IRQHandler /* SDIO */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
||||
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word DCMI_IRQHandler /* DCMI */
|
||||
.word CRYP_IRQHandler /* CRYP crypto */
|
||||
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_TIM9_IRQHandler
|
||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM10_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FSMC_IRQHandler
|
||||
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TX_IRQHandler
|
||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX0_IRQHandler
|
||||
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX1_IRQHandler
|
||||
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_SCE_IRQHandler
|
||||
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRYP_IRQHandler
|
||||
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_RNG_IRQHandler
|
||||
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user