Restructure include hierarchy

stm-firmware/include/stm-periph/clock-enable-manager.h

@@ -0,0 +1,48 @@
+#ifndef __CLOCK_ENABLE_MANAGER_H__
+#define __CLOCK_ENABLE_MANAGER_H__
+
+#include <stdint.h>
+#include <stm-periph/stm32-gpio-macros.h>
+
+/**
+ * @brief The RCC Enable Manager uses static memory with a fixed maximum
+ */
+#define RCC_ENABLE_MANAGER_STATIC 1U
+
+#if RCC_ENABLE_MANAGER_STATIC
+#define RCC_ENABLE_MANAGER_COUNT 30U
+#else
+#error "RCC Enable Manager not yet implemented with dynamic memory"
+#endif
+
+/**
+ * @brief Enable Clock for peripheral by setting the corresponding bit (@p bit_no) to one
+ *
+ * This function also keeps a enable count on each bit that is set, in order to allow nested enables/disables
+ *
+ * If there is no more space to track a new register bit in memory (either due to the static limit or due to no remaining heap space),
+ * the function still enables the peripheral clock but does not track it and returns -1
+ *
+ * @param rcc_enable_register
+ * @param bit_no
+ *
+ * @return 0 if successful
+ */
+int rcc_manager_enable_clock(volatile uint32_t *rcc_enable_register, uint8_t bit_no);
+
+/**
+ * @brief Disable clock for peripheral and decrement the enaböe-counter of that bit.
+ *
+ * If there is no bit entry in the counting table yet, teh peripheral clock is not disabled and error code
+ * -1 is returned.
+ *
+ * If the count reaches zero, the element is removed from the list to make room for new ones
+ *
+ * @param rcc_enable_register Register to disable the bit in
+ * @param bit_no Bit number (0 to 31) of the bit to disable
+ * @return 0 if successful
+ */
+int rcc_manager_disable_clock(volatile uint32_t *rcc_enable_register, uint8_t bit_no);
+
+
+#endif /* __CLOCK_ENABLE_MANAGER_H__ */

stm-firmware/include/stm-periph/stm32-gpio-macros.h

@@ -0,0 +1,21 @@
+#ifndef __STM32GPIOMACROS_H__
+#define __STM32GPIOMACROS_H__
+
+#define MODER_DELETE(pin) ~(0x3U << (pin * 2))
+#define OUTPUT(pin)  (0x01U << (pin * 2))
+#define PULLUP(pin) (0x1U << (pin* 2))
+#define ALTFUNC(pin) ((0x2) << (pin * 2))
+#define PINMASK(pin) ((0x3) << (pin * 2))
+#define SETAF(PORT,PIN,AF)  PORT->AFR[(PIN < 8 ? 0 : 1)] |= AF << ((PIN < 8 ? PIN : (PIN - 8)) * 4)
+#define ANALOG(pin)  (0x03 << (pin * 2))
+
+#define BITMASK_TO_BITNO(x) (x&0x1?0:x&0x2?1:x&0x4?2:x&0x8?3: \
+		 x&0x10?4:x&0x20?5:x&0x40?6:x&0x80?7: \
+		 x&0x100?8:x&0x200?9:x&0x400?10:x&0x800?11: \
+		 x&0x1000?12:x&0x2000?13:x&0x4000?14:x&0x8000?15: \
+		 x&0x10000?16:x&0x20000?17:x&0x40000?18:x&0x80000?19: \
+		 x&0x100000?20:x&0x200000?21:x&0x400000?22:x&0x800000?23: \
+		 x&0x1000000?24:x&0x2000000?25:x&0x4000000?26:x&0x8000000?27: \
+		 x&0x10000000?28:x&0x20000000?29:x&0x40000000?30:x&0x80000000?31:32)
+
+#endif /* __STM32GPIOMACROS_H__ */

stm-firmware/include/stm-periph/uart/dma-ring-buffer.h

@@ -0,0 +1,40 @@
+#ifndef __DMA_RING_BUFFER_H__
+#define __DMA_RING_BUFFER_H__
+
+#include <stdbool.h>
+#include <stm32/stm32f4xx.h>
+#include <stddef.h>
+
+struct dma_ring_buffer_to_mem {
+	void *data_ptr;
+	size_t buffer_count;
+	DMA_Stream_TypeDef *dma;
+	size_t get_idx;
+	uint8_t base_dma_id;
+	size_t element_size;
+};
+
+struct dma_ring_buffer_to_periph {
+	void *src_buffer;
+	size_t buffer_count;
+	DMA_Stream_TypeDef *dma;
+	volatile size_t dma_get_idx_current;
+	volatile size_t dma_get_idx_future;
+	volatile size_t sw_put_idx;
+	uint8_t dma_base_id;
+	size_t element_size;
+};
+
+int dma_ring_buffer_periph_to_mem_initialize(struct dma_ring_buffer_to_mem *dma_buffer, uint8_t base_dma_id, DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count, size_t element_size, void *data_buffer, void *src_reg, uint8_t dma_trigger_channel);
+int dma_ring_buffer_periph_to_mem_get_data(struct dma_ring_buffer_to_mem *buff, const void **data_buff, size_t *len);
+void dma_ring_buffer_periph_to_mem_stop(struct dma_ring_buffer_to_mem *buff);
+
+int dma_ring_buffer_mem_to_periph_initialize(struct dma_ring_buffer_to_periph *dma_buffer, uint8_t base_dma_id, DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count, size_t element_size, void *data_buffer, uint8_t dma_trigger_channel, void *dest_reg);
+int dma_ring_buffer_mem_to_periph_insert_data(struct dma_ring_buffer_to_periph *buff, const void *data_to_insert, size_t count);
+void dma_ring_buffer_mem_to_periph_int_callback(struct dma_ring_buffer_to_periph *buff);
+void dma_ring_buffer_mem_to_periph_stop(struct dma_ring_buffer_to_periph *buff);
+
+#endif /* __DMA_RING_BUFFER_H__ */
+
+
+

stm-firmware/include/stm-periph/uart/uart.h

@@ -0,0 +1,54 @@
+#include <stdint.h>
+#include <stddef.h>
+
+#ifndef UART_UART_H_
+#define UART_UART_H_
+
+#define UART_RECEIVE_DMA_STREAM DMA2_Stream5
+
+#define UART_SEND_DMA_STREAM DMA2_Stream7
+
+#define UART_PERIPH USART1
+#define UART_RCC_MASK RCC_APB2ENR_USART1EN
+
+#ifdef DEBUGBUILD
+
+#define UART_PORT GPIOA
+#define UART_PORT_RCC_MASK RCC_AHB1ENR_GPIOAEN
+#define UART_RX_PIN 10
+#define UART_TX_PIN 9
+#define UART_RX_PIN_ALTFUNC 7
+#define UART_TX_PIN_ALTFUNC 7
+#else
+
+#endif
+
+/* UART_DIV is 45.5625 => 115200 @ 84 MHz */
+#define UART_DIV_FRACTION 9U /* Equals 9/16 = 0.5625 */
+#define UART_DIV_MANTISSA 45U /* Equals 45 */
+
+#define UART_BRR_REG_VALUE ((UART_DIV_MANTISSA<<4) | UART_DIV_FRACTION);
+
+void initUART();
+void sendChar(char c);
+void sendString(char* s, int count);
+
+
+void uart_init_with_dma();
+
+void uart_disable();
+
+void uart_send_char(char c);
+
+void uart_send_array(const char *data, uint32_t len);
+
+void uart_send_string(const char *string);
+
+void uart_send_array_with_dma(const char *data, uint32_t len);
+
+void uart_send_string_with_dma(const char *string);
+
+int uart_receive_data_with_dma(const char **data, size_t *len);
+
+
+#endif /* UART_UART_H_ */