Compare commits
No commits in common. "14ea4d22fe28b00fb64ce9ae34ccaea140286266" and "d4d654e8dd2ff07b9fc1da32a2eef00452271b02" have entirely different histories.
14ea4d22fe
...
d4d654e8dd
@ -1 +1 @@
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Subproject commit aeb2707d80049094337742d0f62cd24dbef1c01d
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Subproject commit cb937262aa71ee3d610900d7f14eef28e9f11dd0
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@ -33,7 +33,7 @@ enum random_number_error {
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void random_number_gen_init(bool int_enable);
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void random_number_gen_deinit(void);
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void random_number_gen_deinit();
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void random_number_gen_reset(bool int_en);
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@ -46,8 +46,7 @@ void backup_ram_init(bool use_backup_regulator)
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PWR->CSR |= PWR_CSR_BRE;
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/* Wait until regulator is ready */
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while (!(PWR->CSR & PWR_CSR_BRR))
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;
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while (!(PWR->CSR & PWR_CSR_BRR));
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}
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/* Enable clock for backup ram interface */
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@ -37,10 +37,11 @@ static size_t calculate_ring_buffer_fill_level(size_t buffer_size, size_t get_id
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{
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size_t fill_level;
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if (put_idx >= get_idx)
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if (put_idx >= get_idx) {
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fill_level = (put_idx - get_idx);
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else
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} else {
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fill_level = buffer_size - get_idx + put_idx;
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}
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return fill_level;
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}
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@ -48,7 +49,7 @@ static size_t calculate_ring_buffer_fill_level(size_t buffer_size, size_t get_id
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static int dma_ring_buffer_switch_clock_enable(uint8_t base_dma, bool clk_en)
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{
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int ret_val;
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int (*clk_func)(volatile uint32_t *reg, uint8_t bit_no);
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int (*clk_func)(volatile uint32_t *, uint8_t);
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if (clk_en)
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clk_func = rcc_manager_enable_clock;
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@ -71,9 +72,8 @@ static int dma_ring_buffer_switch_clock_enable(uint8_t base_dma, bool clk_en)
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}
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int dma_ring_buffer_periph_to_mem_initialize(struct dma_ring_buffer_to_mem *dma_buffer, uint8_t base_dma_id,
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DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count,
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size_t element_size, volatile void *data_buffer,
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void *src_reg, uint8_t dma_trigger_channel)
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DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count, size_t element_size,
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volatile void *data_buffer, void* src_reg, uint8_t dma_trigger_channel)
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{
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int ret_val = 0;
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@ -106,8 +106,7 @@ int dma_ring_buffer_periph_to_mem_initialize(struct dma_ring_buffer_to_mem *dma_
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return 0;
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}
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int dma_ring_buffer_periph_to_mem_get_data(struct dma_ring_buffer_to_mem *buff, const volatile void **data_buff,
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size_t *len)
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int dma_ring_buffer_periph_to_mem_get_data(struct dma_ring_buffer_to_mem *buff, const volatile void **data_buff, size_t *len)
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{
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int ret_code = 0;
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uint32_t ndtr;
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@ -168,10 +167,7 @@ int dma_ring_buffer_periph_to_mem_fill_level(struct dma_ring_buffer_to_mem *buff
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return 0;
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}
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int dma_ring_buffer_mem_to_periph_initialize(struct dma_ring_buffer_to_periph *dma_buffer, uint8_t base_dma_id,
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DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count,
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size_t element_size, volatile void *data_buffer,
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uint8_t dma_trigger_channel, void *dest_reg)
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int dma_ring_buffer_mem_to_periph_initialize(struct dma_ring_buffer_to_periph *dma_buffer, uint8_t base_dma_id, DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count, size_t element_size, volatile void *data_buffer, uint8_t dma_trigger_channel, void *dest_reg)
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{
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if (!dma_buffer || !dma_stream || !data_buffer || !dest_reg)
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return -1000;
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@ -225,8 +221,7 @@ static void queue_or_start_dma_transfer(struct dma_ring_buffer_to_periph *buff)
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buff->dma->CR |= DMA_SxCR_EN;
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}
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int dma_ring_buffer_mem_to_periph_insert_data(struct dma_ring_buffer_to_periph *buff, const void *data_to_insert,
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size_t count)
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int dma_ring_buffer_mem_to_periph_insert_data(struct dma_ring_buffer_to_periph *buff, const void *data_to_insert, size_t count)
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{
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int ret = 0;
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size_t free_item_count;
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@ -239,8 +234,7 @@ int dma_ring_buffer_mem_to_periph_insert_data(struct dma_ring_buffer_to_periph *
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return -1000;
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/* Check if data fits into buffer minus one element. If not: try full-1 buffer and rest
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* Buffer is not allowed to be completely full, because I cannot ddifferentiate a full buffer from a
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* completely empty one
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* Buffer is not allowed to be completely full, because I cannot ddifferentiate a full buffer from a completely empty one
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*/
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if (count >= buff->buffer_count) {
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ret = dma_ring_buffer_mem_to_periph_insert_data(buff, data_to_insert, buff->buffer_count - 1);
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@ -253,9 +247,7 @@ int dma_ring_buffer_mem_to_periph_insert_data(struct dma_ring_buffer_to_periph *
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/* Wait for buffer to be able to handle input */
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do {
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free_item_count = buff->buffer_count -
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calculate_ring_buffer_fill_level(buff->buffer_count, buff->dma_get_idx_current,
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buff->sw_put_idx);
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free_item_count = buff->buffer_count - calculate_ring_buffer_fill_level(buff->buffer_count, buff->dma_get_idx_current, buff->sw_put_idx);
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} while (free_item_count < count+1);
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/* Fillup buffer (max is buffer end, wrap around afterwards) */
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@ -269,7 +261,7 @@ int dma_ring_buffer_mem_to_periph_insert_data(struct dma_ring_buffer_to_periph *
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buff->sw_put_idx += count;
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/* If buffer is used up to last element, set put index to beginning */
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if (buff->sw_put_idx >= buff->buffer_count)
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if(buff->sw_put_idx >= buff->buffer_count)
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buff->sw_put_idx = 0;
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} else {
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/* Fill up to end of buffer and fill rest after wrap around */
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@ -76,14 +76,12 @@ int stm_option_bytes_program(const struct option_bytes *opts)
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reg |= (opts->read_protection << 8) & FLASH_OPTCR_RDP;
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reg |= (opts->wdg_sw << 5) & FLASH_OPTCR_WDG_SW;
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while (FLASH->SR & FLASH_SR_BSY)
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;
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while (FLASH->SR & FLASH_SR_BSY);
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FLASH->OPTCR = reg;
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FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
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__DSB();
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while (FLASH->SR & FLASH_SR_BSY)
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;
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while (FLASH->SR & FLASH_SR_BSY);
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FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
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@ -95,8 +95,9 @@ int rcc_manager_enable_clock(volatile uint32_t *rcc_enable_register, uint8_t bit
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int ret_val = 0;
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struct rcc_enable_count *entry;
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if (!rcc_enable_register || bit_no > 31)
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if (!rcc_enable_register || bit_no > 31) {
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return -1000;
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}
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/* Enable the clock in any case, no matter what follows */
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*rcc_enable_register |= (1U<<bit_no);
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@ -131,8 +132,9 @@ int rcc_manager_disable_clock(volatile uint32_t *rcc_enable_register, uint8_t bi
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int ret_val = -1;
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struct rcc_enable_count *entry;
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if (!rcc_enable_register || bit_no > 31)
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if (!rcc_enable_register || bit_no > 31) {
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return -1000;
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}
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entry = search_enable_entry_in_list(rcc_enable_register, bit_no);
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@ -30,7 +30,7 @@ void random_number_gen_init(bool int_enable)
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random_number_gen_reset(int_enable);
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}
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void random_number_gen_deinit(void)
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void random_number_gen_deinit()
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{
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RNG->CR = 0;
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__DSB();
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@ -66,5 +66,5 @@ enum random_number_error random_number_gen_get_number(uint32_t *random_number, b
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*random_number = RNG->DR;
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/* Return from function with proper status */
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return value_ready ? RNG_ERROR_OK : RNG_ERROR_NOT_READY;
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return (value_ready ? RNG_ERROR_OK : RNG_ERROR_NOT_READY);
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}
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@ -1,22 +1,22 @@
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/* Reflow Oven Controller
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*
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* Copyright (C) 2021 Mario Hüttel <mario.huettel@gmx.net>
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*
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* This file is part of the Reflow Oven Controller Project.
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*
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* The reflow oven controller is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The Reflow Oven Control Firmware is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the reflow oven controller project.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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*
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* Copyright (C) 2021 Mario Hüttel <mario.huettel@gmx.net>
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*
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* This file is part of the Reflow Oven Controller Project.
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*
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* The reflow oven controller is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The Reflow Oven Control Firmware is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
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* You should have received a copy of the GNU General Public License
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* along with the reflow oven controller project.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stm-periph/spi.h>
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#include <helper-macros/helper-macros.h>
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@ -65,8 +65,7 @@ static struct stm_spi_dev *spi_handle_to_struct(stm_spi_handle handle)
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return dev;
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}
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stm_spi_handle spi_init(struct stm_spi_dev *spi_dev_struct, SPI_TypeDef *spi_regs,
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const struct stm_spi_settings *settings)
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stm_spi_handle spi_init(struct stm_spi_dev *spi_dev_struct, SPI_TypeDef *spi_regs, const struct stm_spi_settings *settings)
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{
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stm_spi_handle ret_handle = NULL;
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uint32_t reg_val;
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@ -132,14 +131,10 @@ void spi_deinit(stm_spi_handle handle)
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static uint8_t transfer_byte(uint8_t byte, struct stm_spi_dev *dev)
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{
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while (dev->spi_regs->SR & SPI_SR_BSY)
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;
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while (dev->spi_regs->SR & SPI_SR_BSY);
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dev->spi_regs->DR = (uint16_t)byte;
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__DSB();
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while ((dev->spi_regs->SR & SPI_SR_BSY) || !(dev->spi_regs->SR & SPI_SR_TXE))
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;
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while((dev->spi_regs->SR & SPI_SR_BSY) || !(dev->spi_regs->SR & SPI_SR_TXE));
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return (uint8_t)dev->spi_regs->DR;
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}
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@ -1,227 +1,224 @@
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/* Reflow Oven Controller
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*
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* Copyright (C) 2020 Mario Hüttel <mario.huettel@gmx.net>
|
||||
*
|
||||
* This file is part of the Reflow Oven Controller Project.
|
||||
*
|
||||
* The reflow oven controller is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* The Reflow Oven Control Firmware is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with the reflow oven controller project.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
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#include <stm-periph/uart.h>
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#include <stm32/stm32f4xx.h>
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#include <stm-periph/rcc-manager.h>
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#include <stm-periph/stm32-gpio-macros.h>
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#include <stm-periph/dma-ring-buffer.h>
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#include <string.h>
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int uart_init(struct stm_uart *uart)
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{
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int ret_val = 0;
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uint32_t cr3 = 0;
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uint32_t cr1 = 0;
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if (!uart)
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return -1000;
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rcc_manager_enable_clock(uart->rcc_reg, uart->rcc_bit_no);
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/* Reset all config regs */
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uart->uart_dev->CR1 = uart->uart_dev->CR2 = uart->uart_dev->CR3 = 0UL;
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|
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/* Set baud rate */
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uart->uart_dev->BRR = uart->brr_val;
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/* If DMA buffers are present, configure for DMA use */
|
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if (uart->dma_rx_buff && uart->rx) {
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cr3 |= USART_CR3_DMAR;
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|
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ret_val = dma_ring_buffer_periph_to_mem_initialize(&uart->rx_ring_buff,
|
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uart->base_dma_num,
|
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uart->dma_rx_stream,
|
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uart->rx_buff_count,
|
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1U,
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uart->dma_rx_buff,
|
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(char *)&uart->uart_dev->DR,
|
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uart->dma_rx_trigger_channel);
|
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if (ret_val)
|
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return ret_val;
|
||||
}
|
||||
|
||||
if (uart->dma_tx_buff && uart->tx) {
|
||||
ret_val = dma_ring_buffer_mem_to_periph_initialize(&uart->tx_ring_buff,
|
||||
uart->base_dma_num,
|
||||
uart->dma_tx_stream,
|
||||
uart->tx_buff_count,
|
||||
1U,
|
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uart->dma_tx_buff,
|
||||
uart->dma_tx_trigger_channel,
|
||||
(void *)&uart->uart_dev->DR);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
cr3 |= USART_CR3_DMAT;
|
||||
}
|
||||
uart->uart_dev->CR3 = cr3;
|
||||
|
||||
if (uart->tx)
|
||||
cr1 |= USART_CR1_TE;
|
||||
if (uart->rx)
|
||||
cr1 |= USART_CR1_RE;
|
||||
|
||||
/* Enable uart */
|
||||
cr1 |= USART_CR1_UE;
|
||||
uart->uart_dev->CR1 = cr1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void uart_change_brr(struct stm_uart *uart, uint32_t brr)
|
||||
{
|
||||
if (!uart || !uart->uart_dev)
|
||||
return;
|
||||
|
||||
uart->brr_val = brr;
|
||||
uart->uart_dev->BRR = brr;
|
||||
}
|
||||
|
||||
uint32_t uart_get_brr(struct stm_uart *uart)
|
||||
{
|
||||
if (!uart || !uart->uart_dev)
|
||||
return 0;
|
||||
|
||||
return uart->brr_val;
|
||||
}
|
||||
|
||||
void uart_disable(struct stm_uart *uart)
|
||||
{
|
||||
if (!uart)
|
||||
return;
|
||||
|
||||
uart->uart_dev->CR1 = 0;
|
||||
uart->uart_dev->CR2 = 0;
|
||||
uart->uart_dev->CR3 = 0;
|
||||
|
||||
if (uart->rx && uart->dma_rx_buff)
|
||||
dma_ring_buffer_periph_to_mem_stop(&uart->rx_ring_buff);
|
||||
|
||||
if (uart->dma_tx_buff && uart->tx)
|
||||
dma_ring_buffer_mem_to_periph_stop(&uart->tx_ring_buff);
|
||||
|
||||
rcc_manager_disable_clock(uart->rcc_reg, uart->rcc_bit_no);
|
||||
}
|
||||
|
||||
void uart_send_char(struct stm_uart *uart, char c)
|
||||
{
|
||||
if (!uart || !uart->uart_dev)
|
||||
return;
|
||||
|
||||
while (!(uart->uart_dev->SR & USART_SR_TXE))
|
||||
;
|
||||
|
||||
uart->uart_dev->DR = c;
|
||||
}
|
||||
|
||||
void uart_send_array(struct stm_uart *uart, const char *data, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
uart_send_char(uart, data[i]);
|
||||
}
|
||||
|
||||
void uart_send_string(struct stm_uart *uart, const char *string)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; string[i] != '\0'; i++)
|
||||
uart_send_char(uart, string[i]);
|
||||
}
|
||||
|
||||
void uart_send_array_with_dma(struct stm_uart *uart, const char *data, uint32_t len)
|
||||
{
|
||||
if (!uart || !uart->dma_tx_buff)
|
||||
return;
|
||||
|
||||
dma_ring_buffer_mem_to_periph_insert_data(&uart->tx_ring_buff, data, len);
|
||||
}
|
||||
|
||||
void uart_send_string_with_dma(struct stm_uart *uart, const char *string)
|
||||
{
|
||||
size_t len;
|
||||
|
||||
len = strlen(string);
|
||||
uart_send_array_with_dma(uart, string, (uint32_t)len);
|
||||
}
|
||||
|
||||
int uart_receive_data_with_dma(struct stm_uart *uart, const char **data, size_t *len)
|
||||
{
|
||||
if (!uart)
|
||||
return -1000;
|
||||
|
||||
return dma_ring_buffer_periph_to_mem_get_data(&uart->rx_ring_buff, (const volatile void **)data, len);
|
||||
}
|
||||
|
||||
char uart_get_char(struct stm_uart *uart)
|
||||
{
|
||||
if (!uart)
|
||||
return 0;
|
||||
/* Wait for data to be available */
|
||||
while (!(uart->uart_dev->SR & USART_SR_RXNE))
|
||||
;
|
||||
|
||||
return (char)uart->uart_dev->DR;
|
||||
}
|
||||
|
||||
int uart_check_rx_avail(struct stm_uart *uart)
|
||||
{
|
||||
if (!uart)
|
||||
return 0;
|
||||
|
||||
if (uart->uart_dev->SR & USART_SR_RXNE)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
void uart_tx_dma_complete_int_callback(struct stm_uart *uart)
|
||||
{
|
||||
if (!uart)
|
||||
return;
|
||||
|
||||
dma_ring_buffer_mem_to_periph_int_callback(&uart->tx_ring_buff);
|
||||
}
|
||||
|
||||
size_t uart_dma_tx_queue_avail(struct stm_uart *uart)
|
||||
{
|
||||
size_t fill_level = 0UL;
|
||||
|
||||
if (!uart)
|
||||
return 0UL;
|
||||
|
||||
(void)dma_ring_buffer_mem_to_periph_fill_level(&uart->tx_ring_buff, &fill_level);
|
||||
|
||||
return fill_level;
|
||||
}
|
||||
|
||||
size_t uart_dma_rx_queue_avail(struct stm_uart *uart)
|
||||
{
|
||||
size_t fill_level = 0UL;
|
||||
|
||||
if (!uart)
|
||||
return 0UL;
|
||||
|
||||
(void)dma_ring_buffer_periph_to_mem_fill_level(&uart->rx_ring_buff, &fill_level);
|
||||
|
||||
return fill_level;
|
||||
}
|
||||
/* Reflow Oven Controller
|
||||
*
|
||||
* Copyright (C) 2020 Mario Hüttel <mario.huettel@gmx.net>
|
||||
*
|
||||
* This file is part of the Reflow Oven Controller Project.
|
||||
*
|
||||
* The reflow oven controller is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* The Reflow Oven Control Firmware is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with the reflow oven controller project.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stm-periph/uart.h>
|
||||
#include <stm32/stm32f4xx.h>
|
||||
#include <stm-periph/rcc-manager.h>
|
||||
#include <stm-periph/stm32-gpio-macros.h>
|
||||
#include <stm-periph/dma-ring-buffer.h>
|
||||
#include <string.h>
|
||||
|
||||
int uart_init(struct stm_uart *uart)
|
||||
{
|
||||
int ret_val = 0;
|
||||
uint32_t cr3 = 0;
|
||||
uint32_t cr1 = 0;
|
||||
|
||||
if (!uart)
|
||||
return -1000;
|
||||
|
||||
rcc_manager_enable_clock(uart->rcc_reg, uart->rcc_bit_no);
|
||||
|
||||
/* Reset all config regs */
|
||||
uart->uart_dev->CR1 = uart->uart_dev->CR2 = uart->uart_dev->CR3 = 0UL;
|
||||
|
||||
/* Set baud rate */
|
||||
uart->uart_dev->BRR = uart->brr_val;
|
||||
|
||||
/* If DMA buffers are present, configure for DMA use */
|
||||
if (uart->dma_rx_buff && uart->rx) {
|
||||
cr3 |= USART_CR3_DMAR;
|
||||
|
||||
ret_val = dma_ring_buffer_periph_to_mem_initialize(&uart->rx_ring_buff,
|
||||
uart->base_dma_num,
|
||||
uart->dma_rx_stream,
|
||||
uart->rx_buff_count,
|
||||
1U,
|
||||
uart->dma_rx_buff,
|
||||
(char *)&uart->uart_dev->DR,
|
||||
uart->dma_rx_trigger_channel);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
if (uart->dma_tx_buff && uart->tx) {
|
||||
ret_val = dma_ring_buffer_mem_to_periph_initialize(&uart->tx_ring_buff,
|
||||
uart->base_dma_num,
|
||||
uart->dma_tx_stream,
|
||||
uart->tx_buff_count,
|
||||
1U,
|
||||
uart->dma_tx_buff,
|
||||
uart->dma_tx_trigger_channel,
|
||||
(void *)&uart->uart_dev->DR);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
cr3 |= USART_CR3_DMAT;
|
||||
}
|
||||
uart->uart_dev->CR3 = cr3;
|
||||
|
||||
if (uart->tx)
|
||||
cr1 |= USART_CR1_TE;
|
||||
if (uart->rx)
|
||||
cr1 |= USART_CR1_RE;
|
||||
|
||||
/* Enable uart */
|
||||
cr1 |= USART_CR1_UE;
|
||||
uart->uart_dev->CR1 = cr1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void uart_change_brr(struct stm_uart *uart, uint32_t brr)
|
||||
{
|
||||
if (!uart || !uart->uart_dev)
|
||||
return;
|
||||
|
||||
uart->brr_val = brr;
|
||||
uart->uart_dev->BRR = brr;
|
||||
}
|
||||
|
||||
uint32_t uart_get_brr(struct stm_uart *uart)
|
||||
{
|
||||
if (!uart || !uart->uart_dev)
|
||||
return 0;
|
||||
|
||||
return uart->brr_val;
|
||||
}
|
||||
|
||||
void uart_disable(struct stm_uart *uart)
|
||||
{
|
||||
if (!uart)
|
||||
return;
|
||||
|
||||
uart->uart_dev->CR1 = 0;
|
||||
uart->uart_dev->CR2 = 0;
|
||||
uart->uart_dev->CR3 = 0;
|
||||
|
||||
if (uart->rx && uart->dma_rx_buff)
|
||||
dma_ring_buffer_periph_to_mem_stop(&uart->rx_ring_buff);
|
||||
|
||||
if (uart->dma_tx_buff && uart->tx)
|
||||
dma_ring_buffer_mem_to_periph_stop(&uart->tx_ring_buff);
|
||||
|
||||
rcc_manager_disable_clock(uart->rcc_reg, uart->rcc_bit_no);
|
||||
}
|
||||
|
||||
void uart_send_char(struct stm_uart *uart, char c)
|
||||
{
|
||||
if (!uart || !uart->uart_dev)
|
||||
return;
|
||||
|
||||
while(!(uart->uart_dev->SR & USART_SR_TXE));
|
||||
uart->uart_dev->DR = c;
|
||||
}
|
||||
|
||||
void uart_send_array(struct stm_uart *uart, const char *data, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
uart_send_char(uart, data[i]);
|
||||
}
|
||||
|
||||
void uart_send_string(struct stm_uart *uart, const char *string)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; string[i] != '\0'; i++)
|
||||
uart_send_char(uart, string[i]);
|
||||
}
|
||||
|
||||
void uart_send_array_with_dma(struct stm_uart *uart, const char *data, uint32_t len)
|
||||
{
|
||||
if (!uart || !uart->dma_tx_buff)
|
||||
return;
|
||||
|
||||
dma_ring_buffer_mem_to_periph_insert_data(&uart->tx_ring_buff, data, len);
|
||||
}
|
||||
|
||||
void uart_send_string_with_dma(struct stm_uart *uart, const char *string)
|
||||
{
|
||||
size_t len;
|
||||
|
||||
len = strlen(string);
|
||||
uart_send_array_with_dma(uart, string, (uint32_t)len);
|
||||
}
|
||||
|
||||
int uart_receive_data_with_dma(struct stm_uart *uart, const char **data, size_t *len)
|
||||
{
|
||||
if (!uart)
|
||||
return -1000;
|
||||
|
||||
return dma_ring_buffer_periph_to_mem_get_data(&uart->rx_ring_buff, (const volatile void **)data, len);
|
||||
}
|
||||
|
||||
char uart_get_char(struct stm_uart *uart)
|
||||
{
|
||||
if (!uart)
|
||||
return 0;
|
||||
/* Wait for data to be available */
|
||||
while (!(uart->uart_dev->SR & USART_SR_RXNE));
|
||||
|
||||
return (char)uart->uart_dev->DR;
|
||||
}
|
||||
|
||||
int uart_check_rx_avail(struct stm_uart *uart)
|
||||
{
|
||||
if (!uart)
|
||||
return 0;
|
||||
|
||||
if (uart->uart_dev->SR & USART_SR_RXNE)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
void uart_tx_dma_complete_int_callback(struct stm_uart *uart)
|
||||
{
|
||||
if (!uart)
|
||||
return;
|
||||
|
||||
dma_ring_buffer_mem_to_periph_int_callback(&uart->tx_ring_buff);
|
||||
}
|
||||
|
||||
size_t uart_dma_tx_queue_avail(struct stm_uart *uart)
|
||||
{
|
||||
size_t fill_level = 0UL;
|
||||
|
||||
if (!uart)
|
||||
return 0UL;
|
||||
|
||||
(void)dma_ring_buffer_mem_to_periph_fill_level(&uart->tx_ring_buff, &fill_level);
|
||||
|
||||
return fill_level;
|
||||
}
|
||||
|
||||
size_t uart_dma_rx_queue_avail(struct stm_uart *uart)
|
||||
{
|
||||
size_t fill_level = 0UL;
|
||||
|
||||
if (!uart)
|
||||
return 0UL;
|
||||
|
||||
(void)dma_ring_buffer_periph_to_mem_fill_level(&uart->rx_ring_buff, &fill_level);
|
||||
|
||||
return fill_level;
|
||||
}
|
||||
|
||||
@ -50,16 +50,16 @@ void stm_cpuid_get(uint8_t *implementer, uint8_t *variant, uint16_t *part_no, ui
|
||||
|
||||
cpuid = SCB->CPUID;
|
||||
|
||||
if (implementer)
|
||||
if (implementer) {
|
||||
*implementer = (uint8_t)((cpuid >> 24) & 0xFFU);
|
||||
|
||||
if (variant)
|
||||
}
|
||||
if (variant) {
|
||||
*variant = (uint8_t)((cpuid >> 20) & 0x0FU);
|
||||
|
||||
if (part_no)
|
||||
}
|
||||
if (part_no) {
|
||||
*part_no = (uint16_t)((cpuid >> 4) & 0x0FFFU);
|
||||
|
||||
if (rev)
|
||||
}
|
||||
if (rev) {
|
||||
*rev = (uint8_t)(cpuid & 0x0FU);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user