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2 Commits
ba8072c21d
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48f69d0fb5
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48f69d0fb5 | |||
8fd924829e |
@ -26,7 +26,7 @@
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extern char __ld_top_of_stack;
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extern char __ld_top_of_stack;
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extern char __ld_end_stack;
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extern char __ld_end_stack;
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int32_t stack_check_get_usage()
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int32_t stack_check_get_usage(void)
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{
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{
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uint32_t stack_top;
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uint32_t stack_top;
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uint32_t stack_ptr;
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uint32_t stack_ptr;
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@ -37,7 +37,7 @@ int32_t stack_check_get_usage()
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return stack_top - stack_ptr;
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return stack_top - stack_ptr;
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}
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}
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int32_t stack_check_get_free()
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int32_t stack_check_get_free(void)
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{
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{
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uint32_t upper_heap_boundary;
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uint32_t upper_heap_boundary;
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uint32_t stack_ptr;
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uint32_t stack_ptr;
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@ -102,9 +102,6 @@ int stack_check_corruption_detect_area(void)
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&__ld_start_stack_corruption_detect_area;
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&__ld_start_stack_corruption_detect_area;
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crc_unit_reset();
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crc_unit_reset();
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crc_unit_input_array(&__ld_start_stack_corruption_detect_area, area_size_in_words);
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crc_unit_input_array(&__ld_start_stack_corruption_detect_area, area_size_in_words);
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if (crc_unit_get_crc() == 0UL) {
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return 0;
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return crc_unit_get_crc() == 0UL ? 0 : -1;
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} else {
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return -1;
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}
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}
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}
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@ -50,7 +50,8 @@ int watchdog_setup(uint8_t prescaler)
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RCC->CSR |= RCC_CSR_LSION;
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RCC->CSR |= RCC_CSR_LSION;
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__DSB();
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__DSB();
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/** - Wait for the oscillator to be ready */
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/** - Wait for the oscillator to be ready */
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while (!(RCC->CSR & RCC_CSR_LSIRDY));
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while (!(RCC->CSR & RCC_CSR_LSIRDY))
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;
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if (prescaler == 4U)
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if (prescaler == 4U)
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prescaler_reg_val = 0UL;
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prescaler_reg_val = 0UL;
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@ -68,23 +69,24 @@ int watchdog_setup(uint8_t prescaler)
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prescaler_reg_val = 6UL;
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prescaler_reg_val = 6UL;
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/** - (De)activate the watchdog during debug access according to @ref WATCHDOG_HALT_DEBUG */
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/** - (De)activate the watchdog during debug access according to @ref WATCHDOG_HALT_DEBUG */
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if (WATCHDOG_HALT_DEBUG) {
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if (WATCHDOG_HALT_DEBUG)
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DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_IWDG_STOP;
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DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_IWDG_STOP;
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} else {
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else
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DBGMCU->APB1FZ &= ~DBGMCU_APB1_FZ_DBG_IWDG_STOP;
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DBGMCU->APB1FZ &= ~DBGMCU_APB1_FZ_DBG_IWDG_STOP;
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}
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/** - Unlock registers */
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/** - Unlock registers */
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IWDG->KR = STM32_WATCHDOG_REGISTER_ACCESS_KEY;
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IWDG->KR = STM32_WATCHDOG_REGISTER_ACCESS_KEY;
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/** - Wait until prescaler can be written */
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/** - Wait until prescaler can be written */
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while (IWDG->SR & IWDG_SR_PVU);
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while (IWDG->SR & IWDG_SR_PVU)
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;
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/** - Write prescaler value */
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/** - Write prescaler value */
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IWDG->PR = prescaler_reg_val;
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IWDG->PR = prescaler_reg_val;
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/* - Wait until reload value can be written */
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/* - Wait until reload value can be written */
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while (IWDG->SR & IWDG_SR_RVU);
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while (IWDG->SR & IWDG_SR_RVU)
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;
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/** - Set reload value fixed to 0xFFF */
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/** - Set reload value fixed to 0xFFF */
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IWDG->RLR = 0xFFFU;
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IWDG->RLR = 0xFFFU;
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