/* Reflow Oven Controller
 *
 * Copyright (C) 2020  Mario Hüttel <mario.huettel@gmx.net>
 *
 * This file is part of the Reflow Oven Controller Project.
 *
 * The reflow oven controller is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * GDSII-Converter is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with the reflow oven controller project.
 * If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __RCC_MANAGER_H__
#define __RCC_MANAGER_H__

#include <stdint.h>
#include <stm-periph/stm32-gpio-macros.h>
#include <stdbool.h>

/**
 * @brief The RCC Enable Manager uses static memory with a fixed maximum
 */
#define RCC_ENABLE_MANAGER_STATIC 1U

#if RCC_ENABLE_MANAGER_STATIC
#define RCC_ENABLE_MANAGER_COUNT 30U
#else
#error "RCC Enable Manager not yet implemented with dynamic memory"
#endif

/**
 * @brief The source/cause of a system reset. The values can be or'ed together as multiple flags may be possible at the same time.
 */
enum rcc_reset_source {
	RCC_RESET_SOURCE_LOW_POWER = (1<<0),	/**< @brief System reset caused by low power reset */
	RCC_RESET_SOURCE_SOFTWARE = (1<<1),	/**< @brief System reset caused by software */
	RCC_RESET_SOURCE_WWD = (1<<2),		/**< @brief System reset caused by window watchdog */
	RCC_RESET_SOURCE_IWDG = (1<<3),		/**< @brief System reset caused by independent watchdog */
	RCC_RESET_SOURCE_POWER_ON = (1<<4),	/**< @brief System reset caused by power on reset (POR) */
	RCC_RESET_SOURCE_PIN = (1<<5),		/**< @brief System reset caused by NRST pin */
	RCC_RESET_BOR_POR = (1<<6),		/**< @brief System reset caused by eitehr brown out or POR */
};

/**
 * @brief Enable Clock for peripheral by setting the corresponding bit (@p bit_no) to one
 *
 * This function also keeps a enable count on each bit that is set, in order to allow nested enables/disables
 *
 * If there is no more space to track a new register bit in memory (either due to the static limit or due to no remaining heap space),
 * the function still enables the peripheral clock but does not track it and returns -1
 *
 * @param rcc_enable_register
 * @param bit_no
 *
 * @return 0 if successful
 */
int rcc_manager_enable_clock(volatile uint32_t *rcc_enable_register, uint8_t bit_no);

/**
 * @brief Disable clock for peripheral and decrement the enaböe-counter of that bit.
 *
 * If there is no bit entry in the counting table yet, teh peripheral clock is not disabled and error code
 * -1 is returned.
 *
 * If the count reaches zero, the element is removed from the list to make room for new ones
 *
 * @param rcc_enable_register Register to disable the bit in
 * @param bit_no Bit number (0 to 31) of the bit to disable
 * @return 0 if successful
 */
int rcc_manager_disable_clock(volatile uint32_t *rcc_enable_register, uint8_t bit_no);

/**
 * @brief Get the causes of the last system reset.
 * @param clear_flags Clear the reset cause
 * @return Reset cause
 */
enum rcc_reset_source rcc_manager_get_reset_cause(bool clear_flags);

#endif /* __RCC_MANAGER_H__ */