#ifndef FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_CONFIG_H_
#define FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_CONFIG_H_

#include <stm32/stm32f4xx.h>

#define SDIO_CLOCK_FREQ 42000000UL

//General Definitions
//Blocksize: 512 = 2^9 => 9
#define BLOCKSIZE 9     //9
//Hardware Flow: Prevents over- and underruns.
#define HW_FLOW   0     //0
//1 bit: !=4
//4 bit: 4
#define BUSWIDTH  4    //4
//Initial Transfer CLK (ca. 400kHz)
#define INITCLK   140UL   //120
//Working CLK (Maximum)
#define WORKCLK   30UL   //0
//Data Timeout in CLK Cycles

#define DATA_TIMEOUT_MS 250UL // 250

#define DTIMEOUT  (((SDIO_CLOCK_FREQ / (WORKCLK+2))) * DATA_TIMEOUT_MS / 1000UL)
//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
// Currently not used due to possible misalignment of the data buffer.
//#define DMASTREAM DMA2_Stream6


/* Port Definitions */

#define PORTCLKMASK (RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIOAEN)

#define ALTFUNC     12

#define CLKPORT     GPIOC
#define D0PORT      GPIOC
#define D1PORT      GPIOC
#define D2PORT      GPIOC
#define D3PORT      GPIOC
#define CMDPORT     GPIOD

#define CLKPIN      12
#define D0PIN       8
#define D1PIN       9
#define D2PIN       10
#define D3PIN       11
#define CMDPIN      2

// Write Protection
#define SDIO_ENABLE_WRITEPROT 0
#define WRITEPROT_PORT GPIOD // Add this port to port clock mask!
#define WRITEPROT_PIN 0
#define WRITEPROT_PULLUP 0
#define WRITEPROT_ACTIVE_LEVEL 0

// Card inserted pin
#define SDIO_ENABLE_INS 1
#define INS_PORT GPIOA // Add this port to port clock mask!
#define INS_PIN 8
#define INS_PULLUP 1
#define INS_ACTIVE_LEVEL 0


#endif /* FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_CONFIG_H_ */