129 lines
2.5 KiB
C
129 lines
2.5 KiB
C
/*
|
|
* main.c
|
|
*
|
|
* Created on: Apr 25, 2015
|
|
* Author: mari
|
|
*/
|
|
#include <stm32f4xx.h>
|
|
#include <systick.h>
|
|
//#include <arm_math.h>
|
|
#include <system_stm32f4xx.h>
|
|
#include <stdlib.h>
|
|
#include <string.h>
|
|
#include <adc-meas.h>
|
|
|
|
#define OUTPUT(pin) (0b01 << (pin * 2))
|
|
#define ANALOG(pin) (0x03 << (pin * 2))
|
|
|
|
struct adc_conversions {
|
|
uint16_t pa2_raw;
|
|
uint16_t ref_raw;
|
|
uint16_t temp_raw;
|
|
uint16_t vbat_raw;
|
|
};
|
|
|
|
static volatile struct adc_conversions adc_results;
|
|
|
|
volatile uint64_t sample_count = 0;
|
|
volatile uint8_t new_data = 0;
|
|
|
|
|
|
void DMA2_Stream0_IRQHandler()
|
|
{
|
|
uint32_t lisr;
|
|
|
|
lisr = DMA2->LISR;
|
|
DMA2->LIFCR = lisr;
|
|
|
|
if (lisr & DMA_LISR_TCIF0) {
|
|
if (new_data)
|
|
new_data = 2;
|
|
new_data = 1;
|
|
sample_count++;
|
|
|
|
GPIOB->ODR ^= (1<<3);
|
|
}
|
|
|
|
}
|
|
|
|
void setup_dma(void *dest, size_t size)
|
|
{
|
|
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
|
|
|
|
DMA2_Stream0->M0AR = (uint32_t)dest;
|
|
DMA2_Stream0->PAR = (uint32_t)&ADC1->DR;
|
|
DMA2_Stream0->CR = DMA_SxCR_PL_1 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC |
|
|
DMA_SxCR_CIRC | DMA_SxCR_TCIE;
|
|
DMA2_Stream0->NDTR = size;
|
|
NVIC_EnableIRQ(DMA2_Stream0_IRQn);
|
|
|
|
DMA2_Stream0->CR |= DMA_SxCR_EN;
|
|
new_data = 0;
|
|
}
|
|
|
|
float ext_lf_corr;
|
|
|
|
float temp_lf_corr;
|
|
|
|
float ref_lf;
|
|
float vdd_calculated = 3.3f;
|
|
|
|
float vbat_lf_corr;
|
|
|
|
|
|
|
|
static void setup_timers(void)
|
|
{
|
|
}
|
|
|
|
|
|
int main() {
|
|
struct adc_conversions working;
|
|
|
|
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
|
|
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
|
|
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
|
|
__DSB();
|
|
GPIOB->MODER = OUTPUT(2) | OUTPUT(3);
|
|
GPIOA->MODER |= ANALOG(2);
|
|
GPIOB->ODR |= (1<<2);
|
|
|
|
ADC1->SMPR2 = (7U<<(3*2));
|
|
ADC1->SMPR1 = (7U<<18) | (7U<<21) | (7U<<24);
|
|
ADC1->SQR1 = (2<<20);
|
|
ADC1->SQR3 = (2<<0) | (16<<(5*2)) | (17<<(5*1));
|
|
|
|
ADC->CCR |= (0x2<<16) | ADC_CCR_TSVREFE;
|
|
ADC1->CR1 = ADC_CR1_SCAN;
|
|
ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS;
|
|
|
|
//while(1);
|
|
|
|
systick_setup();
|
|
|
|
setup_dma(&adc_results, 3);
|
|
adc_pt1000_setup_meas();
|
|
|
|
ADC1->CR2 |= ADC_CR2_SWSTART;
|
|
|
|
while(1) {
|
|
if (!new_data) {
|
|
continue;
|
|
}
|
|
|
|
|
|
memcpy(&working, &adc_results, sizeof(adc_results));
|
|
new_data = 0;
|
|
//ref_lf = 0.995f * ref_lf + 0.005f * (float)working.ref_raw;
|
|
//vdd_calculated = ((1.21f * 4096)/ ref_lf);
|
|
|
|
//temp_lf_corr = 0.99f * temp_lf_corr + 0.01 * (float)working.temp_raw * vdd_calculated / 2.495f;
|
|
ext_lf_corr = 0.995f * ext_lf_corr + 0.005f * (float)working.pa2_raw / 4096 * 2500.0f; // * vdd_calculated / 2.495f;
|
|
|
|
//vbat_lf_corr = 0.99 * vbat_lf_corr + 0.01 * (float)working.vbat_raw / 4096 * vdd_calculated * 2.0f;
|
|
}
|
|
|
|
}
|
|
|
|
|