388 lines
9.6 KiB
C
388 lines
9.6 KiB
C
/* Reflow Oven Controller
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*
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* Copyright (C) 2020 Mario Hüttel <mario.huettel@gmx.net>
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*
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* This file is part of the Reflow Oven Controller Project.
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*
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* The reflow oven controller is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The Reflow Oven Control Firmware is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the reflow oven controller project.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <reflow-controller/adc-meas.h>
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#include <stm32/stm32f4xx.h>
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#include <cmsis/core_cm4.h>
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#include <stm-periph/stm32-gpio-macros.h>
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#include <stdlib.h>
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#include <stm-periph/clock-enable-manager.h>
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static float pt1000_offset;
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static float pt1000_sens_dev;
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static bool calibration_active;
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static float filter_alpha;
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static volatile float pt1000_res_raw_lf;
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static volatile bool filter_ready;
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static volatile enum adc_pt1000_error pt1000_error = ADC_PT1000_INACTIVE;
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static volatile int * volatile streaming_flag_ptr = NULL;
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static uint32_t filter_startup_cnt;
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static volatile float adc_pt1000_raw_reading_hf;
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static volatile uint16_t dma_sample_buffer[ADC_PT1000_DMA_AVG_SAMPLES];
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volatile float * volatile stream_buffer = NULL;
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volatile uint32_t stream_count;
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volatile uint32_t stream_pos;
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#define ADC_TO_RES(adc) ((float)(adc) / 4096.0f * 2500.0f)
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static inline void adc_pt1000_stop_sample_frequency_timer()
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{
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TIM2->CR1 &= ~TIM_CR1_CEN;
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rcc_manager_disable_clock(&RCC->APB1ENR, BITMASK_TO_BITNO(RCC_APB1ENR_TIM2EN));
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}
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static inline void adc_pt1000_setup_sample_frequency_timer()
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{
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rcc_manager_enable_clock(&RCC->APB1ENR, BITMASK_TO_BITNO(RCC_APB1ENR_TIM2EN));
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/* Divide 42 MHz peripheral clock by 42 */
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TIM2->PSC = (42UL-1UL);
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/* Reload value */
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TIM2->ARR = ADC_PT1000_SAMPLE_CNT_DELAY;
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/* Trigger output at update event */
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TIM2->CR2 = TIM_CR2_MMS_1;
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/* Start Timer in downcounting mode with autoreload */
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TIM2->CR1 = TIM_CR1_DIR | TIM_CR1_CEN;
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}
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static inline void adc_pt1000_disable_adc()
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{
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ADC1->CR2 &= ~ADC_CR2_ADON;
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DMA2_Stream0->CR = 0;
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pt1000_error |= ADC_PT1000_INACTIVE;
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rcc_manager_disable_clock(&RCC->APB2ENR, BITMASK_TO_BITNO(RCC_APB2ENR_ADC1EN));
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rcc_manager_disable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(ADC_PT1000_PORT_RCC_MASK));
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}
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/**
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* @brief Enable DMA Stream for ADC
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*
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* DMA2 Stream 0 is used. It will capture @ref ADC_PT1000_DMA_AVG_SAMPLES measurement values,
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* delete the two most extreme values
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* and calculate the avereage over the remaining values. This ensures, that one time errors are
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* not included in the measurement.
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*
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* After that, the moving average filter is fed with the values.
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*
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*/
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static inline void adc_pt1000_enable_dma_stream()
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{
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/* Enable peripheral clock for DMA2 */
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rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA2EN));
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/* Destination is the DMA sample buffer */
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DMA2_Stream0->M0AR = (uint32_t)dma_sample_buffer;
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/* Source is the ADC data register */
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DMA2_Stream0->PAR = (uint32_t)&ADC1->DR;
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/* Transfer size is ADC_PT1000_DMA_AVG_SAMPLES */
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DMA2_Stream0->NDTR = ADC_PT1000_DMA_AVG_SAMPLES;
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NVIC_EnableIRQ(DMA2_Stream0_IRQn);
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/* Enable the stream in Peripheral-to-Memory mode with 16 bit data and a circular destination buffer
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* Enable interrupt generation on transfer complete
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*
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* Todo: Maybe use twice as big of a buffer and also use half-fill interrupt in order to prevent overruns
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*/
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DMA2_Stream0->CR = DMA_SxCR_PL_1 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC |
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DMA_SxCR_CIRC | DMA_SxCR_TCIE | DMA_SxCR_TEIE | DMA_SxCR_EN;
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}
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static inline void adc_pt1000_disable_dma_stream()
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{
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/* Disable the stream */
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DMA2_Stream0->CR = 0;
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/* Disable clock if necessary */
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rcc_manager_disable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA2EN));
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/* Disable interrupt */
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NVIC_DisableIRQ(DMA2_Stream0_IRQn);
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}
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void adc_pt1000_setup_meas()
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{
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rcc_manager_enable_clock(&RCC->APB2ENR, BITMASK_TO_BITNO(RCC_APB2ENR_ADC1EN));
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rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(ADC_PT1000_PORT_RCC_MASK));
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ADC_PT1000_PORT->MODER |= ANALOG(ADC_PT1000_PIN);
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/* Set S&H time for PT1000 ADC channel */
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#if ADC_PT1000_CHANNEL < 10
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ADC1->SMPR2 |= (7U << (3*ADC_PT1000_CHANNEL));
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#else
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ADC1->SMPR1 |= (7U << (3*(ADC_PT1000_CHANNEL-10)));
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#endif
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ADC->CCR |= (0x2<<16);
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/* Set watchdog limits */
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ADC1->HTR = ADC_PT1000_UPPER_WATCHDOG;
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ADC1->LTR = ADC_PT1000_LOWER_WATCHDOG;
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/* Set length of sequence to 1 */
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ADC1->SQR1 = (0UL<<20);
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/* Set channel as 1st element in sequence */
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ADC1->SQR3 = (ADC_PT1000_CHANNEL<<0);
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ADC1->CR1 = ADC_CR1_OVRIE | ADC_CR1_AWDEN | ADC_CR1_AWDIE;
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ADC1->CR2 = ADC_CR2_EXTEN_0 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_DDS;
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adc_pt1000_set_moving_average_filter_param(ADC_PT1000_FILTER_WEIGHT);
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adc_pt1000_set_resistance_calibration(0, 0, false);
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pt1000_res_raw_lf = 0.0f;
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NVIC_EnableIRQ(ADC_IRQn);
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adc_pt1000_enable_dma_stream();
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adc_pt1000_setup_sample_frequency_timer();
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pt1000_error &= ~ADC_PT1000_INACTIVE;
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}
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void adc_pt1000_set_moving_average_filter_param(float alpha)
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{
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filter_alpha = alpha;
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filter_ready = false;
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filter_startup_cnt = ADC_FILTER_STARTUP_CYCLES;
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}
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void adc_pt1000_set_resistance_calibration(float offset, float sensitivity_deviation, bool active)
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{
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pt1000_offset = offset;
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pt1000_sens_dev = sensitivity_deviation;
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calibration_active = active;
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}
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void adc_pt1000_get_resistance_calibration(float *offset, float *sensitivity_deviation, bool *active)
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{
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if (!offset || !sensitivity_deviation || !active)
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return;
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*offset = pt1000_offset;
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*sensitivity_deviation = pt1000_sens_dev;
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*active = calibration_active;
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}
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static inline float adc_pt1000_apply_calibration(float raw_resistance)
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{
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if (calibration_active)
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return pt1000_res_raw_lf * (1.0f + pt1000_sens_dev) + pt1000_offset;
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else
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return raw_resistance;
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}
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int adc_pt1000_get_current_resistance(float *resistance)
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{
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int ret_val = 0;
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if (!resistance)
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return -1001;
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*resistance = adc_pt1000_apply_calibration(pt1000_res_raw_lf);
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if (adc_pt1000_check_error()) {
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ret_val = -100;
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goto return_value;
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}
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if (!filter_ready) {
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ret_val = 2;
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goto return_value;
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}
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return_value:
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return ret_val;
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}
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int adc_pt1000_stream_raw_value_to_memory(volatile float *adc_array, uint32_t length, volatile int *flag_to_set)
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{
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int ret = 0;
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if (!flag_to_set)
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return -1;
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stream_buffer = adc_array;
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stream_count = length;
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stream_pos = 0U;
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if (adc_array) {
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*flag_to_set = 0;
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streaming_flag_ptr = flag_to_set;
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} else {
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ret = -2;
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}
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return ret;
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}
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void adc_pt1000_convert_raw_value_array_to_resistance(float *resistance_dest, float *raw_source, uint32_t count)
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{
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uint32_t i;
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if (!resistance_dest)
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resistance_dest = raw_source;
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if (!raw_source || !count)
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return;
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for (i = 0; i < count; i++)
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resistance_dest[i] = ADC_TO_RES(raw_source[i]);
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}
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enum adc_pt1000_error adc_pt1000_check_error()
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{
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return pt1000_error;
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}
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void adc_pt1000_clear_error()
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{
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pt1000_error &= ~ADC_PT1000_OVERFLOW & ~ADC_PT1000_WATCHDOG_ERROR;
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}
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void adc_pt1000_disable()
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{
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adc_pt1000_disable_adc();
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adc_pt1000_stop_sample_frequency_timer();
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adc_pt1000_disable_dma_stream();
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filter_ready = false;
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pt1000_res_raw_lf = 0.0f;
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pt1000_error |= ADC_PT1000_INACTIVE;
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if (streaming_flag_ptr) {
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*streaming_flag_ptr = -3;
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streaming_flag_ptr = NULL;
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}
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}
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static inline __attribute__((optimize("O3"))) void adc_pt1000_filter(float adc_prefiltered_value)
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{
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if (!filter_ready && --filter_startup_cnt <= 0)
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filter_ready = true;
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pt1000_res_raw_lf = (1.0f-filter_alpha) * pt1000_res_raw_lf + filter_alpha * ADC_TO_RES(adc_prefiltered_value);
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}
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static inline __attribute__((optimize("O3"))) float adc_pt1000_dma_avg_pre_filter()
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{
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unsigned int i;
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uint32_t sum = 0;
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uint16_t max_val = 0U;
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uint16_t min_val = 65535U;
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uint16_t sample;
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for (i = 0; i < ADC_PT1000_DMA_AVG_SAMPLES; i++) {
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sample = dma_sample_buffer[i];
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/* Update min and max trackers */
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max_val = (sample > max_val ? sample : max_val);
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min_val = (sample < min_val ? sample : min_val);
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/* Sum up all values (for average) */
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sum += sample;
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}
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/* Delete max and min vals from sum */
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sum = sum - (uint32_t)max_val - (uint32_t)min_val;
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/* Divide to get average and return */
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return (float)sum / (float)(ADC_PT1000_DMA_AVG_SAMPLES-2);
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}
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void ADC_IRQHandler(void)
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{
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uint32_t adc1_sr;
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static uint32_t watchdog_errors;
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adc1_sr = ADC1->SR;
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if (adc1_sr & ADC_SR_OVR) {
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ADC1->SR &= ~ADC_SR_OVR;
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pt1000_error |= ADC_PT1000_OVERFLOW;
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/* Disable ADC in case of overrrun*/
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adc_pt1000_disable();
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if (!(adc1_sr & ADC_SR_AWD)) {
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watchdog_errors = 0;
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}
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}
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if (adc1_sr & ADC_SR_AWD) {
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ADC1->SR &= ~ADC_SR_AWD;
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watchdog_errors++;
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if (watchdog_errors >= ADC_PT1000_WATCHDOG_SAMPLE_COUNT)
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pt1000_error |= ADC_PT1000_WATCHDOG_ERROR;
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}
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}
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static void append_stream_buffer(float val)
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{
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if (!stream_buffer || !streaming_flag_ptr)
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return;
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if (stream_pos < stream_count)
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stream_buffer[stream_pos++] = val;
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if (stream_pos >= stream_count) {
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*streaming_flag_ptr = 1;
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streaming_flag_ptr = NULL;
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}
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}
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void DMA2_Stream0_IRQHandler()
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{
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uint32_t lisr;
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float adc_val;
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lisr = DMA2->LISR;
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DMA2->LIFCR = lisr;
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if (lisr & DMA_LISR_TCIF0) {
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/* Samples Transfered */
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adc_val = adc_pt1000_dma_avg_pre_filter();
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adc_pt1000_raw_reading_hf = adc_val;
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if (streaming_flag_ptr)
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append_stream_buffer(adc_val);
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/* Call moving average filter */
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adc_pt1000_filter(adc_val);
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}
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if (lisr & DMA_LISR_TEIF0) {
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adc_pt1000_disable();
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}
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}
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