116 lines
2.8 KiB
C
116 lines
2.8 KiB
C
/* Reflow Oven Controller
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*
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* Copyright (C) 2020 Mario Hüttel <mario.huettel@gmx.net>
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*
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* This file is part of the Reflow Oven Controller Project.
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*
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* The reflow oven controller is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The Reflow Oven Control Firmware is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the reflow oven controller project.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stm-periph/backup-ram.h>
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#include <stm-periph/rcc-manager.h>
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#include <stm32/stm32f4xx.h>
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#include <helper-macros/helper-macros.h>
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#define BACKUP_RAM_BASE BKPSRAM_BASE
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#define BACKUP_RAM_SIZE 4096U
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#define BACKUP_RAM_SIZE_WORDS (BACKUP_RAM_SIZE / 4U)
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#define BACKUP_RAM_END_ADDR (BACKUP_RAM_BASE + BACKUP_RAM_SIZE - 1U)
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#define backup_ram ((volatile uint32_t *)BACKUP_RAM_BASE)
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#if !is_power_of_two(BACKUP_RAM_SIZE)
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#error "Backup RAM size ahs to be a power of two!"
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#endif
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void backup_ram_init(bool use_backup_regulator)
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{
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rcc_manager_enable_clock(&RCC->APB1ENR, BITMASK_TO_BITNO(RCC_APB1ENR_PWREN));
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/* Enable access to backup RAM register set */
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PWR->CR |= PWR_CR_DBP;
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if (use_backup_regulator) {
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/* Enable the backup regulator */
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PWR->CSR |= PWR_CSR_BRE;
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/* Wait until regulator is ready */
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while (!(PWR->CSR & PWR_CSR_BRR))
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;
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}
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/* Enable clock for backup ram interface */
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rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_BKPSRAMEN));
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}
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void backup_ram_disable(void)
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{
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/* Disable access to backup RAM register set */
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PWR->CR &= ~PWR_CR_DBP;
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rcc_manager_disable_clock(&RCC->APB1ENR, BITMASK_TO_BITNO(RCC_APB1ENR_PWREN));
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rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_BKPSRAMEN));
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}
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void backup_ram_wipe(void)
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{
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uint32_t i;
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for (i = 0; i < BACKUP_RAM_SIZE_WORDS; i++)
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backup_ram[i] = 0UL;
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}
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int backup_ram_get_data(uint32_t addr, uint32_t *data, uint32_t count)
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{
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volatile uint32_t *ptr;
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if (!data)
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return -1002;
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if (addr >= BACKUP_RAM_SIZE_WORDS)
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return -1001;
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ptr = &backup_ram[addr];
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for (; count > 0; count--)
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*(data++) = *(ptr++);
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return 0;
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}
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int backup_ram_write_data(uint32_t addr, const uint32_t *data, uint32_t count)
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{
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volatile uint32_t *ptr;
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if (!data)
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return -1002;
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if (addr >= BACKUP_RAM_SIZE_WORDS)
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return -1001;
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ptr = &backup_ram[addr];
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for (; count > 0; count--)
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*(ptr++) = *(data++);
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return 0;
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}
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uint32_t backup_ram_get_size_in_words(void)
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{
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return (uint32_t)BACKUP_RAM_SIZE_WORDS;
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}
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volatile void *backup_ram_get_base_ptr(void)
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{
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return backup_ram;
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}
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