reflow-oven-control-sw/stm-firmware/stm-periph/option-bytes.c

91 lines
2.5 KiB
C

/* Reflow Oven Controller
*
* Copyright (C) 2021 Mario Hüttel <mario.huettel@gmx.net>
*
* This file is part of the Reflow Oven Controller Project.
*
* The reflow oven controller is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* The Reflow Oven Control Firmware is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with the reflow oven controller project.
* If not, see <http://www.gnu.org/licenses/>.
*/
#include <stm-periph/option-bytes.h>
#include <stm32/stm32f4xx.h>
/**
* @brief First key for unlocking hte option byte write access
*/
#define FLASH_OPTION_KEY1 (0x08192A3BUL)
/**
* @brief Second key for unlocking hte option byte write access
*/
#define FLASH_OPTION_KEY2 (0x4C5D6E7FUL)
void stm_option_bytes_read(struct option_bytes *opts)
{
uint32_t opt_reg;
if (!opts)
return;
opt_reg = FLASH->OPTCR;
opts->brown_out_level = (opt_reg & FLASH_OPTCR_BOR_LEV) >> 2;
opts->nrst_standby = (opt_reg & FLASH_OPTCR_nRST_STDBY) >> 7;
opts->nrst_stop = (opt_reg & FLASH_OPTCR_nRST_STOP) >> 6;
opts->nwrpi = (opt_reg & FLASH_OPTCR_nWRP) >> 16;
opts->read_protection = (opt_reg & FLASH_OPTCR_RDP) >> 8;
opts->wdg_sw = (opt_reg & FLASH_OPTCR_WDG_SW) >> 5;
}
int stm_option_bytes_program(const struct option_bytes *opts)
{
uint32_t reg;
FLASH->OPTKEYR = FLASH_OPTION_KEY1;
FLASH->OPTKEYR = FLASH_OPTION_KEY2;
__DSB();
if (FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) {
/* Unlocking failed */
return -1;
}
reg = FLASH->OPTCR;
reg &= ~FLASH_OPTCR_BOR_LEV;
reg &= ~FLASH_OPTCR_nRST_STDBY;
reg &= ~FLASH_OPTCR_nRST_STOP;
reg &= ~FLASH_OPTCR_nWRP;
reg &= ~FLASH_OPTCR_RDP;
reg &= ~FLASH_OPTCR_WDG_SW;
reg |= (opts->brown_out_level << 2) & FLASH_OPTCR_BOR_LEV;
reg |= (opts->nrst_standby << 7) & FLASH_OPTCR_nRST_STDBY;
reg |= (opts->nrst_stop << 6) & FLASH_OPTCR_nRST_STOP;
reg |= (opts->nwrpi << 16) & FLASH_OPTCR_nWRP;
reg |= (opts->read_protection << 8) & FLASH_OPTCR_RDP;
reg |= (opts->wdg_sw << 5) & FLASH_OPTCR_WDG_SW;
while (FLASH->SR & FLASH_SR_BSY);
FLASH->OPTCR = reg;
FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
__DSB();
while (FLASH->SR & FLASH_SR_BSY);
FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
__DSB();
return 0;
}