66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
#ifndef FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_CONFIG_H_
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#define FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_CONFIG_H_
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#include <stm32/stm32f4xx.h>
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#define SDIO_CLOCK_FREQ 42000000UL
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//General Definitions
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//Blocksize: 512 = 2^9 => 9
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#define BLOCKSIZE 9 //9
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//Hardware Flow: Prevents over- and underruns.
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#define HW_FLOW 0 //0
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//1 bit: !=4
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//4 bit: 4
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#define BUSWIDTH 4 //4
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//Initial Transfer CLK (ca. 400kHz)
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#define INITCLK 140UL //120
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//Working CLK (Maximum)
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#define WORKCLK 30UL //0
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//Data Timeout in CLK Cycles
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#define DATA_TIMEOUT_MS 250UL // 250
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#define DTIMEOUT (((SDIO_CLOCK_FREQ / (WORKCLK+2))) * DATA_TIMEOUT_MS / 1000UL)
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//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
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// Currently not used due to possible misalignment of the data buffer.
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//#define DMASTREAM DMA2_Stream6
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/* Port Definitions */
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#define PORTCLKMASK (RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIOAEN)
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#define ALTFUNC 12
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#define CLKPORT GPIOC
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#define D0PORT GPIOC
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#define D1PORT GPIOC
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#define D2PORT GPIOC
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#define D3PORT GPIOC
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#define CMDPORT GPIOD
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#define CLKPIN 12
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#define D0PIN 8
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#define D1PIN 9
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#define D2PIN 10
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#define D3PIN 11
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#define CMDPIN 2
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// Write Protection
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#define SDIO_ENABLE_WRITEPROT 0
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#define WRITEPROT_PORT GPIOD // Add this port to port clock mask!
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#define WRITEPROT_PIN 0
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#define WRITEPROT_PULLUP 0
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#define WRITEPROT_ACTIVE_LEVEL 0
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// Card inserted pin
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#define SDIO_ENABLE_INS 1
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#define INS_PORT GPIOA // Add this port to port clock mask!
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#define INS_PIN 8
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#define INS_PULLUP 1
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#define INS_ACTIVE_LEVEL 0
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#endif /* FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_CONFIG_H_ */
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