mhu/stm32f4-sdio
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implmented initialization, fixed a few bugs, fixed indentation

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This commit is contained in:
Mario Hüttel 2017-04-02 23:54:06 +02:00
parent a5ae7ec9a1
commit 00bcf66457
10 changed files with 504 additions and 548 deletions
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4
Makefile
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@ -19,7 +19,7 @@ mapfile = dafuqishappening
#TODO #TODO
CFILES += fatfs/option/syscall.c fatfs/option/ccsbcs.c fatfs/diskio.c fatfs/ff.c fatfs/shimatta_sdio_driver/shimatta_sdio-driver.c CFILES += fatfs/option/syscall.c fatfs/option/ccsbcs.c fatfs/diskio.c fatfs/ff.c fatfs/shimatta_sdio_driver/shimatta_sdio.c
################################################################################### ###################################################################################
CC=arm-none-eabi-gcc CC=arm-none-eabi-gcc
@ -32,7 +32,7 @@ LFLAGS += -mfloat-abi=hard -mfpu=fpv4-sp-d16 --disable-newlib-supplied-syscalls
LFLAGS += -Tstm32f407vgt6_flash.ld -Wl,-Map=$(mapfile).map -Wl,--gc-sections LFLAGS += -Tstm32f407vgt6_flash.ld -Wl,-Map=$(mapfile).map -Wl,--gc-sections
CFLAGS = -c -fmessage-length=0 -mlittle-endian -mthumb -mcpu=cortex-m4 -mthumb-interwork CFLAGS = -c -fmessage-length=0 -mlittle-endian -mthumb -mcpu=cortex-m4 -mthumb-interwork
CFLAGS += -mfloat-abi=hard -mfpu=fpv4-sp-d16 -nostartfiles CFLAGS += -mfloat-abi=hard -mfpu=fpv4-sp-d16 -nostartfiles -Wall
#################################################################################### ####################################################################################

2
fatfs/diskio.c
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@ -9,7 +9,7 @@
//Only ONE device with ONE partition!!! //Only ONE device with ONE partition!!!
#include <fatfs/diskio.h> /* FatFs lower layer API */ #include <fatfs/diskio.h> /* FatFs lower layer API */
#include "shimatta_sdio_driver/shimatta_sdio-driver.h" #include "shimatta_sdio_driver/shimatta_sdio.h"
/* Definitions of physical drive number for each drive */ /* Definitions of physical drive number for each drive */
#define SDCARD 0 /* Example: Map ATA harddisk to physical drive 0 */ #define SDCARD 0 /* Example: Map ATA harddisk to physical drive 0 */

403
fatfs/shimatta_sdio_driver/shimatta_sdio-driver.c
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@ -1,403 +0,0 @@
/*
* shimatta_sdio-driver.c
*
* Created on: Apr 30, 2015
* Mario Hüttel
*/
#include "shimatta_sdio-driver.h"
#define SETAF(PORT,PIN,AF) PORT->AFR[(PIN < 8 ? 0 : 1)] |= AF << ((PIN < 8 ? PIN : (PIN - 8)) * 4)
#define READCTRL ((BLOCKSIZE << 4) | SDIO_DCTRL_DMAEN)
#define DMAP2M (DMA_SxCR_CHSEL_2 | DMA_SxCR_PBURST_0 | DMA_SxCR_MBURST_0 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PSIZE_1 | DMA_SxCR_MINC | DMA_SxCR_PFCTRL)
#define DMAM2P (DMA_SxCR_CHSEL_2 | DMA_SxCR_PBURST_0 | DMA_SxCR_MBURST_0 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PSIZE_1 | DMA_SxCR_MINC | DMA_SxCR_PFCTRL | DMA_SxCR_DIR_0)
#define SHORT_ANS 1
#define LONG_ANS 3
#define NO_ANS 0
#define CCRCFAIL -1
#define CTIMEOUT -2
/* OCR Register Masks */
#define OCS_CCS (1<<30)
#define OCS_BUSY (1<<31)
typedef enum {ACMD41_RESP_INIT, ACMD41_RESP_ERR, ACMD41_RESP_SDSC, ACMD41_RESP_SDXC} ACMD41_RESP_t;
typedef enum {CMD8_RESP_TIMEOUT, CMD8_RESP_ACK, CMD8_RESP_ERR} CMD8_RESP_t;
typedef uint8_t CID_t;
void initModuleHw();
int SDIO_send_cmd(uint8_t CMD, uint32_t arg, uint8_t expectedAns);
int SDIO_get_response(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t* responseBuffer);
void SDIO_wait_cmd_sent();
ACMD41_RESP_t SDIO_send_ACMD41(uint8_t HCS);
int SDIO_send_CMD55();
int SDIO_send_CMD2();
int SDIO_send_CMD3(uint16_t* rca);
int SDIO_send_CMD0();
CMD8_RESP_t SDIO_send_CMD8();
void initDetectandProtectionPins();
int checkNotInserted(); // Returns 0 if inserted!
int checkWriteProtection(); // returns 0 if write protected
void switchPrescaler(uint8_t clkdiv);
//BYTE rxtxbuffer[1<<BLOCKSIZE]; //Data RX and TX Buffer not needed anymore. thanks to DMA
SDInfo_t cardInfo; // = {.type = CARD_NONE};
DSTATUS SDIO_status(){
DSTATUS returnval = 0;
if (checkNotInserted()) {
returnval |= STA_NODISK;
}
if (cardInfo.type == CARD_NONE) {
returnval |= STA_NOINIT;
}
if (checkWriteProtection()) {
returnval |= STA_PROTECT;
}
return returnval;
}
DSTATUS SDIO_initialize(){
CMD8_RESP_t res8;
ACMD41_RESP_t resa41;
uint8_t hcs_flag = 0;
cardInfo.rca = 0;
cardInfo.type = CARD_NONE;
initModuleHw();
initDetectandProtectionPins();
if (checkNotInserted()) {
return STA_NOINIT | STA_NODISK;
}
SDIO_send_CMD0();
res8 = SDIO_send_CMD8();
switch (res8) {
case CMD8_RESP_ACK: // SDV2 Card
hcs_flag = 1;
break;
case CMD8_RESP_ERR: // should not happen
return STA_NOINIT;
break;
case CMD8_RESP_TIMEOUT: // SDV1 Card
hcs_flag=0;
break;
default:
return STA_NOINIT;
break;
}
do {
resa41 = SDIO_send_ACMD41(hcs_flag);
}while(resa41 == ACMD41_RESP_INIT);
switch (resa41) {
case ACMD41_RESP_SDSC:
cardInfo.type = (hcs_flag ? SD_V2_SC : SD_V1);
break;
case ACMD41_RESP_SDXC:
cardInfo.type = SD_V2_HC;
break;
default:
return STA_NOINIT;
break;
}
if (SDIO_send_CMD2())
return STA_NOINIT;
if (SDIO_send_CMD3(&cardInfo.rca))
return STA_NOINIT;
//TODO: Set block length
//TODO: Set 4 bit mode
//TODO:
switchPrescaler(WORKCLK);
if (checkWriteProtection()) {
return STA_PROTECT;
} else
return 0;
}
DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){
return RES_OK;
}
DRESULT SDIO_disk_write(const BYTE *buff, DWORD sector, UINT count){
return RES_OK;
}
DRESULT SDIO_disk_ioctl(BYTE cmd, void* buff){
DRESULT res = RES_OK;
switch(cmd) {
case GET_BLOCK_SIZE:
*((DWORD*)buff) = 0x01;
break;
case GET_SECTOR_SIZE:
*((WORD*)buff) = (1<<BLOCKSIZE);
break;
case GET_SECTOR_COUNT:
res = RES_ERROR;
//TODO: Implement
break;
case CTRL_SYNC:
res = RES_OK;
//No cache
//Nothing to do
break;
default:
res = RES_PARERR;
break;
}
return res;
}
DWORD __attribute__((weak)) get_fattime(){
return (1<<16) | (1<<24); // return Jan. 1st 1980 00:00:00
}
void initModuleHw(){
//Init Clocks
RCC->AHB1ENR |= PORTCLKMASK;
RCC->APB2ENR |= RCC_APB2ENR_SDIOEN;
//Init Alternate Functions
CLKPORT->MODER |= (2<<CLKPIN*2);
D0PORT->MODER |= (2<<D0PIN*2);
D0PORT->PUPDR |= (1<<D0PIN*2);
#if BUSWIDTH==1
D1PORT->MODER |= (2<<D1PIN*2);
D1PORT->PUPDR |= (1<<D1PIN*2);
D2PORT->MODER |= (2<<D2PIN*2);
D2PORT->PUPDR |= (1<<D2PIN*2);
D3PORT->MODER |= (2<<D3PIN*2);
D3PORT->PUPDR |= (1<<D3PIN*2);
#endif
//CLKPORT->AFR[(CLKPIN < 8 ? 0 : 1)] |= ALTFUNC << ((CLKPIN < 8 ? CLKPIN : (CLKPIN - 8)) * 4);
SETAF(CLKPORT, CLKPIN, ALTFUNC);
SETAF(D0PORT, D0PIN, ALTFUNC);
#if BUSWIDTH==1
SETAF(D1PORT, D1PIN, ALTFUNC);
SETAF(D2PORT, D2PIN, ALTFUNC);
SETAF(D3PORT, D3PIN, ALTFUNC);
#endif
//Init Module
//Set CLK Control Register
SDIO->CLKCR = (HW_FLOW<<14) | (BUSWIDTH<<11) | SDIO_CLKCR_CLKEN | (INITCLK & SDIO_CLKCR_CLKDIV);
//Set Data Timeout
SDIO->DTIMER = DTIMEOUT;
//Set Data Parameters
//SDIO->DCTRL = (BLOCKSIZE << 4) | SDIO_DCTRL_DMAEN;
//Set Power Register: Power up Card CLK
SDIO->POWER = SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1;
}
void switchPrescaler(uint8_t clkdiv) {
uint32_t reg;
reg = SDIO->CLKCR;
reg &= ~SDIO_CLKCR_CLKDIV; // Clear prescaler
reg |= (SDIO_CLKCR_CLKDIV & clkdiv); // Set bits
SDIO->CLKCR = reg;
}
//Send Command
//Clear respone Flags
//->CRC Fail, complete response, Timeout
int SDIO_send_cmd(uint8_t CMD, uint32_t arg, uint8_t expectedAns){
//Clear Flags
SDIO->ICR = SDIO_ICR_CCRCFAILC | SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CMDSENTC;
//Send command
SDIO->ARG = arg;
SDIO->CMD = (CMD & SDIO_CMD_CMDINDEX) | SDIO_CMD_CPSMEN | SDIO_CMD_WAITPEND | ((expectedAns << 6) & SDIO_CMD_WAITRESP);
return 0;
}
void SDIO_wait_cmd_sent() {
while (!(SDIO->STA & SDIO_STA_CMDSENT));
SDIO->ICR |= SDIO_ICR_CMDSENTC;
}
int SDIO_get_response(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t *responseBuffer) {
//Wait for error or success
while (1) {
if (SDIO->STA & SDIO_STA_CMDREND) break; //Correct Respone Received
if ((SDIO->STA & SDIO_STA_CMDSENT) && (typeOfAns == NO_ANS)) break; // No response required
//Exclude ACMD41 and CMD2 from valid CRC check
if ((SDIO->STA & SDIO_STA_CCRCFAIL)) {
if(expectedCMD == 0xff) { // TODO: This seems odd..
break;
} else
return CCRCFAIL;
}
if (SDIO->STA & SDIO_STA_CTIMEOUT)
return CTIMEOUT;
}
//Valid Respone Received
if (((SDIO->RESPCMD & SDIO_RESPCMD_RESPCMD) != expectedCMD) && expectedCMD != 0xff)
return -1; //Not the expected respose
//If case of a correct Response
*(responseBuffer++) = SDIO->RESP1;
//Long response.
if (typeOfAns == LONG_ANS) {
*(responseBuffer++) = SDIO->RESP2;
*(responseBuffer++) = SDIO->RESP3;
*(responseBuffer++) = SDIO->RESP4;
}
}
int SDIO_send_CMD55(){
int retry = 0x20;
StatusConv_t converter;
uint32_t response;
do {
//Execute Command and check for valid response
SDIO_send_cmd(55, cardInfo.rca, SHORT_ANS);
if (!SDIO_get_response(55, SHORT_ANS, &response))
{
//Response valid. Check if Card has accepted switch to application command mode
converter.value = response;
if (converter.statusstruct.APP_CMD == 1)
return 0;
}
}while(--retry > 0);
return -1;
}
ACMD41_RESP_t SDIO_send_ACMD41(uint8_t HCS){
uint32_t response;
int retry = 0x20;
if (SDIO_send_CMD55()) return -1;
do {
SDIO_send_cmd(41, (HCS ? (1<<30) : 0) | (1<<28), SHORT_ANS);
if (!SDIO_get_response(0xFF, SHORT_ANS, &response)) {
if (response & OCS_BUSY) { // Card is ready... Who knows why this bit is called busy...
if (response & OCS_CCS) {
return ACMD41_RESP_SDXC;
} else {
return ACMD41_RESP_SDSC;
}
} else {
return ACMD41_RESP_INIT;
}
}
}while(--retry > 0);
return ACMD41_RESP_ERR;
}
int SDIO_send_CMD2() {
uint32_t response[4];
int retry = 0x20;
do {
SDIO_send_cmd(2, 0, LONG_ANS);
if (!SDIO_get_response(0xFF, LONG_ANS, response)) return 0;
}while(retry-- > 0);
}
int SDIO_send_CMD3(uint16_t* rca) {
uint32_t response;
int retry = 0x20;
do {
SDIO_send_cmd(3, 0, SHORT_ANS);
if (!SDIO_get_response(3, SHORT_ANS, &response)) {
// TODO: Do some *optional* checking
*rca = ((response & 0xFFFF0000) >> 16);
return 0;
}
}while(retry-- > 0);
return -1;
}
int SDIO_send_CMD0() {
SDIO_send_cmd(0, 0, NO_ANS);
SDIO_wait_cmd_sent();
return 0;
}
CMD8_RESP_t SDIO_send_CMD8() {
uint32_t response;
int res = 0;
int retry = 0x20;
do {
SDIO_send_cmd(8, 0x1CC, SHORT_ANS);
res = SDIO_get_response(8, SHORT_ANS, &response);
if (res == 0) {
if (response & 0x100)
return CMD8_RESP_ACK;
else
return CMD8_RESP_ERR;
}
}while(retry-- > 0);
return CMD8_RESP_TIMEOUT;
}
/**
* @brief initDetectandProtectionPins
*/
void initDetectandProtectionPins() {
#if SDIO_ENABLE_WRITEPROT==1
WRITEPROT_PORT->PUPDR |= ((WRITEPROT_PULLUP ? 1 : 0)<<WRITEPROT_PIN*2);
#endif /* SDIO_ENABLE_WRITEPROT */
#if SDIO_ENABLE_INS==1
INS_PORT->PUPDR |= ((INS_PULLUP? 1 : 0)<<INS_PIN*2);
#endif /* SDIO_ENABLE_INS */
__DSB();
}
/**
* @brief checkNotInserted
* @return return 0 if card is inserted, else 1
*/
int checkNotInserted() {
#if SDIO_ENABLE_INS
return ((INS_PORT->IDR & INS_PIN) == INS_ACTIVE_LEVEL ? 0 : 1);
#else
return 0; // Assume Card is inserted
#endif
}
/**
* @brief checkWriteProtection
* @return 0 if card is writable.
*/
int checkWriteProtection() {
#if SDIO_ENABLE_WRITEPROT
return ((WRITEPROT_PORT->IDR & WRITEPROT_PIN) == WRITEPROT_ACTIVE_LEVEL ? 1 : 0);
#else
return 0; // Assume Card is not write protected
#endif
}

133
fatfs/shimatta_sdio_driver/shimatta_sdio-driver.h~
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@ -1,133 +0,0 @@
/*
* shimatta_sdio-driver.h
*
* Created on: Apr 26, 2015
* Mario Hüttel
*/
#ifndef FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_DRIVER_H_
#define FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_DRIVER_H_
#include <diskio.h>
#include <stm32f4xx.h>
DSTATUS SDIO_status();
DSTATUS SDIO_initialize();
DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count);
DRESULT SDIO_disk_write(const BYTE *buff, DWORD sector, UINT count);
DRESULT SDIO_disk_ioctl(BYTE cmd, void* buff);
DWORD get_fattime();
//Defines for Card Status in struct _CardStatus
#define CURRENT_STATE_IDLE 0
#define CURRENT_STATE_READY 1
#define CURRENT_STATE_IDENT 2
#define CURRENT_STATE_STBY 3
#define CURRENT_STATE_TRAN 4
#define CURRENT_STATE_DATA 5
#define CURRENT_STATE_RCV 6
#define CURRENT_STATE_PRG 7
#define CURRENT_STATE_DIS 8
typedef struct _CardStatus {
uint32_t reserved : 3;
uint32_t AKE_SEQ_ERROR : 1;
uint32_t reserved_2 : 1;
uint32_t APP_CMD : 1;
uint32_t reserved_3 : 2;
uint32_t READY_FOR_DATA : 1;
uint32_t CURRENT_STATE : 4;
uint32_t ERASE_RESET : 1;
uint32_t CARD_ECC_DIABLED : 1;
uint32_t WP_ERASE_SKIP : 1;
uint32_t CSD_OVERWRITE : 1;
uint32_t reserved17 : 1;
uint32_t reserved18 : 1;
uint32_t ERROR : 1;
uint32_t CC_ERROR : 1;
uint32_t CARD_ECC_FAILED : 1;
uint32_t ILLEGAL_COMMAND : 1;
uint32_t COM_CRC_ERROR : 1;
uint32_t LOCK_UNLOCK_FAILED : 1;
uint32_t CARD_IS_LOCKED : 1;
uint32_t WP_VIOLATION : 1;
uint32_t ERASE_PARAM : 1;
uint32_t ERASE_SEQ_ERROR : 1;
uint32_t BLOCK_LEN_ERROR : 1;
uint32_t ADDRESS_ERROR : 1;
uint32_t OUT_OF_RANGE : 1;
}CardStatus_t;
typedef enum {CARD_NONE = 0, MMC, SD_V1, SD_V2_SC, SD_V2_HC} card_type_t;
// MMC not supported
typedef struct _SDInfo {
uint16_t rca;
card_type_t type;
}SDInfo_t;
typedef union _StatusConv {
CardStatus_t statusstruct;
uint32_t value;
}StatusConv_t;
//General Definitions
//Blocksize: 512 = 2^9 => 9
#define BLOCKSIZE 9 //9
//Hardware Flow: Prevents over- and underruns.
#define HW_FLOW 0 //0
//1 bit: 0
//4 bit: 1
#define BUSWIDTH 1 //1
//Initial Transfer CLK (ca. 400kHz)
#define INITCLK 120 //120
//Working CLK (Maximum)
#define WORKCLK 0 //0
//Data Timeout in CLK Cycles
#define DTIMEOUT 150 //150
//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
#define DMASTREAM DMA2_Stream3
//Port Definitions
#define PORTCLKMASK (RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOCEN)
#define ALTFUNC 12
#define CLKPORT GPIOC
#define D0PORT GPIOC
#define D1PORT GPIOC
#define D2PORT GPIOC
#define D3PORT GPIOC
#define CMDPORT GPIOD
#define CLKPIN 12
#define D0PIN 8
#define D1PIN 9
#define D2PIN 10
#define D3PIN 11
#define CMDPIN 2
// Write Protection
#define SDIO_ENABLE_WRITEPROT 0
#define WRITEPROT_PORT GPIOD // Add this port to port clock mask!
#define WRITEPROT_PIN 0
#define WRITEPROT_PULLUP 0
#define WRITEPROT_ACTIVE_LEVEL 0
// Card inserted pin
#define SDIO_ENABLE_INS 0
#define INS_PORT GPIOD // Add this port to port clock mask!
#define INS_PIN 0
#define INS_PULLUP 0
#define INS_ACTIVE_LEVEL 0
#endif /* FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_DRIVER_H_ */

435
fatfs/shimatta_sdio_driver/shimatta_sdio.c Normal file
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@ -0,0 +1,435 @@
/*
* shimatta_sdio-driver.c
*
* Created on: Apr 30, 2015
* Mario Hüttel
*/
#include "shimatta_sdio.h"
#include "shimatta_sdio_config.h"
#define SETAF(PORT,PIN,AF) PORT->AFR[(PIN < 8 ? 0 : 1)] |= AF << ((PIN < 8 ? PIN : (PIN - 8)) * 4)
#define READCTRL ((BLOCKSIZE << 4) | SDIO_DCTRL_DMAEN)
#define DMAP2M (DMA_SxCR_CHSEL_2 | DMA_SxCR_PBURST_0 | DMA_SxCR_MBURST_0 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PSIZE_1 | DMA_SxCR_MINC | DMA_SxCR_PFCTRL)
#define DMAM2P (DMA_SxCR_CHSEL_2 | DMA_SxCR_PBURST_0 | DMA_SxCR_MBURST_0 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PSIZE_1 | DMA_SxCR_MINC | DMA_SxCR_PFCTRL | DMA_SxCR_DIR_0)
#define SHORT_ANS 1
#define LONG_ANS 3
#define NO_ANS 0
#define CCRCFAIL 1
#define CTIMEOUT 2
/* OCR Register Masks */
#define OCS_CCS (1<<30)
#define OCS_BUSY (1<<31)
typedef enum {ACMD41_RESP_INIT, ACMD41_RESP_ERR, ACMD41_RESP_SDSC, ACMD41_RESP_SDXC} ACMD41_RESP_t;
typedef enum {CMD8_RESP_TIMEOUT, CMD8_VOLTAGE_ACCEPTED, CMD8_VOLTAGE_DENIED} CMD8_RESP_t;
typedef uint8_t CID_t;
void SDIO_init_hw();
int SDIO_send_cmd(uint8_t CMD, uint32_t arg, uint8_t expectedAns);
int SDIO_get_response(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t* responseBuffer);
void SDIO_wait_cmd_sent();
ACMD41_RESP_t SDIO_init_card_ACMD41(uint8_t HCS);
int SDIO_switch_appmode_CMD55();
int SDIO_send_all_send_cid_CMD2();
int SDIO_send_relative_address_CMD3(uint16_t* rca);
int SDIO_send_go_idle_CMD0();
CMD8_RESP_t SDIO_send_iface_condition_CMD8();
int SDIO_send_block_length_CMD16(uint32_t blocklen);
int SDIO_send_bus_width_ACMD6(uint8_t bus_width);
void SDIO_init_detect_pins();
int checkNotInserted(); // Returns 0 if inserted!
int checkWriteProtection(); // returns 0 if write protected
void switchPrescaler(uint8_t clkdiv);
//BYTE rxtxbuffer[1<<BLOCKSIZE]; //Data RX and TX Buffer not needed anymore. thanks to DMA
SDInfo_t card_info; // = {.type = CARD_NONE};
DSTATUS SDIO_status(){
DSTATUS returnval = 0;
if (checkNotInserted()) {
returnval |= STA_NODISK;
}
if (card_info.type == CARD_NONE) {
returnval |= STA_NOINIT;
}
if (checkWriteProtection()) {
returnval |= STA_PROTECT;
}
return returnval;
}
DSTATUS SDIO_initialize(){
int timeout = 200;
CMD8_RESP_t res8;
ACMD41_RESP_t resa41;
uint8_t hcs_flag = 0;
card_info.rca = 0;
card_info.type = CARD_NONE;
card_type_t detected_card = CARD_NONE;
SDIO_init_hw();
SDIO_init_detect_pins();
if (checkNotInserted()) {
return STA_NOINIT | STA_NODISK;
}
SDIO_send_go_idle_CMD0();
res8 = SDIO_send_iface_condition_CMD8();
switch (res8) {
case CMD8_VOLTAGE_ACCEPTED: // SDV2 Card
hcs_flag = 1;
break;
case CMD8_VOLTAGE_DENIED: // should not happen
return STA_NOINIT;
break;
case CMD8_RESP_TIMEOUT: // SDV1 Card
hcs_flag=0;
break;
default:
return STA_NOINIT;
break;
}
do {
resa41 = SDIO_init_card_ACMD41(hcs_flag);
}while((resa41 == ACMD41_RESP_INIT) && (--timeout > 0));
switch (resa41) {
case ACMD41_RESP_SDSC:
detected_card = (hcs_flag ? SD_V2_SC : SD_V1);
break;
case ACMD41_RESP_SDXC:
detected_card = SD_V2_HC;
break;
default:
return STA_NOINIT;
break;
}
if (SDIO_send_all_send_cid_CMD2())
return STA_NOINIT;
if (SDIO_send_relative_address_CMD3(&card_info.rca))
return STA_NOINIT;
if (SDIO_send_block_length_CMD16((uint32_t)(1<<BLOCKSIZE)))
return STA_NOINIT;
if (SDIO_send_bus_width_ACMD6(BUSWIDTH))
return STA_NOINIT;
switchPrescaler(WORKCLK);
card_info.type = detected_card;
if (checkWriteProtection()) {
return STA_PROTECT;
} else
return 0;
}
DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){
return RES_ERROR;
}
DRESULT SDIO_disk_write(const BYTE *buff, DWORD sector, UINT count){
return RES_ERROR;
}
DRESULT SDIO_disk_ioctl(BYTE cmd, void* buff){
DRESULT res = RES_OK;
switch(cmd) {
case GET_BLOCK_SIZE:
*((DWORD*)buff) = (DWORD)0x01;
break;
case GET_SECTOR_SIZE:
*((WORD*)buff) = (WORD)(1<<BLOCKSIZE);
break;
case GET_SECTOR_COUNT:
res = RES_ERROR;
//TODO: Implement
break;
case CTRL_SYNC:
res = RES_OK;
//No cache
//Nothing to do
break;
default:
res = RES_PARERR;
break;
}
return res;
}
DWORD __attribute__((weak)) get_fattime(){
return (1<<16) | (1<<24); // return Jan. 1st 1980 00:00:00
}
void SDIO_init_hw(){
//Init Clocks
RCC->AHB1ENR |= PORTCLKMASK;
RCC->APB2ENR |= RCC_APB2ENR_SDIOEN;
//Init Alternate Functions
CLKPORT->MODER |= (2<<CLKPIN*2);
D0PORT->MODER |= (2<<D0PIN*2);
D0PORT->PUPDR |= (1<<D0PIN*2);
#if BUSWIDTH==4
D1PORT->MODER |= (2<<D1PIN*2);
D1PORT->PUPDR |= (1<<D1PIN*2);
D2PORT->MODER |= (2<<D2PIN*2);
D2PORT->PUPDR |= (1<<D2PIN*2);
D3PORT->MODER |= (2<<D3PIN*2);
D3PORT->PUPDR |= (1<<D3PIN*2);
#endif
//CLKPORT->AFR[(CLKPIN < 8 ? 0 : 1)] |= ALTFUNC << ((CLKPIN < 8 ? CLKPIN : (CLKPIN - 8)) * 4);
SETAF(CLKPORT, CLKPIN, ALTFUNC);
SETAF(D0PORT, D0PIN, ALTFUNC);
#if BUSWIDTH==4
SETAF(D1PORT, D1PIN, ALTFUNC);
SETAF(D2PORT, D2PIN, ALTFUNC);
SETAF(D3PORT, D3PIN, ALTFUNC);
#endif
//Init Module
//Set CLK Control Register
SDIO->CLKCR = (HW_FLOW<<14) | ((BUSWIDTH == 4 ? 1 : 0)<<11) | SDIO_CLKCR_CLKEN |
(INITCLK & SDIO_CLKCR_CLKDIV);
//Set Data Timeout
SDIO->DTIMER = DTIMEOUT;
//Set Data Parameters
//SDIO->DCTRL = (BLOCKSIZE << 4) | SDIO_DCTRL_DMAEN;
//Set Power Register: Power up Card CLK
SDIO->POWER = SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1;
}
void switchPrescaler(uint8_t clkdiv) {
uint32_t reg;
reg = SDIO->CLKCR;
reg &= ~SDIO_CLKCR_CLKDIV; // Clear prescaler
reg |= (SDIO_CLKCR_CLKDIV & clkdiv); // Set bits
SDIO->CLKCR = reg;
}
int SDIO_send_bus_width_ACMD6(uint8_t bus_width) {
uint32_t response;
int retry = 0x20;
int ret;
if (SDIO_switch_appmode_CMD55()) return -1;
do {
SDIO_send_cmd(0x6, (bus_width == 4 ? 0x2 : 0x0), SHORT_ANS);
if (!(ret = SDIO_get_response(0x6, SHORT_ANS, &response)))
return 0;
} while(--retry > 0);
return ret;
}
//Send Command
//Clear respone Flags
//->CRC Fail, complete response, Timeout
int SDIO_send_cmd(uint8_t CMD, uint32_t arg, uint8_t expectedAns){
//Clear Flags
SDIO->ICR = SDIO_ICR_CCRCFAILC | SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CMDSENTC;
//Send command
SDIO->ARG = arg;
SDIO->CMD = (CMD & SDIO_CMD_CMDINDEX) | SDIO_CMD_CPSMEN | SDIO_CMD_WAITPEND | ((expectedAns << 6) & SDIO_CMD_WAITRESP);
return 0;
}
void SDIO_wait_cmd_sent() {
while (!(SDIO->STA & SDIO_STA_CMDSENT));
SDIO->ICR |= SDIO_ICR_CMDSENTC;
}
int SDIO_get_response(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t *responseBuffer) {
//Wait for error or success
while (1) {
if (SDIO->STA & SDIO_STA_CMDREND) break; //Correct Respone Received
if ((SDIO->STA & SDIO_STA_CMDSENT) && (typeOfAns == NO_ANS)) break; // No response required
//Exclude ACMD41 and CMD2 from valid CRC check
if ((SDIO->STA & SDIO_STA_CCRCFAIL)) {
if(expectedCMD == 0xff) { // TODO: This seems odd..
break;
} else
return -CCRCFAIL;
}
if (SDIO->STA & SDIO_STA_CTIMEOUT)
return -CTIMEOUT;
}
//Valid Respone Received
if (((SDIO->RESPCMD & SDIO_RESPCMD_RESPCMD) != expectedCMD) && expectedCMD != 0xff)
return -1; //Not the expected respose
//If case of a correct Response
*(responseBuffer++) = SDIO->RESP1;
//Long response.
if (typeOfAns == LONG_ANS) {
*(responseBuffer++) = SDIO->RESP2;
*(responseBuffer++) = SDIO->RESP3;
*(responseBuffer++) = SDIO->RESP4;
}
return 0;
}
int SDIO_switch_appmode_CMD55(){
int retry = 0x20;
StatusConv_t converter;
uint32_t response;
do {
//Execute Command and check for valid response
SDIO_send_cmd(55, card_info.rca, SHORT_ANS);
if (!SDIO_get_response(55, SHORT_ANS, &response))
{
//Response valid. Check if Card has accepted switch to application command mode
converter.value = response;
if (converter.statusstruct.APP_CMD == 1)
return 0;
}
}while(--retry > 0);
return -1;
}
ACMD41_RESP_t SDIO_init_card_ACMD41(uint8_t HCS){
uint32_t response;
int retry = 0x20;
if (SDIO_switch_appmode_CMD55()) return -1;
do {
SDIO_send_cmd(41, (HCS ? (1<<30) : 0) | (1<<28), SHORT_ANS);
if (!SDIO_get_response(0xFF, SHORT_ANS, &response)) {
if (response & OCS_BUSY) { // Card is ready... Who knows why this bit is called busy...
if (response & OCS_CCS) {
return ACMD41_RESP_SDXC;
} else {
return ACMD41_RESP_SDSC;
}
} else {
return ACMD41_RESP_INIT;
}
}
}while(--retry > 0);
return ACMD41_RESP_ERR;
}
int SDIO_send_all_send_cid_CMD2() {
uint32_t response[4];
int ret;
int retry = 0x20;
do {
SDIO_send_cmd(2, 0, LONG_ANS);
if (!(ret = SDIO_get_response(0xFF, LONG_ANS, response))) return 0;
}while(retry-- > 0);
return ret;
}
int SDIO_send_relative_address_CMD3(uint16_t* rca) {
uint32_t response;
int retry = 0x20;
do {
SDIO_send_cmd(3, 0, SHORT_ANS);
if (!SDIO_get_response(3, SHORT_ANS, &response)) {
// TODO: Do some *optional* checking
*rca = ((response & 0xFFFF0000) >> 16);
return 0;
}
}while(retry-- > 0);
return -1;
}
int SDIO_send_go_idle_CMD0() {
SDIO_send_cmd(0, 0, NO_ANS);
SDIO_wait_cmd_sent();
return 0;
}
CMD8_RESP_t SDIO_send_iface_condition_CMD8() {
uint32_t response;
int res = 0;
int retry = 0x20;
do {
SDIO_send_cmd(8, 0x1CC, SHORT_ANS); // 3.3V supply requesR
res = SDIO_get_response(8, SHORT_ANS, &response);
if (res == 0) {
if (response & 0x100)
return CMD8_VOLTAGE_ACCEPTED;
else
return CMD8_VOLTAGE_DENIED;
}
}while(retry-- > 0);
return CMD8_RESP_TIMEOUT;
}
/**
* @brief initDetectandProtectionPins
*/
void SDIO_init_detect_pins() {
#if SDIO_ENABLE_WRITEPROT==1
WRITEPROT_PORT->PUPDR |= ((WRITEPROT_PULLUP ? 1 : 0)<<WRITEPROT_PIN*2);
#endif /* SDIO_ENABLE_WRITEPROT */
#if SDIO_ENABLE_INS==1
INS_PORT->PUPDR |= ((INS_PULLUP? 1 : 0)<<INS_PIN*2);
#endif /* SDIO_ENABLE_INS */
__DSB();
}
/**
* @brief checkNotInserted
* @return return 0 if card is inserted, else 1
*/
int checkNotInserted() {
#if SDIO_ENABLE_INS
return ((INS_PORT->IDR & INS_PIN) == INS_ACTIVE_LEVEL ? 0 : 1);
#else
return 0; // Assume Card is inserted
#endif
}
int SDIO_send_block_length_CMD16(uint32_t blocklen) {
int timeout = 0x20;
int res;
uint32_t response;
do {
SDIO_send_cmd(16, (0x1<<BLOCKSIZE), SHORT_ANS);
if (!(res = SDIO_get_response(16, SHORT_ANS, &response)))
return 0;
}while(--timeout > 0);
return res;
}
/**
* @brief checkWriteProtection
* @return 0 if card is writable.
*/
int checkWriteProtection() {
#if SDIO_ENABLE_WRITEPROT
return ((WRITEPROT_PORT->IDR & WRITEPROT_PIN) == WRITEPROT_ACTIVE_LEVEL ? 1 : 0);
#else
return 0; // Assume Card is not write protected
#endif
}

9
fatfs/shimatta_sdio_driver/shimatta_sdio-driver.h → fatfs/shimatta_sdio_driver/shimatta_sdio.h
View File

@ -9,8 +9,7 @@
#define FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_DRIVER_H_ #define FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_DRIVER_H_
#include <fatfs/diskio.h> #include <fatfs/diskio.h>
#include <stm32f4xx.h> #include <stdint.h>
DSTATUS SDIO_status(); DSTATUS SDIO_status();
DSTATUS SDIO_initialize(); DSTATUS SDIO_initialize();
@ -81,9 +80,9 @@ typedef union _StatusConv {
#define BLOCKSIZE 9 //9 #define BLOCKSIZE 9 //9
//Hardware Flow: Prevents over- and underruns. //Hardware Flow: Prevents over- and underruns.
#define HW_FLOW 0 //0 #define HW_FLOW 0 //0
//1 bit: 0 //1 bit: !=4
//4 bit: 1 //4 bit: 4
#define BUSWIDTH 1 //1 #define BUSWIDTH 4 //4
//Initial Transfer CLK (ca. 400kHz) //Initial Transfer CLK (ca. 400kHz)
#define INITCLK 120 //120 #define INITCLK 120 //120
//Working CLK (Maximum) //Working CLK (Maximum)

59
fatfs/shimatta_sdio_driver/shimatta_sdio_config.h Normal file
View File

@ -0,0 +1,59 @@
#ifndef FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_CONFIG_H_
#define FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_CONFIG_H_
#include <stm32f4xx.h>
//General Definitions
//Blocksize: 512 = 2^9 => 9
#define BLOCKSIZE 9 //9
//Hardware Flow: Prevents over- and underruns.
#define HW_FLOW 0 //0
//1 bit: !=4
//4 bit: 4
#define BUSWIDTH 4 //4
//Initial Transfer CLK (ca. 400kHz)
#define INITCLK 120 //120
//Working CLK (Maximum)
#define WORKCLK 0 //0
//Data Timeout in CLK Cycles
#define DTIMEOUT 150 //150
//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
#define DMASTREAM DMA2_Stream3
/* Port Definitions */
#define PORTCLKMASK (RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOCEN)
#define ALTFUNC 12
#define CLKPORT GPIOC
#define D0PORT GPIOC
#define D1PORT GPIOC
#define D2PORT GPIOC
#define D3PORT GPIOC
#define CMDPORT GPIOD
#define CLKPIN 12
#define D0PIN 8
#define D1PIN 9
#define D2PIN 10
#define D3PIN 11
#define CMDPIN 2
// Write Protection
#define SDIO_ENABLE_WRITEPROT 0
#define WRITEPROT_PORT GPIOD // Add this port to port clock mask!
#define WRITEPROT_PIN 0
#define WRITEPROT_PULLUP 0
#define WRITEPROT_ACTIVE_LEVEL 0
// Card inserted pin
#define SDIO_ENABLE_INS 0
#define INS_PORT GPIOD // Add this port to port clock mask!
#define INS_PIN 0
#define INS_PULLUP 0
#define INS_ACTIVE_LEVEL 0
#endif /* FATFS_SHIMATTA_SDIO_DRIVER_SHIMATTA_SDIO_CONFIG_H_ */

1
main.c
View File

@ -20,6 +20,7 @@ int main() {
__DSB(); __DSB();
GPIOD->MODER = OUTPUT(12); GPIOD->MODER = OUTPUT(12);
SysTick_Config(8*1680000); SysTick_Config(8*1680000);
f_mount(&SDfs, "0:/", 1);
while(1); while(1);
} }

2
startup/system_stm32f4xx.c
View File

@ -400,8 +400,6 @@ static void SetSysClock(void)
/* Wait till the main PLL is used as system clock source */ /* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
} }
else else
{ /* If HSE fails to start-up, the application will have wrong clock { /* If HSE fails to start-up, the application will have wrong clock

4
stm32f4sdio.pro
View File

@ -1,6 +1,6 @@
TEMPLATE = app TEMPLATE = app
CONFIG -= console app_bundle qt CONFIG -= console app_bundle qt
SOURCES += main.c syscalls/syscalls.c uart/uart.c startup/system_stm32f4xx.c fatfs/option/syscall.c fatfs/option/ccsbcs.c fatfs/diskio.c fatfs/ff.c fatfs/shimatta_sdio_driver/shimatta_sdio-driver.c boot/startup_stm32f4xx.S SOURCES += main.c syscalls/syscalls.c uart/uart.c startup/system_stm32f4xx.c fatfs/option/syscall.c fatfs/option/ccsbcs.c fatfs/diskio.c fatfs/ff.c fatfs/shimatta_sdio_driver/shimatta_sdio.c boot/startup_stm32f4xx.S
INCLUDEPATH += ./include INCLUDEPATH += ./include
HEADERS += ./include/stm32f4xx.h ./include/startup/system_stm32f4xx.h ./include/stm32f407xx.h ./include/fatfs/ffconf.h ./include/fatfs/diskio.h ./include/fatfs/integer.h ./include/fatfs/ff.h ./include/cmsis/core_cmFunc.h ./include/cmsis/core_cmInstr.h ./include/cmsis/arm_math.h ./include/cmsis/core_cm4.h ./include/cmsis/core_cm4_simd.h ./include/uart/uart.h ./fatfs/shimatta_sdio_driver/shimatta_sdio-driver.h HEADERS += ./include/stm32f407xx.h ./include/cmsis/core_cm4.h ./include/cmsis/core_cmInstr.h ./include/cmsis/core_cmFunc.h ./include/cmsis/core_cm4_simd.h ./include/cmsis/arm_math.h ./include/startup/system_stm32f4xx.h ./include/stm32f4xx.h ./include/fatfs/ffconf.h ./include/fatfs/diskio.h ./include/fatfs/integer.h ./include/fatfs/ff.h ./include/uart/uart.h ./fatfs/shimatta_sdio_driver/shimatta_sdio_config.h ./fatfs/shimatta_sdio_driver/shimatta_sdio.h
DEFINES += STM32F407xx STM32F4XX ARM_MATH_CM4 DEFINES += STM32F407xx STM32F4XX ARM_MATH_CM4