eclipse debugging project

fatfs/shimatta_sdio_driver/shimatta_sdio.c

@@ -7,6 +7,7 @@
 
 #include "shimatta_sdio.h"
 #include "shimatta_sdio_config.h"
+#include <cmsis/core_cm4.h>
 
 #define SETAF(PORT,PIN,AF)  PORT->AFR[(PIN < 8 ? 0 : 1)] |= AF << ((PIN < 8 ? PIN : (PIN - 8)) * 4)
 
@@ -51,7 +52,8 @@ void SDIO_init_detect_pins();
 int checkNotInserted(); // Returns 0 if inserted!
 int checkWriteProtection(); // returns 0 if write protected
 void switchPrescaler(uint8_t clkdiv);
-
+int SDIO_send_write_block_CMD24(uint32_t addr);
+int SDIO_send_read_block_CMD17(uint32_t addr);
 int SDIO_get_sector_count(uint16_t rca, uint32_t *sector_count);
 
 //BYTE rxtxbuffer[1<<BLOCKSIZE]; //Data RX and TX Buffer not needed anymore. thanks to DMA
@@ -70,9 +72,11 @@ DSTATUS SDIO_status(){
 	}
 	return returnval;
 }
-
+uint32_t debug;
+uint32_t debug_timeout;
 DSTATUS SDIO_initialize(){
-	int timeout = 0x2000;
+	int timeout = 0x3000;
+	int i;
 	CMD8_RESP_t res8;
 	ACMD41_RESP_t resa41;
 	uint8_t hcs_flag = 0;
@@ -86,7 +90,7 @@ DSTATUS SDIO_initialize(){
 		return STA_NOINIT | STA_NODISK;
 	}
 
-
+	debug=0;
 	SDIO_send_go_idle_CMD0();
 	res8 = SDIO_send_iface_condition_CMD8();
 	switch (res8) {
@@ -103,10 +107,13 @@ DSTATUS SDIO_initialize(){
 		return STA_NOINIT;
 		break;
 	}
-
+	debug++;
+	debug_timeout=timeout;
 	do {
 		resa41 = SDIO_init_card_ACMD41(hcs_flag);
 	} while((resa41 == ACMD41_RESP_INIT) && (--timeout > 0));
+	debug++;
+	debug_timeout= timeout;
 	switch (resa41) {
 	case ACMD41_RESP_SDSC:
 		detected_card = (hcs_flag ? SD_V2_SC : SD_V1);
@@ -118,7 +125,7 @@ DSTATUS SDIO_initialize(){
 		return STA_NOINIT;
 		break;
 	}
-
+	debug++;
 	if (SDIO_send_all_send_cid_CMD2())
 		return STA_NOINIT;
 
@@ -144,8 +151,96 @@ DSTATUS SDIO_initialize(){
 	} else
 		return 0;
 }
+uint32_t debug_addr, debug_count;
+
+uint32_t __attribute__ ((aligned (16))) buffer_sdio[512/4];
+
 DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){
-	return RES_ERROR;
+	uint32_t addr;
+	uint32_t sdio_status;
+	uint32_t fifo;
+	uint32_t counter;
+	debug_addr = sector;
+	debug_count = count;
+	addr = (card_info.type == SD_V2_HC ? (sector) : (sector*512));
+	for (; count > 0; count--) {
+
+		/* configure read DMA */
+		DMA2->LIFCR = 0xffffffff;
+		DMA2->HIFCR = 0xffffffff;
+		DMASTREAM->NDTR = 0;
+		DMASTREAM->FCR |= 0x21 | 0x3 | (1<<DMA_SxFCR_DMDIS);
+		DMASTREAM->M0AR = (uint32_t)(&buffer_sdio);
+		DMASTREAM->PAR = (uint32_t)&(SDIO->FIFO);
+		DMASTREAM->CR = DMAP2M | DMA_SxCR_PL_1 | DMA_SxCR_PL_1;
+		DMASTREAM->CR |= DMA_SxCR_EN;
+
+		SDIO->DLEN = (1 << BLOCKSIZE);
+
+		/* Init Transfer */
+		if (SDIO_send_read_block_CMD17(addr)) {
+			return RES_ERROR;
+		}
+		SDIO->ICR = SDIO_ICR_CCRCFAILC | SDIO_ICR_DCRCFAILC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_DTIMEOUTC |
+						SDIO_ICR_TXUNDERRC | SDIO_ICR_RXOVERRC | SDIO_ICR_CMDRENDC | SDIO_ICR_CMDSENTC | SDIO_ICR_DATAENDC |
+						SDIO_ICR_STBITERRC | SDIO_ICR_DBCKENDC | SDIO_ICR_SDIOITC | SDIO_ICR_CEATAENDC;
+		SDIO->DCTRL = (BLOCKSIZE<<4) | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTEN;
+
+		debug=0;
+//		counter = 0;
+//		while (counter < (1<<(BLOCKSIZE-2)) || !(SDIO->STA & (SDIO_STA_DBCKEND | SDIO_STA_DATAEND))) { // TODO: Handle errors
+//			if (SDIO->STA & (SDIO_STA_DCRCFAIL | SDIO_STA_DTIMEOUT | SDIO_STA_STBITERR))
+//			{
+//				return RES_ERROR;
+//			}
+//
+//			if (SDIO->STA & SDIO_STA_RXDAVL) {
+//				counter++;
+//				fifo = SDIO->FIFO;
+//				*(buff++) = (BYTE)(fifo & 0xFF);
+//				fifo >>= 8;
+//				*(buff++) = (BYTE)(fifo & 0xFF);
+//				fifo >>= 8;
+//				*(buff++) = (BYTE)(fifo & 0xFF);
+//				fifo >>= 8;
+//				*(buff++) = (BYTE)(fifo & 0xFF);
+//			}
+//
+//		}
+//		if (SDIO->STA & SDIO_STA_DCRCFAIL) return RES_ERROR;
+
+		while(DMASTREAM->CR & DMA_SxCR_EN);
+		while(1) {
+			__DSB();
+			__DMB();
+			sdio_status = SDIO->STA;
+			if (sdio_status & SDIO_STA_DCRCFAIL) {
+				return RES_ERROR;
+			}
+			if (sdio_status & SDIO_STA_DTIMEOUT) {
+				return RES_ERROR;
+			}
+
+			if (sdio_status & SDIO_STA_DATAEND) {
+
+				if (!(sdio_status & SDIO_STA_RXACT)) {
+					break;
+				}
+			}
+		}
+
+
+		DMASTREAM->CR = 0x0;
+		while (DMASTREAM->CR);
+		__asm("dsb");
+
+		if (card_info.type == SD_V2_HC) {
+			addr++;
+		} else {
+			addr += (1<<BLOCKSIZE);
+		}
+	}
+	return RES_OK;
 }
 DRESULT SDIO_disk_write(const BYTE *buff, DWORD sector, UINT count){
 	return RES_ERROR;
@@ -184,7 +279,7 @@ DWORD __attribute__((weak)) get_fattime(){
 
 void SDIO_init_hw(){
 	//Init Clocks
-	RCC->AHB1ENR    |= PORTCLKMASK;
+	RCC->AHB1ENR    |= PORTCLKMASK | RCC_AHB1ENR_DMA2EN;
 	RCC->APB2ENR    |= RCC_APB2ENR_SDIOEN;
 	//Init Alternate Functions
 	CLKPORT->MODER  |= (2<<CLKPIN*2);
@@ -238,12 +333,16 @@ void switchPrescaler(uint8_t clkdiv) {
 int SDIO_send_bus_width_ACMD6(uint8_t bus_width) {
 	uint32_t response;
 	int retry = 0x20;
+	StatusConv_t status;
 	int ret;
 	if (SDIO_switch_appmode_CMD55()) return -1;
 	do {
 		SDIO_send_cmd(0x6, (bus_width == 4 ? 0x2 : 0x0), SHORT_ANS);
-		if (!(ret = SDIO_get_response(0x6, SHORT_ANS, &response)))
+		if (!(ret = SDIO_get_response(0x6, SHORT_ANS, &response))) {
+			status.value = response;
 			return 0;
+		}
+
 
 	} while(--retry > 0);
 	return ret;
@@ -263,6 +362,17 @@ int SDIO_send_cmd(uint8_t CMD, uint32_t arg, uint8_t expectedAns){
 	return 0;
 }
 
+int SDIO_send_write_block_CMD24(uint32_t addr) {
+	return -1;
+}
+
+int SDIO_send_read_block_CMD17(uint32_t addr) {
+	uint32_t response;
+
+	SDIO_send_cmd(17, addr, SHORT_ANS);
+	return SDIO_get_response(17, SHORT_ANS, &response);
+}
+
 void SDIO_wait_cmd_sent() {
 	while (!(SDIO->STA & SDIO_STA_CMDSENT));
 	SDIO->ICR |= SDIO_ICR_CMDSENTC;
@@ -276,7 +386,7 @@ int SDIO_get_response(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t *response
 
 		//Exclude ACMD41 and CMD2 from valid CRC check
 		if ((SDIO->STA & SDIO_STA_CCRCFAIL)) {
-			if(expectedCMD == 0xff) { // TODO: This seems odd..
+			if(expectedCMD == 0xff) {
 				break;
 			} else {
 				return -CCRCFAIL;
@@ -330,7 +440,7 @@ ACMD41_RESP_t SDIO_init_card_ACMD41(uint8_t HCS){
 	if (SDIO_switch_appmode_CMD55()) return ACMD41_RESP_ERR;
 
 	do {
-		SDIO_send_cmd(41, (HCS ? (1<<30) : 0) | (1<<28) | (1<<20) |(1<<21), SHORT_ANS);
+		SDIO_send_cmd(41, (HCS ? (1<<30) : 0) | (1<<28) | (1<<20) |(1<<21)|(1<<22) |(1<<23)|(1<<19), SHORT_ANS);
 		if (!SDIO_get_response(0xFF, SHORT_ANS, &response)) {
 			if (response & OCS_BUSY) { // Card is ready... Who knows why this bit is called busy...
 				if (response & OCS_CCS) {

fatfs/shimatta_sdio_driver/shimatta_sdio_config.h

@@ -14,11 +14,11 @@
 //Initial Transfer CLK (ca. 400kHz)
 #define INITCLK   120   //120
 //Working CLK (Maximum)
-#define WORKCLK   50     //0
+#define WORKCLK   255    //0
 //Data Timeout in CLK Cycles
-#define DTIMEOUT  150   //150
+#define DTIMEOUT  0x3000   //150
 //DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
-#define DMASTREAM DMA2_Stream3
+#define DMASTREAM DMA2_Stream6
 
 
 /* Port Definitions */