From 79d476e1eb4c9480f0579a3581aec78ea49d07c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mario=20H=C3=BCttel?= Date: Sat, 15 Apr 2017 19:50:17 +0200 Subject: [PATCH] STM32F407VE adaptations, tried to find initialization bug --- boot/startup_stm32f4xx.S | 6 +- fatfs/shimatta_sdio_driver/shimatta_sdio.c | 76 ++++++++++--------- .../shimatta_sdio_config.h | 5 +- hardfault/hardfault_prehandler.S | 20 +++++ include/fatfs/ffconf.h | 2 +- main.c | 54 ++++++++++--- stm32f407vgt6_flash.ld | 2 +- stm32sdio Debug.launch | 4 +- 8 files changed, 113 insertions(+), 56 deletions(-) create mode 100644 hardfault/hardfault_prehandler.S diff --git a/boot/startup_stm32f4xx.S b/boot/startup_stm32f4xx.S index 0b9c10a..87ae3d0 100644 --- a/boot/startup_stm32f4xx.S +++ b/boot/startup_stm32f4xx.S @@ -131,7 +131,7 @@ g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler - .word HardFault_Handler + .word HardFault_PreHandler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler @@ -240,8 +240,8 @@ g_pfnVectors: .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler + .weak HardFault_PreHandler + .thumb_set HardFault_PreHandler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler diff --git a/fatfs/shimatta_sdio_driver/shimatta_sdio.c b/fatfs/shimatta_sdio_driver/shimatta_sdio.c index bd5c566..c6bae01 100644 --- a/fatfs/shimatta_sdio_driver/shimatta_sdio.c +++ b/fatfs/shimatta_sdio_driver/shimatta_sdio.c @@ -8,6 +8,8 @@ #include "shimatta_sdio.h" #include "shimatta_sdio_config.h" #include +#include +extern void SDIO_wait_ms(unsigned int i); #define SETAF(PORT,PIN,AF) PORT->AFR[(PIN < 8 ? 0 : 1)] |= AF << ((PIN < 8 ? PIN : (PIN - 8)) * 4) @@ -74,6 +76,7 @@ DSTATUS SDIO_status(){ } uint32_t debug; uint32_t debug_timeout; +int debug_acmd = 0; DSTATUS SDIO_initialize(){ int timeout = 0x3000; int i; @@ -85,6 +88,7 @@ DSTATUS SDIO_initialize(){ card_type_t detected_card = CARD_NONE; SDIO_init_hw(); + SDIO_wait_ms(2); SDIO_init_detect_pins(); if (checkNotInserted()) { return STA_NOINIT | STA_NODISK; @@ -92,6 +96,7 @@ DSTATUS SDIO_initialize(){ debug=0; SDIO_send_go_idle_CMD0(); + SDIO_wait_ms(2); res8 = SDIO_send_iface_condition_CMD8(); switch (res8) { case CMD8_VOLTAGE_ACCEPTED: // SDV2 Card @@ -112,7 +117,9 @@ DSTATUS SDIO_initialize(){ do { resa41 = SDIO_init_card_ACMD41(hcs_flag); } while((resa41 == ACMD41_RESP_INIT) && (--timeout > 0)); + debug++; + debug_acmd = resa41; debug_timeout= timeout; switch (resa41) { case ACMD41_RESP_SDSC: @@ -153,7 +160,7 @@ DSTATUS SDIO_initialize(){ } uint32_t debug_addr, debug_count; -uint32_t __attribute__ ((aligned (16))) buffer_sdio[512/4]; +//uint32_t __attribute__ ((aligned (16))) buffer_sdio[512/4]; DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){ uint32_t addr; @@ -166,14 +173,14 @@ DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){ for (; count > 0; count--) { /* configure read DMA */ - DMA2->LIFCR = 0xffffffff; - DMA2->HIFCR = 0xffffffff; - DMASTREAM->NDTR = 0; - DMASTREAM->FCR |= 0x21 | 0x3 | (1<M0AR = (uint32_t)(&buffer_sdio); - DMASTREAM->PAR = (uint32_t)&(SDIO->FIFO); - DMASTREAM->CR = DMAP2M | DMA_SxCR_PL_1 | DMA_SxCR_PL_1; - DMASTREAM->CR |= DMA_SxCR_EN; +// DMA2->LIFCR = 0xffffffff; +// DMA2->HIFCR = 0xffffffff; +// DMASTREAM->NDTR = 0; +// DMASTREAM->FCR = DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1 | DMA_SxFCR_DMDIS; +// DMASTREAM->M0AR = (uint32_t)(buff); +// DMASTREAM->PAR = (uint32_t)&(SDIO->FIFO); +// DMASTREAM->CR = DMAP2M | DMA_SxCR_PL_1 | DMA_SxCR_PL_1; +// DMASTREAM->CR |= DMA_SxCR_EN; SDIO->DLEN = (1 << BLOCKSIZE); @@ -187,29 +194,29 @@ DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){ SDIO->DCTRL = (BLOCKSIZE<<4) | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTEN; debug=0; -// counter = 0; -// while (counter < (1<<(BLOCKSIZE-2)) || !(SDIO->STA & (SDIO_STA_DBCKEND | SDIO_STA_DATAEND))) { // TODO: Handle errors -// if (SDIO->STA & (SDIO_STA_DCRCFAIL | SDIO_STA_DTIMEOUT | SDIO_STA_STBITERR)) -// { -// return RES_ERROR; -// } -// -// if (SDIO->STA & SDIO_STA_RXDAVL) { -// counter++; -// fifo = SDIO->FIFO; -// *(buff++) = (BYTE)(fifo & 0xFF); -// fifo >>= 8; -// *(buff++) = (BYTE)(fifo & 0xFF); -// fifo >>= 8; -// *(buff++) = (BYTE)(fifo & 0xFF); -// fifo >>= 8; -// *(buff++) = (BYTE)(fifo & 0xFF); -// } -// -// } -// if (SDIO->STA & SDIO_STA_DCRCFAIL) return RES_ERROR; + counter = 0; + while (counter < (1<<(BLOCKSIZE-2)) || !(SDIO->STA & (SDIO_STA_DBCKEND | SDIO_STA_DATAEND))) { // TODO: Handle errors + if (SDIO->STA & (SDIO_STA_DCRCFAIL | SDIO_STA_DTIMEOUT | SDIO_STA_STBITERR)) + { + return RES_ERROR; + } - while(DMASTREAM->CR & DMA_SxCR_EN); + if (SDIO->STA & SDIO_STA_RXDAVL) { + counter++; + fifo = SDIO->FIFO; + *(buff++) = (BYTE)(fifo & 0xFF); + fifo >>= 8; + *(buff++) = (BYTE)(fifo & 0xFF); + fifo >>= 8; + *(buff++) = (BYTE)(fifo & 0xFF); + fifo >>= 8; + *(buff++) = (BYTE)(fifo & 0xFF); + } + + } + if (SDIO->STA & SDIO_STA_DCRCFAIL) return RES_ERROR; + + //while(DMASTREAM->CR & DMA_SxCR_EN); while(1) { __DSB(); __DMB(); @@ -230,10 +237,6 @@ DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){ } - DMASTREAM->CR = 0x0; - while (DMASTREAM->CR); - __asm("dsb"); - if (card_info.type == SD_V2_HC) { addr++; } else { @@ -398,7 +401,7 @@ int SDIO_get_response(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t *response return -CTIMEOUT; } //Valid Respone Received - if (((SDIO->RESPCMD & SDIO_RESPCMD_RESPCMD) != expectedCMD) && expectedCMD != 0xff) + if (((SDIO->RESPCMD & SDIO_RESPCMD_RESPCMD) != expectedCMD) && (expectedCMD != 0xff)) return -1; //Not the expected respose //If case of a correct Response @@ -438,7 +441,6 @@ ACMD41_RESP_t SDIO_init_card_ACMD41(uint8_t HCS){ uint32_t response; int retry = 0x20; if (SDIO_switch_appmode_CMD55()) return ACMD41_RESP_ERR; - do { SDIO_send_cmd(41, (HCS ? (1<<30) : 0) | (1<<28) | (1<<20) |(1<<21)|(1<<22) |(1<<23)|(1<<19), SHORT_ANS); if (!SDIO_get_response(0xFF, SHORT_ANS, &response)) { diff --git a/fatfs/shimatta_sdio_driver/shimatta_sdio_config.h b/fatfs/shimatta_sdio_driver/shimatta_sdio_config.h index f2fc2fb..c0974dd 100644 --- a/fatfs/shimatta_sdio_driver/shimatta_sdio_config.h +++ b/fatfs/shimatta_sdio_driver/shimatta_sdio_config.h @@ -12,13 +12,14 @@ //4 bit: 4 #define BUSWIDTH 4 //4 //Initial Transfer CLK (ca. 400kHz) -#define INITCLK 120 //120 +#define INITCLK 130 //120 //Working CLK (Maximum) #define WORKCLK 255 //0 //Data Timeout in CLK Cycles #define DTIMEOUT 0x3000 //150 //DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible -#define DMASTREAM DMA2_Stream6 +// Currently not used due to possible misalignment of the data buffer. +//#define DMASTREAM DMA2_Stream6 /* Port Definitions */ diff --git a/hardfault/hardfault_prehandler.S b/hardfault/hardfault_prehandler.S new file mode 100644 index 0000000..628f4f3 --- /dev/null +++ b/hardfault/hardfault_prehandler.S @@ -0,0 +1,20 @@ +/* Preliminary Header: Author: Mario Huettel */ + +.syntax unified +.cpu cortex-m4 +.thumb +.type HardFault_PreHandler, %function +.global HardFault_PreHandler +.type HardFault_PreHandler, %function +HardFault_PreHandler: +TST LR, #4 // Test bit 2. If active => PSP was used, else MSP +ITE EQ +MRSEQ R0, MSP // Bit not set => MSP as argument +MRSNE R0, PSP // Bit set => PSP +LDR R1, =HardFault_Handler +BX R1 + +//.weak HardFault_Handler +//.thumb_set HardFault_Handler, HardFault_Handler_Default +//HardFault_Handler_Default: +//B HardFault_Handler_Default diff --git a/include/fatfs/ffconf.h b/include/fatfs/ffconf.h index d57e73a..b28445f 100644 --- a/include/fatfs/ffconf.h +++ b/include/fatfs/ffconf.h @@ -98,7 +98,7 @@ */ -#define _USE_LFN 0 +#define _USE_LFN 1 #define _MAX_LFN 255 /* The _USE_LFN switches the support of long file name (LFN). / diff --git a/main.c b/main.c index c6e75ca..be3b088 100644 --- a/main.c +++ b/main.c @@ -10,6 +10,7 @@ #include #include #include +#include #define OUTPUT(pin) (0b01 << (pin * 2)) @@ -17,24 +18,24 @@ FATFS SDfs; FIL file; DIR root; volatile int w; - - DSTATUS SDIO_initialize(); +volatile uint32_t sdio_wait; int initreq = 0xFF; int main() { - char buff[100]; + char buff[1024]; char *name; FILINFO fno; - RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN; + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN; __DSB(); - GPIOD->MODER |= OUTPUT(12) | OUTPUT(13); + GPIOA->MODER |= OUTPUT(6) | OUTPUT(7); + GPIOA->ODR |= (1<<7); SysTick_Config(8*1680000); // f_mount(&SDfs, "0:/", 1); w = 0; initUART(); setvbuf(stdout, NULL, _IONBF, 0); - while(w<10); + //while(w<10); initreq = f_mount(&SDfs, "0:/", 1); while(initreq); @@ -43,16 +44,16 @@ int main() { if (!f_readdir(&root, &fno)) { name = fno.fname; - initreq = f_open(&file, _T("test.txt"), FA_READ); + initreq = f_open(&file, name, FA_READ); if (initreq == FR_OK) { f_gets(buff, sizeof(buff), &file); - printf("test.txt:\r\n%s\r\n", buff); + printf("%s:\r\n%s\r\n",name, buff); f_close(&file); } } } -fflush(stdout); +//fflush(stdout); while(1); @@ -60,8 +61,41 @@ while(1); } + + +void HardFault_Handler(uint32_t *stack) { +// unsigned int stacked_r0; +// unsigned int stacked_r1; +// unsigned int stacked_r2; +// unsigned int stacked_r3; +// unsigned int stacked_r12; +// unsigned int stacked_lr; +// unsigned int stacked_pc; +// unsigned int stacked_psr; +// +// stacked_r0 = stack[0]; +// stacked_r1 = stack[1]; +// stacked_r2 = stack[2]; +// stacked_r3 = stack[3]; +// +// stacked_r12 = stack[4]; +// stacked_lr = stack[5]; +// stacked_pc = stack[6]; +// stacked_psr = stack[7]; + GPIOA->MODER |= OUTPUT(6) | OUTPUT(7); + GPIOA->ODR |= (1<<6) | (1<<7); + while(1); +} + void SysTick_Handler() { - GPIOD->ODR ^= (1<<12); + GPIOA->ODR ^= (1<<6)|(1<<7); w++; + sdio_wait++; +} + +void SDIO_wait_ms(unsigned int i) { + sdio_wait = 0; + while(sdio_wait - + @@ -79,5 +79,5 @@ - +