Improve single block writing and reading
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		@@ -373,9 +373,12 @@ static void sdio_init_hw()
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static int sdio_send_read_block_cmd17(uint32_t addr)
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{
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	uint32_t response;
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	int retry;
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	int ret;
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	sdio_send_cmd(17, addr, SHORT_ANS);
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	return sdio_get_response(17, SHORT_ANS, &response);
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	ret = sdio_get_response(17, SHORT_ANS, &response);
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	return ret;
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}
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static int sdio_send_all_send_cid_cmd2()
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@@ -605,6 +608,7 @@ DRESULT sdio_disk_read(BYTE *buff, DWORD sector, UINT count){
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	uint32_t sdio_status;
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	uint32_t fifo;
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	uint32_t counter;
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	union sdio_status_conv status; 
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	addr = (card_info.type == SD_V2_HC ? (sector) : (sector*512));
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	for (; count > 0; count--) {
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@@ -619,7 +623,13 @@ DRESULT sdio_disk_read(BYTE *buff, DWORD sector, UINT count){
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		//		DMASTREAM->CR = DMAP2M | DMA_SxCR_PL_1 | DMA_SxCR_PL_1;
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		//		DMASTREAM->CR |= DMA_SxCR_EN;
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		do {
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                        sdio_check_status_register_cmd13(card_info.rca, &status.value);
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                } while (status.statusstruct.CURRENT_STATE != CURRENT_STATE_TRAN);
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		SDIO->DLEN = (1 << BLOCKSIZE);
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		SDIO->DTIMER = DTIMEOUT;
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		SDIO->ICR = SDIO_ICR_CCRCFAILC | SDIO_ICR_DCRCFAILC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_DTIMEOUTC |
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				SDIO_ICR_TXUNDERRC | SDIO_ICR_RXOVERRC | SDIO_ICR_CMDRENDC | SDIO_ICR_CMDSENTC | SDIO_ICR_DATAENDC |
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@@ -704,16 +714,6 @@ DRESULT sdio_disk_write(const BYTE *buff, DWORD sector, UINT count)
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	addr = (card_info.type == SD_V2_HC ? (sector) : (sector * 512));
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	while (count) {
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		do {
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			sdio_check_status_register_cmd13(card_info.rca, &status.value);
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		} while (status.statusstruct.CURRENT_STATE == CURRENT_STATE_PRG ||
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			 status.statusstruct.CURRENT_STATE == CURRENT_STATE_RCV);
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		if (status.statusstruct.CURRENT_STATE == CURRENT_STATE_STBY) {
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			if (sdio_send_select_card_cmd7(card_info.rca))
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				return RES_ERROR;
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		}
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		do {
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			sdio_check_status_register_cmd13(card_info.rca, &status.value);
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		} while (status.statusstruct.READY_FOR_DATA != 1);
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@@ -14,9 +14,9 @@
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//Initial Transfer CLK (ca. 400kHz)
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#define INITCLK   130   //120
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//Working CLK (Maximum)
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#define WORKCLK   50   //0
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#define WORKCLK   8   //0
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//Data Timeout in CLK Cycles
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#define DTIMEOUT  0x3000   //150
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#define DTIMEOUT  0x8000   //150
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//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
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// Currently not used due to possible misalignment of the data buffer.
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//#define DMASTREAM DMA2_Stream6
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