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4 changed files with 94 additions and 11 deletions

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@ -39,21 +39,21 @@ int SDIO_send_cmd(uint8_t CMD, uint32_t arg, uint8_t expectedAns);
int SDIO_get_response(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t* responseBuffer); int SDIO_get_response(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t* responseBuffer);
void SDIO_wait_cmd_sent(void); void SDIO_wait_cmd_sent();
ACMD41_RESP_t SDIO_init_card_ACMD41(uint8_t HCS); ACMD41_RESP_t SDIO_init_card_ACMD41(uint8_t HCS);
int SDIO_switch_appmode_CMD55(void); int SDIO_switch_appmode_CMD55();
int SDIO_send_all_send_cid_CMD2(void); int SDIO_send_all_send_cid_CMD2();
int SDIO_send_relative_address_CMD3(uint16_t* rca); int SDIO_send_relative_address_CMD3(uint16_t* rca);
int SDIO_send_go_idle_CMD0(void); int SDIO_send_go_idle_CMD0();
CMD8_RESP_t SDIO_send_iface_condition_CMD8(void); CMD8_RESP_t SDIO_send_iface_condition_CMD8();
int SDIO_send_block_length_CMD16(uint32_t blocklen); int SDIO_send_block_length_CMD16(uint32_t blocklen);
int SDIO_send_bus_width_ACMD6(uint8_t bus_width); int SDIO_send_bus_width_ACMD6(uint8_t bus_width);
int SDIO_send_csd_CMD9(uint16_t rca, uint32_t *responsebuffer); int SDIO_send_csd_CMD9(uint16_t rca, uint32_t *responsebuffer);
int SDIO_send_select_card_CMD7(uint16_t rca); int SDIO_send_select_card_CMD7(uint16_t rca);
int SDIO_check_status_register_CMD13(uint16_t rca, uint32_t *status); int SDIO_check_status_register_CMD13(uint16_t rca, uint32_t *status);
void SDIO_init_detect_pins(void); void SDIO_init_detect_pins();
int checkNotInserted(void); // Returns 0 if inserted! int checkNotInserted(); // Returns 0 if inserted!
int checkWriteProtection(void); // returns 0 if write protected int checkWriteProtection(); // returns 0 if write protected
void switchPrescaler(uint8_t clkdiv); void switchPrescaler(uint8_t clkdiv);
int SDIO_send_write_block_CMD24(uint32_t addr); int SDIO_send_write_block_CMD24(uint32_t addr);
int SDIO_send_read_block_CMD17(uint32_t addr); int SDIO_send_read_block_CMD17(uint32_t addr);

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@ -14,7 +14,7 @@
//Initial Transfer CLK (ca. 400kHz) //Initial Transfer CLK (ca. 400kHz)
#define INITCLK 130 //120 #define INITCLK 130 //120
//Working CLK (Maximum) //Working CLK (Maximum)
#define WORKCLK 50 //0 #define WORKCLK 255 //0
//Data Timeout in CLK Cycles //Data Timeout in CLK Cycles
#define DTIMEOUT 0x3000 //150 #define DTIMEOUT 0x3000 //150
//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible //DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible

4
main.c
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@ -11,8 +11,8 @@
#include <uart/uart.h> #include <uart/uart.h>
#include <stdio.h> #include <stdio.h>
#include <stdint.h> #include <stdint.h>
#define OUTPUT(pin) (0x01 << (pin * 2)) #define OUTPUT(pin) (0b01 << (pin * 2))
FATFS SDfs; FATFS SDfs;
FIL file; FIL file;

83
stm32sdio Debug.launch Normal file
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@ -0,0 +1,83 @@
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