stm32f4-sdio/FATFS/shimatta_sdio_driver/shimatta_sdio-driver.c

/*
 * shimatta_sdio-driver.c
 *
 *  Created on: Apr 30, 2015
 *  Mario Hüttel
 */

#include <shimatta_sdio-driver.h>

#define SETAF(PORT,PIN,AF)  PORT->AFR[(PIN < 8 ? 0 : 1)] |= AF << ((PIN < 8 ? PIN : (PIN - 8)) * 4)

#define READCTRL ((BLOCKSIZE << 4) | SDIO_DCTRL_DMAEN)
#define DMAP2M (DMA_SxCR_CHSEL_2 | DMA_SxCR_PBURST_0 | DMA_SxCR_MBURST_0 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PSIZE_1 | DMA_SxCR_MINC | DMA_SxCR_PFCTRL)
#define DMAM2P (DMA_SxCR_CHSEL_2 | DMA_SxCR_PBURST_0 | DMA_SxCR_MBURST_0 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PSIZE_1 | DMA_SxCR_MINC | DMA_SxCR_PFCTRL | DMA_SxCR_DIR_0)
#define SHORT_ANS 1
#define LONG_ANS 3
#define NO_ANS 0


#define CCRCFAIL -1
#define CTIMEOUT -2


void SDIO_DMA_Init();
void SDIO_InitModule();

int SDIO_sendCmd(uint8_t CMD, uint32_t arg, uint8_t expectedAns);
int SDIO_getResp(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t* responseBuffer);
int SDIO_parseR1Ans(uint32_t resp, StatusConv_t converter);

int SDIO_send_ACMD41();
int SDIO_send_CMD55();


//BYTE rxtxbuffer[1<<BLOCKSIZE]; //Data RX and TX Buffer not needed anymore. thanks to DMA
SDInfo_t cardInfo;

DSTATUS SDIO_status(){
	return 0;
}
DSTATUS SDIO_initialize(){
    cardInfo.rca = 0;
    cardInfo.type = CARD_NONE;

    SDIO_DMA_Init();
    SDIO_InitModule();


	return 0;
}
DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){
	return RES_OK;
}
DRESULT SDIO_disk_write(const BYTE *buff, DWORD sector, UINT count){
	return RES_OK;
}
DRESULT SDIO_disk_ioctl(BYTE cmd, void* buff){
    DRESULT res = RES_OK;
    switch(cmd) {
    case GET_BLOCK_SIZE:
        *((DWORD*)buff) = 0x01;
        break;
     case GET_SECTOR_SIZE:
        *((WORD*)buff) = (1<<BLOCKSIZE);
        break;
     case GET_SECTOR_COUNT:
        res = RES_ERROR;
        //TODO: Implement
        break;
      case CTRL_SYNC:
        res = RES_ERROR;
        //TODO: Implement
        break;
     default:
        res = RES_PARERR;
     break;
    }
    return res;
}
DWORD __attribute__((weak)) get_fattime(){
	return 0;
}


void SDIO_DMA_Init(){
    RCC->AHB1ENR    |= RCC_AHB1ENR_DMA2EN;
    DMASTREAM->CR   = DMAM2P;
    //Address Conffiguration
    //Memory address is set by write and read block functions
    //DMASTREAM->M0AR = (uint32_t)&rxtxbuffer; //Has to be set in read/write func
    DMASTREAM->PAR = (uint32_t)&SDIO->FIFO; //Not sure if this works
    //DMASTREAM->CR   |= DMA_SxCR_EN;

}

void SDIO_InitModule(){
    //Init Clocks
    RCC->AHB1ENR    |= PORTCLKMASK;
    RCC->APB2ENR    |= RCC_APB2ENR_SDIOEN;
    //Init Alternate Functions
    CLKPORT->MODER  |= (2<<CLKPIN*2);
    D0PORT->MODER   |= (2<<D0PIN*2);
    D0PORT->PUPDR   |= (1<<D0PIN*2);
#if BUSWIDTH==1
    D1PORT->MODER   |= (2<<D1PIN*2);
    D1PORT->PUPDR   |= (1<<D1PIN*2);
    D2PORT->MODER   |= (2<<D2PIN*2);
    D2PORT->PUPDR   |= (1<<D2PIN*2);
    D3PORT->MODER   |= (2<<D3PIN*2);
    D3PORT->PUPDR   |= (1<<D3PIN*2);
#endif
    //CLKPORT->AFR[(CLKPIN < 8 ? 0 : 1)] |= ALTFUNC << ((CLKPIN < 8 ? CLKPIN : (CLKPIN - 8)) * 4);
    SETAF(CLKPORT,  CLKPIN, ALTFUNC);
    SETAF(D0PORT,   D0PIN,  ALTFUNC);
#if BUSWIDTH==1
    SETAF(D1PORT,   D1PIN,  ALTFUNC);
    SETAF(D2PORT,   D2PIN,  ALTFUNC);
    SETAF(D3PORT,   D3PIN,  ALTFUNC);
#endif


    //Init Module

    //Set CLK Control Register
    SDIO->CLKCR = (HW_FLOW<<14) | (BUSWIDTH<<11) | SDIO_CLKCR_CLKEN | (INITCLK & SDIO_CLKCR_CLKDIV);

    //Set Data Timeout
    SDIO->DTIMER = DTIMEOUT;

    //Set Data Parameters
    //SDIO->DCTRL = (BLOCKSIZE << 4) | SDIO_DCTRL_DMAEN;
    //Set Power Register: Power up Card CLK
    SDIO->POWER = SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1;

}


//Send Command
//Clear respone Flags
//->CRC Fail, complete response, Timeout
int SDIO_sendCmd(uint8_t CMD, uint32_t arg, uint8_t expectedAns){
    //Clear Flags
    SDIO->ICR = SDIO_ICR_CCRCFAILC | SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC;
    //Send command
    SDIO->ARG = arg;
    SDIO->CMD = (CMD & SDIO_CMD_CMDINDEX) | SDIO_CMD_CPSMEN | SDIO_CMD_WAITPEND | ((expectedAns << 6) & SDIO_CMD_WAITRESP);
    return 0;
}

int SDIO_getResp(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t *responseBuffer) {
    //Return with success because no data is needed
    if (typeOfAns == NO_ANS) return 0;

    //Wait for error or success
    while (1) {
        if (SDIO->STA & SDIO_STA_CMDREND) break; //Correct Respone Received

        //Exclude ACMD41 from valid CRC check
        if ((SDIO->STA & SDIO_STA_CCRCFAIL)) {
            if(expectedCMD == 41) {
                //This command does not have a CRC...Doushite....
                break;//Hopefully the response is correct. Even without CRC....
            } else 
                return CCRCFAIL; 
        }


        if (SDIO->STA & SDIO_STA_CTIMEOUT)
            return CTIMEOUT;
    }
    //Valid Respone Received
    if ((SDIO->RESPCMD & SDIO_RESPCMD_RESPCMD) != expectedCMD) return -1; //Not the expected respose

    //If case of a correct Response
    *(responseBuffer++) = SDIO->RESP1;
    //Long response.
    if (typeOfAns == LONG_ANS) {
        *(responseBuffer++) = SDIO->RESP2;
        *(responseBuffer++) = SDIO->RESP3;
        *(responseBuffer++) = SDIO->RESP4;
    }

}

int SDIO_send_CMD55(){
    int retry = 0x20;
    StatusConv_t converter;
    uint32_t response;
    do {
        //Execute Command and check for valid response
        SDIO_sendCmd(55, cardInfo.rca, SHORT_ANS);

        if (!SDIO_getResp(55, SHORT_ANS, &response))
        {
            //Response valid. Check if Card has accepted switch to application command mode
            converter.value = response;
            if (converter.statusstruct.APP_CMD == 1)
                return 0;
        }
    }while(--retry > 0);

    return -1;
}

int SDIO_send_ACMD41(){
    int retry = 0x20;
    if (SDIO_send_CMD55()) return -1;

    do {

        SDIO_sendCmd(41, 1<<30, SHORT_ANS);
        //TODO: Implement Response Check...


    }while(--retry > 0);
}