702 lines
17 KiB
C
702 lines
17 KiB
C
/*
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* shimatta_sdio-driver.c
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*
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* Created on: Apr 30, 2015
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* Mario Hüttel
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*/
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#include "shimatta_sdio.h"
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#include "shimatta_sdio_config.h"
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#include <cmsis/core_cm4.h>
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#include <stm32f4xx.h>
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extern void SDIO_wait_ms(unsigned int i);
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#define SETAF(PORT,PIN,AF) PORT->AFR[(PIN < 8 ? 0 : 1)] |= AF << ((PIN < 8 ? PIN : (PIN - 8)) * 4)
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#define READCTRL ((BLOCKSIZE << 4) | SDIO_DCTRL_DMAEN)
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#define DMAP2M (DMA_SxCR_CHSEL_2 | DMA_SxCR_PBURST_0 | DMA_SxCR_MBURST_0 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PSIZE_1 | DMA_SxCR_MINC | DMA_SxCR_PFCTRL)
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#define DMAM2P (DMA_SxCR_CHSEL_2 | DMA_SxCR_PBURST_0 | DMA_SxCR_MBURST_0 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PSIZE_1 | DMA_SxCR_MINC | DMA_SxCR_PFCTRL | DMA_SxCR_DIR_0)
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#define SHORT_ANS 1
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#define LONG_ANS 3
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#define NO_ANS 0
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#define CCRCFAIL 1
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#define CTIMEOUT 2
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#define CNOTEXPETED 3
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/* OCR Register Masks */
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#define OCS_CCS (1<<30)
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#define OCS_BUSY (1<<31)
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typedef enum {ACMD41_RESP_INIT = 0, ACMD41_RESP_ERR, ACMD41_RESP_SDSC, ACMD41_RESP_SDXC} ACMD41_RESP_t;
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typedef enum {CMD8_RESP_TIMEOUT = 0, CMD8_VOLTAGE_ACCEPTED, CMD8_VOLTAGE_DENIED} CMD8_RESP_t;
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typedef uint8_t CID_t;
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void SDIO_init_hw();
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int SDIO_send_cmd(uint8_t CMD, uint32_t arg, uint8_t expectedAns);
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int SDIO_get_response(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t* responseBuffer);
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void SDIO_wait_cmd_sent(void);
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ACMD41_RESP_t SDIO_init_card_ACMD41(uint8_t HCS);
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int SDIO_switch_appmode_CMD55(void);
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int SDIO_send_all_send_cid_CMD2(void);
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int SDIO_send_relative_address_CMD3(uint16_t* rca);
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int SDIO_send_go_idle_CMD0(void);
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CMD8_RESP_t SDIO_send_iface_condition_CMD8(void);
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int SDIO_send_block_length_CMD16(uint32_t blocklen);
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int SDIO_send_bus_width_ACMD6(uint8_t bus_width);
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int SDIO_send_csd_CMD9(uint16_t rca, uint32_t *responsebuffer);
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int SDIO_send_select_card_CMD7(uint16_t rca);
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int SDIO_check_status_register_CMD13(uint16_t rca, uint32_t *status);
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void SDIO_init_detect_pins(void);
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int checkNotInserted(void); // Returns 0 if inserted!
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int checkWriteProtection(void); // returns 0 if write protected
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void switchPrescaler(uint8_t clkdiv);
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int SDIO_send_write_block_CMD24(uint32_t addr);
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int SDIO_send_read_block_CMD17(uint32_t addr);
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int SDIO_get_sector_count(uint16_t rca, uint32_t *sector_count);
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//BYTE rxtxbuffer[1<<BLOCKSIZE]; //Data RX and TX Buffer not needed anymore. thanks to DMA
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SDInfo_t card_info; // = {.type = CARD_NONE};
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DSTATUS SDIO_status(){
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DSTATUS returnval = 0;
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if (checkNotInserted()) {
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returnval |= STA_NODISK;
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}
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if (card_info.type == CARD_NONE) {
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returnval |= STA_NOINIT;
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}
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if (checkWriteProtection()) {
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returnval |= STA_PROTECT;
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}
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return returnval;
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}
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volatile uint32_t debug;
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volatile uint32_t debug_timeout;
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volatile int debug_acmd = 0;
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sdio_write_buffer(uint32_t dlen, uint32_t blklen, uint8_t *buff)
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{
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int count;
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int byte_count;
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int byte_max;
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uint32_t fifo;
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SDIO->DLEN = dlen;
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/* Init Transfer */
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SDIO->ICR = SDIO_ICR_CCRCFAILC | SDIO_ICR_DCRCFAILC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_DTIMEOUTC |
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SDIO_ICR_TXUNDERRC | SDIO_ICR_RXOVERRC | SDIO_ICR_CMDRENDC | SDIO_ICR_CMDSENTC | SDIO_ICR_DATAENDC |
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SDIO_ICR_STBITERRC | SDIO_ICR_DBCKENDC | SDIO_ICR_SDIOITC | SDIO_ICR_CEATAENDC;
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SDIO->DCTRL = (blklen<<4) | SDIO_DCTRL_DTEN;
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for (count = 0; count < dlen; count += 4) {
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fifo = 0;
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if ((dlen - count) < 4)
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byte_max = dlen - count;
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else
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byte_max = 4;
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for (byte_count = 0; byte_count < byte_max; byte_count++)
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{
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fifo >>= 8;
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fifo |= (((uint32_t)*(buff++)) << 24) & 0xFF000000;
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}
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while (SDIO->STA & SDIO_STA_TXFIFOF);
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SDIO->FIFO = fifo;
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}
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while (SDIO->STA & SDIO_STA_TXACT);
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}
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uint8_t data1[512] = {(1<<1), 16, 0xC9, 0x9A, 0x20, 0x84, 0x3E, 0xD7, 0xD9, 0x0B, 0x68, 0x01,
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0xE4, 0x9F, 0x2B, 0xC8, 0x02, 0x77};
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sdio_unlock_card()
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{
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uint32_t resp[10];
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//SDIO_send_block_length_CMD16(18U);
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SDIO_send_cmd(42, 0, SHORT_ANS);
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SDIO_get_response(42, SHORT_ANS, resp);
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sdio_write_buffer(512, 9, data1);
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}
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DSTATUS SDIO_initialize(){
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int timeout = 0x3000;
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int i;
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CMD8_RESP_t res8;
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ACMD41_RESP_t resa41;
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uint8_t hcs_flag = 0;
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card_info.rca = 0;
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card_info.type = CARD_NONE;
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card_type_t detected_card = CARD_NONE;
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SDIO_init_hw();
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SDIO_wait_ms(2);
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SDIO_init_detect_pins();
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if (checkNotInserted()) {
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return STA_NOINIT | STA_NODISK;
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}
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debug=0;
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SDIO_send_go_idle_CMD0();
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SDIO_wait_ms(2);
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res8 = SDIO_send_iface_condition_CMD8();
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switch (res8) {
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case CMD8_VOLTAGE_ACCEPTED: // SDV2 Card
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hcs_flag = 1;
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break;
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case CMD8_VOLTAGE_DENIED: // should not happen
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return STA_NOINIT;
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break;
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case CMD8_RESP_TIMEOUT: // SDV1 Card
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hcs_flag=0;
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break;
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default:
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return STA_NOINIT;
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break;
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}
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debug++;
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debug_timeout=timeout;
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do {
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//SDIO_wait_ms(2);
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resa41 = SDIO_init_card_ACMD41(hcs_flag);
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} while((resa41 == ACMD41_RESP_INIT) && (--timeout > 0));
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debug++;
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debug_acmd = resa41;
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debug_timeout= timeout;
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switch (resa41) {
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case ACMD41_RESP_SDSC:
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detected_card = (hcs_flag ? SD_V2_SC : SD_V1);
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break;
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case ACMD41_RESP_SDXC:
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detected_card = SD_V2_HC;
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break;
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default:
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return STA_NOINIT;
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break;
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}
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debug++;
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if (SDIO_send_all_send_cid_CMD2())
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return STA_NOINIT;
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if (SDIO_send_relative_address_CMD3(&card_info.rca))
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return STA_NOINIT;
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if (SDIO_get_sector_count(card_info.rca, &card_info.sector_count))
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return STA_NOINIT;
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if (SDIO_send_select_card_CMD7(card_info.rca))
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return STA_NOINIT;
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if (SDIO_send_block_length_CMD16((uint32_t)(1<<BLOCKSIZE)))
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return STA_NOINIT;
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sdio_unlock_card();
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if (SDIO_send_bus_width_ACMD6(BUSWIDTH))
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return STA_NOINIT;
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switchPrescaler(WORKCLK);
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card_info.type = detected_card;
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if (checkWriteProtection()) {
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return STA_PROTECT;
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} else
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return 0;
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}
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uint32_t debug_addr, debug_count;
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//uint32_t __attribute__ ((aligned (16))) buffer_sdio[512/4];
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DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){
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uint32_t addr;
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uint32_t sdio_status;
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uint32_t fifo;
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uint32_t counter;
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debug_addr = sector;
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debug_count = count;
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addr = (card_info.type == SD_V2_HC ? (sector) : (sector*512));
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for (; count > 0; count--) {
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/* configure read DMA */
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// DMA2->LIFCR = 0xffffffff;
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// DMA2->HIFCR = 0xffffffff;
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// DMASTREAM->NDTR = 0;
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// DMASTREAM->FCR = DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1 | DMA_SxFCR_DMDIS;
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// DMASTREAM->M0AR = (uint32_t)(buff);
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// DMASTREAM->PAR = (uint32_t)&(SDIO->FIFO);
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// DMASTREAM->CR = DMAP2M | DMA_SxCR_PL_1 | DMA_SxCR_PL_1;
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// DMASTREAM->CR |= DMA_SxCR_EN;
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SDIO->DLEN = (1 << BLOCKSIZE);
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/* Init Transfer */
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if (SDIO_send_read_block_CMD17(addr)) {
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return RES_ERROR;
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}
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SDIO->ICR = SDIO_ICR_CCRCFAILC | SDIO_ICR_DCRCFAILC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_DTIMEOUTC |
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SDIO_ICR_TXUNDERRC | SDIO_ICR_RXOVERRC | SDIO_ICR_CMDRENDC | SDIO_ICR_CMDSENTC | SDIO_ICR_DATAENDC |
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SDIO_ICR_STBITERRC | SDIO_ICR_DBCKENDC | SDIO_ICR_SDIOITC | SDIO_ICR_CEATAENDC;
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SDIO->DCTRL = (BLOCKSIZE<<4) | SDIO_DCTRL_DTDIR | /*SDIO_DCTRL_DMAEN |*/ SDIO_DCTRL_DTEN;
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debug=0;
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counter = 0;
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while (counter < (1<<(BLOCKSIZE-2)) || !(SDIO->STA & (SDIO_STA_DBCKEND | SDIO_STA_DATAEND))) { // TODO: Handle errors
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if (SDIO->STA & (SDIO_STA_DCRCFAIL | SDIO_STA_DTIMEOUT | SDIO_STA_STBITERR))
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{
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return RES_ERROR;
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}
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if (SDIO->STA & SDIO_STA_RXDAVL) {
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counter++;
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fifo = SDIO->FIFO;
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*(buff++) = (BYTE)(fifo & 0xFF);
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fifo >>= 8;
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*(buff++) = (BYTE)(fifo & 0xFF);
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fifo >>= 8;
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*(buff++) = (BYTE)(fifo & 0xFF);
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fifo >>= 8;
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*(buff++) = (BYTE)(fifo & 0xFF);
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}
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}
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if (SDIO->STA & SDIO_STA_DCRCFAIL) return RES_ERROR;
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//while(DMASTREAM->CR & DMA_SxCR_EN);
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while(1) {
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__DSB();
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__DMB();
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sdio_status = SDIO->STA;
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if (sdio_status & SDIO_STA_DCRCFAIL) {
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return RES_ERROR;
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}
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if (sdio_status & SDIO_STA_DTIMEOUT) {
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return RES_ERROR;
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}
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if (sdio_status & SDIO_STA_DATAEND) {
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if (!(sdio_status & SDIO_STA_RXACT)) {
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break;
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}
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}
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}
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if (card_info.type == SD_V2_HC) {
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addr++;
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} else {
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addr += (1<<BLOCKSIZE);
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}
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}
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return RES_OK;
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}
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DRESULT SDIO_disk_write(const BYTE *buff, DWORD sector, UINT count){
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return RES_ERROR;
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}
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DRESULT SDIO_disk_ioctl(BYTE cmd, void* buff){
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DRESULT res = RES_OK;
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switch(cmd) {
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case GET_BLOCK_SIZE:
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*((DWORD*)buff) = (DWORD)0x01;
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break;
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case GET_SECTOR_SIZE:
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*((WORD*)buff) = (WORD)(1<<BLOCKSIZE);
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break;
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case GET_SECTOR_COUNT:
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if (card_info.type != CARD_NONE) {
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*((DWORD*)buff) = (DWORD)card_info.sector_count;
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} else {
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res = RES_ERROR;
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}
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break;
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case CTRL_SYNC:
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res = RES_OK;
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//No cache
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//Nothing to do
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break;
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default:
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res = RES_PARERR;
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break;
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}
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return res;
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}
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DWORD __attribute__((weak)) get_fattime(){
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return (1<<16) | (1<<24); // return Jan. 1st 1980 00:00:00
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}
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void SDIO_init_hw(){
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//Init Clocks
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RCC->AHB1ENR |= PORTCLKMASK | RCC_AHB1ENR_DMA2EN;
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RCC->APB2ENR |= RCC_APB2ENR_SDIOEN;
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//Init Alternate Functions
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CLKPORT->MODER |= (2<<CLKPIN*2);
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D0PORT->MODER |= (2<<D0PIN*2);
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D0PORT->PUPDR |= (1<<D0PIN*2);
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CMDPORT->MODER |= (2<<CMDPIN*2);
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CMDPORT->PUPDR |= (1<<CMDPIN*2);
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#if BUSWIDTH==4
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D1PORT->MODER |= (2<<D1PIN*2);
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D1PORT->PUPDR |= (1<<D1PIN*2);
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D2PORT->MODER |= (2<<D2PIN*2);
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D2PORT->PUPDR |= (1<<D2PIN*2);
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D3PORT->MODER |= (2<<D3PIN*2);
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D3PORT->PUPDR |= (1<<D3PIN*2);
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#endif
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//CLKPORT->AFR[(CLKPIN < 8 ? 0 : 1)] |= ALTFUNC << ((CLKPIN < 8 ? CLKPIN : (CLKPIN - 8)) * 4);
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SETAF(CLKPORT, CLKPIN, ALTFUNC);
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SETAF(CMDPORT, CMDPIN, ALTFUNC);
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SETAF(D0PORT, D0PIN, ALTFUNC);
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#if BUSWIDTH==4
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SETAF(D1PORT, D1PIN, ALTFUNC);
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SETAF(D2PORT, D2PIN, ALTFUNC);
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SETAF(D3PORT, D3PIN, ALTFUNC);
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#endif
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//Init Module
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//Set CLK Control Register
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SDIO->CLKCR = (HW_FLOW<<14) | ((BUSWIDTH == 4 ? 1 : 0)<<11) | SDIO_CLKCR_CLKEN |
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(INITCLK & SDIO_CLKCR_CLKDIV);
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//Set Data Timeout
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SDIO->DTIMER = DTIMEOUT;
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//Set Data Parameters
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//SDIO->DCTRL = (BLOCKSIZE << 4) | SDIO_DCTRL_DMAEN;
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//Set Power Register: Power up Card CLK
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SDIO->POWER = SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1;
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}
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void switchPrescaler(uint8_t clkdiv) {
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uint32_t reg;
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reg = SDIO->CLKCR;
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reg &= ~SDIO_CLKCR_CLKDIV; // Clear prescaler
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reg |= (SDIO_CLKCR_CLKDIV & clkdiv); // Set bits
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SDIO->CLKCR = reg;
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}
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int SDIO_send_bus_width_ACMD6(uint8_t bus_width) {
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uint32_t response;
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int retry = 0x20;
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StatusConv_t status;
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int ret;
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if (SDIO_switch_appmode_CMD55()) return -1;
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do {
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SDIO_send_cmd(0x6, (bus_width == 4 ? 0x2 : 0x0), SHORT_ANS);
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if (!(ret = SDIO_get_response(0x6, SHORT_ANS, &response))) {
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status.value = response;
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return 0;
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}
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} while(--retry > 0);
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return ret;
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}
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//Send Command
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//Clear respone Flags
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//->CRC Fail, complete response, Timeout
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int SDIO_send_cmd(uint8_t CMD, uint32_t arg, uint8_t expectedAns){
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//Clear Flags
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SDIO->ICR = SDIO_ICR_CCRCFAILC | SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CMDSENTC;
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//Send command
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SDIO->ARG = arg;
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SDIO->CMD = (CMD & SDIO_CMD_CMDINDEX) | SDIO_CMD_CPSMEN | /*SDIO_CMD_WAITPEND |*/ ((expectedAns << 6) & SDIO_CMD_WAITRESP);
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return 0;
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}
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int SDIO_send_write_block_CMD24(uint32_t addr) {
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return -1;
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}
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int SDIO_send_read_block_CMD17(uint32_t addr) {
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uint32_t response;
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SDIO_send_cmd(17, addr, SHORT_ANS);
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return SDIO_get_response(17, SHORT_ANS, &response);
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}
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void SDIO_wait_cmd_sent() {
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while (!(SDIO->STA & SDIO_STA_CMDSENT));
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SDIO->ICR |= SDIO_ICR_CMDSENTC;
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}
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int /*__attribute__((noinline)) __attribute__((optimize("O0")))*/ SDIO_get_response(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t *responseBuffer) {
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uint32_t sdio_status;
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/* Wait until command isn't active anymore */
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while (SDIO->STA & SDIO_STA_CMDACT);
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//Wait for error or success
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while (1) {
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sdio_status = SDIO->STA;
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if (sdio_status & SDIO_STA_CMDREND) break; //Correct Respone Received
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if ((sdio_status & SDIO_STA_CMDSENT) && (typeOfAns == NO_ANS)) break; // No response required
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//Exclude ACMD41 and CMD2 from valid CRC check
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if ((sdio_status & SDIO_STA_CCRCFAIL)) {
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if(expectedCMD == 0xff) {
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break;
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} else {
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return -CCRCFAIL;
|
|
}
|
|
}
|
|
|
|
|
|
if (sdio_status & SDIO_STA_CTIMEOUT)
|
|
return -CTIMEOUT;
|
|
}
|
|
//Valid Respone Received
|
|
if (((SDIO->RESPCMD & SDIO_RESPCMD_RESPCMD) != expectedCMD) && (expectedCMD != 0xff))
|
|
return -CNOTEXPETED; //Not the expected respose
|
|
|
|
//If case of a correct Response
|
|
*(responseBuffer++) = SDIO->RESP1;
|
|
//Long response.
|
|
if (typeOfAns == LONG_ANS) {
|
|
*(responseBuffer++) = SDIO->RESP2;
|
|
*(responseBuffer++) = SDIO->RESP3;
|
|
*(responseBuffer++) = SDIO->RESP4;
|
|
}
|
|
return 0;
|
|
|
|
}
|
|
|
|
int SDIO_switch_appmode_CMD55(){
|
|
int retry = 0x20;
|
|
StatusConv_t converter;
|
|
uint32_t response;
|
|
do {
|
|
//Execute Command and check for valid response
|
|
SDIO_send_cmd(55, (card_info.rca<<16)&0xFFFF0000, SHORT_ANS);
|
|
|
|
if (!SDIO_get_response(55, SHORT_ANS, &response))
|
|
{
|
|
//Response valid. Check if Card has accepted switch to application command mode
|
|
converter.value = response;
|
|
if (converter.statusstruct.APP_CMD == 1)
|
|
return 0;
|
|
}
|
|
}while(--retry > 0);
|
|
|
|
return -1;
|
|
}
|
|
|
|
|
|
ACMD41_RESP_t SDIO_init_card_ACMD41(uint8_t HCS){
|
|
uint32_t response;
|
|
int retry = 0x20;
|
|
if (SDIO_switch_appmode_CMD55()) return ACMD41_RESP_ERR;
|
|
do {
|
|
SDIO_send_cmd(41, (HCS ? (1<<30) : 0) | (1<<28) | (1<<20) |(1<<21)|(1<<22) |(1<<23)|(1<<19), SHORT_ANS);
|
|
if (!SDIO_get_response(0xFF, SHORT_ANS, &response)) {
|
|
if (response & OCS_BUSY) { // Card is ready... Who knows why this bit is called busy...
|
|
if (response & OCS_CCS) {
|
|
return ACMD41_RESP_SDXC;
|
|
} else {
|
|
return ACMD41_RESP_SDSC;
|
|
}
|
|
} else {
|
|
return ACMD41_RESP_INIT;
|
|
}
|
|
}
|
|
}while(--retry > 0);
|
|
|
|
return ACMD41_RESP_ERR;
|
|
}
|
|
|
|
int SDIO_send_all_send_cid_CMD2() {
|
|
uint32_t response[4];
|
|
int ret;
|
|
int retry = 0x20;
|
|
do {
|
|
SDIO_send_cmd(2, 0, LONG_ANS);
|
|
if (!(ret = SDIO_get_response(0xFF, LONG_ANS, response))) return 0;
|
|
}while(retry-- > 0);
|
|
return ret;
|
|
}
|
|
|
|
int SDIO_send_relative_address_CMD3(uint16_t* rca) {
|
|
uint32_t response;
|
|
int retry = 0x20;
|
|
do {
|
|
SDIO_send_cmd(3, 0, SHORT_ANS);
|
|
if (!SDIO_get_response(3, SHORT_ANS, &response)) {
|
|
// TODO: Do some *optional* checking
|
|
*rca = ((response & 0xFFFF0000) >> 16);
|
|
return 0;
|
|
}
|
|
}while(retry-- > 0);
|
|
return -1;
|
|
}
|
|
|
|
int SDIO_send_go_idle_CMD0() {
|
|
SDIO_send_cmd(0, 0x0, NO_ANS);
|
|
SDIO_wait_cmd_sent();
|
|
return 0;
|
|
}
|
|
|
|
CMD8_RESP_t SDIO_send_iface_condition_CMD8() {
|
|
uint32_t response;
|
|
int res = 0;
|
|
int retry = 0x20;
|
|
do {
|
|
SDIO_send_cmd(8, 0x1CC, SHORT_ANS); // 3.3V supply requesR
|
|
res = SDIO_get_response(8, SHORT_ANS, &response);
|
|
if (res == 0) {
|
|
if (response & 0x100)
|
|
return CMD8_VOLTAGE_ACCEPTED;
|
|
else
|
|
return CMD8_VOLTAGE_DENIED;
|
|
}
|
|
}while(retry-- > 0);
|
|
return CMD8_RESP_TIMEOUT;
|
|
}
|
|
|
|
/**
|
|
* @brief initDetectandProtectionPins
|
|
*/
|
|
void SDIO_init_detect_pins() {
|
|
#if SDIO_ENABLE_WRITEPROT==1
|
|
WRITEPROT_PORT->PUPDR |= ((WRITEPROT_PULLUP ? 1 : 0)<<WRITEPROT_PIN*2);
|
|
#endif /* SDIO_ENABLE_WRITEPROT */
|
|
#if SDIO_ENABLE_INS==1
|
|
INS_PORT->PUPDR |= ((INS_PULLUP? 1 : 0)<<INS_PIN*2);
|
|
#endif /* SDIO_ENABLE_INS */
|
|
__DSB();
|
|
}
|
|
|
|
/**
|
|
* @brief checkNotInserted
|
|
* @return return 0 if card is inserted, else 1
|
|
*/
|
|
int checkNotInserted() {
|
|
#if SDIO_ENABLE_INS
|
|
return ((INS_PORT->IDR & INS_PIN) == (INS_ACTIVE_LEVEL<<INS_PIN) ? 0 : 1);
|
|
#else
|
|
return 0; // Assume Card is inserted
|
|
#endif
|
|
}
|
|
|
|
int SDIO_send_block_length_CMD16(uint32_t blocklen) {
|
|
int timeout = 0x20;
|
|
int res;
|
|
uint32_t response;
|
|
|
|
do {
|
|
SDIO_send_cmd(16, blocklen, SHORT_ANS);
|
|
if (!(res = SDIO_get_response(16, SHORT_ANS, &response))) {
|
|
return 0;
|
|
}
|
|
}while(--timeout > 0);
|
|
|
|
return res;
|
|
}
|
|
|
|
int SDIO_send_select_card_CMD7(uint16_t rca) {
|
|
int timeout = 0x20;
|
|
uint32_t response;
|
|
StatusConv_t status;
|
|
int res;
|
|
|
|
/* Send CMD7. Selects card */
|
|
do {
|
|
SDIO_send_cmd(7, (rca<<16)&0xFFFF0000, SHORT_ANS);
|
|
if (!(res = SDIO_get_response(7, SHORT_ANS, &response))) {
|
|
break;
|
|
}
|
|
} while(--timeout > 0);
|
|
|
|
/* Check, if card in in TRANS state */
|
|
if (SDIO_check_status_register_CMD13(rca, &(status.value)))
|
|
res = -1;
|
|
if (status.statusstruct.CURRENT_STATE != CURRENT_STATE_TRAN)
|
|
res = -2;
|
|
return res;
|
|
}
|
|
|
|
int SDIO_check_status_register_CMD13(uint16_t rca, uint32_t *status) {
|
|
int timeout = 0x20;
|
|
uint32_t response;
|
|
int res;
|
|
do {
|
|
SDIO_send_cmd(13, (rca<<16)&0xFFFF0000, SHORT_ANS);
|
|
if (!(res = SDIO_get_response(13, SHORT_ANS, &response))) {
|
|
*status = response;
|
|
break;
|
|
}
|
|
} while(--timeout > 0);
|
|
|
|
return res;
|
|
}
|
|
|
|
int SDIO_get_sector_count(uint16_t rca, uint32_t *sector_count) {
|
|
uint32_t csd[4];
|
|
int res;
|
|
uint32_t size, mult, read_len, csd_rev;
|
|
|
|
if ((res = SDIO_send_csd_CMD9(rca, csd))) {
|
|
return -1;
|
|
}
|
|
|
|
csd_rev = ((csd[0] >> 30) & (0x3));
|
|
|
|
if (csd_rev == 0) { // SD v1 Card
|
|
size = ((csd[1] & 0x3FF) <<2) | (((csd[2]) & ((1<<31) | (1<<30)))>>30);
|
|
mult = ((csd[2] & ((1<<17)|(1<<16)|(1<<15)))>>15);
|
|
read_len = (1<<((csd[1] & ((1<<19)|(1<<18)|(1<<17)|(1<<16)))>>16));
|
|
*sector_count = (((size +1)*(1<<(mult+2))*read_len) >> BLOCKSIZE);
|
|
} else if (csd_rev == 1) { // SD v2 Card
|
|
size = (((csd[1] & 0x3F)<<16) | ((csd[2] & 0xFFFF0000) >> 16));
|
|
*sector_count = (size << (19-BLOCKSIZE));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int SDIO_send_csd_CMD9(uint16_t rca, uint32_t *responsebuffer) {
|
|
int timeout = 0x20;
|
|
int res;
|
|
|
|
do {
|
|
SDIO_send_cmd(9, (rca<<16)&0xFFFF0000, LONG_ANS);
|
|
if (!(res = SDIO_get_response(0xFF, LONG_ANS, responsebuffer))) {
|
|
break;
|
|
}
|
|
} while(--timeout > 0);
|
|
|
|
return res;
|
|
}
|
|
|
|
/**
|
|
* @brief checkWriteProtection
|
|
* @return 0 if card is writable.
|
|
*/
|
|
int checkWriteProtection() {
|
|
#if SDIO_ENABLE_WRITEPROT
|
|
return ((WRITEPROT_PORT->IDR & WRITEPROT_PIN) == (WRITEPROT_ACTIVE_LEVEL<<WRITEPROT_PIN) ? 1 : 0);
|
|
#else
|
|
return 0; // Assume Card is not write protected
|
|
#endif
|
|
}
|