112 lines
3.1 KiB
C
112 lines
3.1 KiB
C
#include <stm32f7xx.h>
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const signed char __pll_main_div_q_val[] = {-1, -1, 2, 3, 4, 5, 6, 7, 8 ,9, 10, 11, 12, 13, 14, 15};
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const signed char __pll_main_div_p_val[] = {-1, -1, 0, -1, 1, -1, 2, -1, 3};
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const signed char __mco_div_val[] = {-1, 0, 4, 5, 6, 7};
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const signed char __apb_presc_val[] = {-1, 0, 4, -1, 5, -1, -1, -1, 6, -1, -1, -1, -1, -1, -1, -1, 7};
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#define SYSINIT_MAIN_I2S_PLL_DIV_M_MIN (2)
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#define SYSINIT_MAIN_I2S_PLL_DIV_M_MAX (63)
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#define SYSINIT_MAIN_I2S_PLL_MULT_N_MIN (2)
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#define SYSINIT_MAIN_I2S_PLL_MULT_N_MAX (432)
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#define SYSINIT_MAIN_I2S_PLL_SRC_HSE (1)
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#define SYSINIT_MAIN_I2S_PLL_SRC_HSI (0)
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#define SYSINIT_MCO2_SRC_SYSCLK (0)
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#define SYSINIT_MCO2_SRC_PLLI2S (1)
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#define SYSINIT_MCO2_SRC_HSE (2)
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#define SYSINIT_MCO2_SRC_PLL (3)
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#define SYSINIT_MCO1_SRC_HSI (0)
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#define SYSINIT_MCO1_SRC_LSE (1)
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#define SYSINIT_MCO1_SRC_HSE (2)
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#define SYSINIT_MCO1_SRC_PLL (3)
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#define SYSINIT_I2S_SRC_PLLI2S (0)
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#define SYSINIT_I2S_SRC_CKIN (1)
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#define SYSINIT_SYSCLK_SRC_HSI (0)
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#define SYSINIT_SYSCLK_SRC_HSE (1)
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#define SYSINIT_SYSCLK_SRC_PLL (2)
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enum sysinit_ahb_presc {DIV1 = 0, DIV2 = 8, DIV4 = 9, DIV8 = 10, DIV16 = 11, DIV64 =12, DIV128 = 13, DIV256 = 14, DIV512 = 15};
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struct clock_config {
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uint32_t hsi_enable : 1;
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uint32_t hse_enable : 1;
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uint32_t lsi_enable : 1;
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uint32_t lse_enable : 1;
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uint32_t pll_sai_on : 1;
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uint32_t pll_i2s_on : 1;
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uint32_t pll_main_on : 1;
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uint32_t css_on : 1;
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uint32_t hse_bypass : 1;
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uint32_t hsi_trim : 5;
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/* Main PLL Conf */
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uint32_t pll_main_i2s_src : 1;
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uint32_t pll_main_div_q : 4; /* true value */
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uint32_t pll_main_div_p : 3; /* true value */
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uint32_t pll_main_mult_n : 9;
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uint32_t pll_main_div_m : 6;
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/* MCO Outputs */
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uint32_t mco2_sel : 2;
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uint32_t mco2_presc : 3;
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uint32_t mco1_sel : 2;
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/* I2S clock selection */
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uint32_t i2s_src : 1;
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/* RTC */
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uint32_t rtc_hse_div_1_meg : 5;
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/* APB */
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uint32_t apb1_presc : 5;
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uint32_t apb2_presc : 5;
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/* Systemclock */
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uint32_t sysclk_src : 2;
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/* AHB */
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enum sysinit_ahb_presc ahb_presc;
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};
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#define VECT_TAB_OFFSET (0x0)
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static void __init_default_clocks(void)
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{
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x24003010;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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void __system_init(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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__init_default_clocks();
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}
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