75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
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/*
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* STM32L052x8 System Setup Code
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*
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* This file is part of 'STM32L052' code template'.
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*
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* It is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 2 of the License.
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*
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* This code is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this template. If not, see <http://www.gnu.org/licenses/>.
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* ------------------------------------------------------------------------
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*/
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#include <stm32l0xx.h>
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#include <stdint.h>
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/**
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* @brief Init for 32 MHz clock
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*/
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static void __init_default_clocks(void)
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{
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uint32_t tmp;
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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/* Set Flash Waitstate */
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FLASH->ACR |= FLASH_ACR_LATENCY;
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/* Configure interal voltage regualtor to range 1 (1.8V) */
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PWR->CR = PWR_CR_VOS_0;
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/* Enable MSI osc as main source for now to ensure we're running stable */
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tmp = RCC->CFGR;
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tmp &= ~0x3;
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RCC->CFGR = tmp;
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/* Enable HSI */
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RCC->CR |= RCC_CR_HSION;
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/* Wait for HSI to be ready */
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while (!(RCC->CR & RCC_CR_HSIRDY));
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/* Disable PLL */
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RCC->CR &= ~RCC_CR_PLLON;
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while (RCC->CR & RCC_CR_PLLRDY);
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/* Reset PLL and clock div config etc. */
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RCC->CFGR = 0;
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/* Configure PLL for HSI input and 32 MHz output
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* PLLDIV = 2
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* PLLMUL = x4
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*/
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RCC->CFGR |= RCC_CFGR_PLLDIV_0 | RCC_CFGR_PLLMUL_0;
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/* Startup PLL */
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY));
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/* Switch over to PLL clock. Prescalers for buses are finde with div by 1 for 32 MHz */
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RCC->CFGR |= RCC_CFGR_SW_0 | RCC_CFGR_SW_1;
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}
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void __system_init(void)
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{
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__init_default_clocks();
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}
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