16672 lines
574 KiB
Plaintext
16672 lines
574 KiB
Plaintext
|
<?xml version="1.0" encoding="utf-8" standalone="no"?>
|
||
|
|
<device schemaVersion="1.1"
|
||
|
|
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
|
||
|
|
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
|
||
|
|
<name>STM32L0x1</name>
|
||
|
|
<version>1.3</version>
|
||
|
|
<description>STM32L0x1</description>
|
||
|
|
<!-- details about the cpu embedded in the device -->
|
||
|
|
<cpu>
|
||
|
|
<name>CM0+</name>
|
||
|
|
<revision>r0p0</revision>
|
||
|
|
<endian>little</endian>
|
||
|
|
<mpuPresent>false</mpuPresent>
|
||
|
|
<fpuPresent>false</fpuPresent>
|
||
|
|
<nvicPrioBits>3</nvicPrioBits>
|
||
|
|
<vendorSystickConfig>false</vendorSystickConfig>
|
||
|
|
</cpu>
|
||
|
|
<!--Bus Interface Properties-->
|
||
|
|
<!--Cortex-M3 is byte addressable-->
|
||
|
|
<addressUnitBits>8</addressUnitBits>
|
||
|
|
<!--the maximum data bit width accessible within a single transfer-->
|
||
|
|
<width>32</width>
|
||
|
|
<!--Register Default Properties-->
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x0</resetValue>
|
||
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
||
|
|
<peripherals>
|
||
|
|
<peripheral>
|
||
|
|
<name>AES</name>
|
||
|
|
<description>Advanced encryption standard hardware
|
||
|
|
accelerator</description>
|
||
|
|
<groupName>AES</groupName>
|
||
|
|
<baseAddress>0x40026000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>AES_RNG_LPUART1</name>
|
||
|
|
<description>AES global interrupt RNG global interrupt and
|
||
|
|
LPUART1 global interrupt through</description>
|
||
|
|
<value>29</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR</name>
|
||
|
|
<displayName>CR</displayName>
|
||
|
|
<description>control register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DMAOUTEN</name>
|
||
|
|
<description>Enable DMA management of data output
|
||
|
|
phase</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DMAINEN</name>
|
||
|
|
<description>Enable DMA management of data input
|
||
|
|
phase</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ERRIE</name>
|
||
|
|
<description>Error interrupt enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CCFIE</name>
|
||
|
|
<description>CCF flag interrupt enable</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ERRC</name>
|
||
|
|
<description>Error clear</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CCFC</name>
|
||
|
|
<description>Computation Complete Flag
|
||
|
|
Clear</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHMOD</name>
|
||
|
|
<description>AES chaining mode</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE</name>
|
||
|
|
<description>AES operating mode</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DATATYPE</name>
|
||
|
|
<description>Data type selection (for data in and
|
||
|
|
data out to/from the cryptographic
|
||
|
|
block)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EN</name>
|
||
|
|
<description>AES enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SR</name>
|
||
|
|
<displayName>SR</displayName>
|
||
|
|
<description>status register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>WRERR</name>
|
||
|
|
<description>Write error flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RDERR</name>
|
||
|
|
<description>Read error flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CCF</name>
|
||
|
|
<description>Computation complete flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>DINR</name>
|
||
|
|
<displayName>DINR</displayName>
|
||
|
|
<description>data input register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AES_DINR</name>
|
||
|
|
<description>Data Input Register.</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>DOUTR</name>
|
||
|
|
<displayName>DOUTR</displayName>
|
||
|
|
<description>data output register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AES_DOUTR</name>
|
||
|
|
<description>Data output register</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>KEYR0</name>
|
||
|
|
<displayName>KEYR0</displayName>
|
||
|
|
<description>key register 0</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AES_KEYR0</name>
|
||
|
|
<description>Data Output Register (LSB key
|
||
|
|
[31:0])</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>KEYR1</name>
|
||
|
|
<displayName>KEYR1</displayName>
|
||
|
|
<description>key register 1</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AES_KEYR1</name>
|
||
|
|
<description>AES key register (key
|
||
|
|
[63:32])</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>KEYR2</name>
|
||
|
|
<displayName>KEYR2</displayName>
|
||
|
|
<description>key register 2</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AES_KEYR2</name>
|
||
|
|
<description>AES key register (key
|
||
|
|
[95:64])</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>KEYR3</name>
|
||
|
|
<displayName>KEYR3</displayName>
|
||
|
|
<description>key register 3</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AES_KEYR3</name>
|
||
|
|
<description>AES key register (MSB key
|
||
|
|
[127:96])</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IVR0</name>
|
||
|
|
<displayName>IVR0</displayName>
|
||
|
|
<description>initialization vector register
|
||
|
|
0</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AES_IVR0</name>
|
||
|
|
<description>initialization vector register (LSB IVR
|
||
|
|
[31:0])</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IVR1</name>
|
||
|
|
<displayName>IVR1</displayName>
|
||
|
|
<description>initialization vector register
|
||
|
|
1</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AES_IVR1</name>
|
||
|
|
<description>Initialization Vector Register (IVR
|
||
|
|
[63:32])</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IVR2</name>
|
||
|
|
<displayName>IVR2</displayName>
|
||
|
|
<description>initialization vector register
|
||
|
|
2</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AES_IVR2</name>
|
||
|
|
<description>Initialization Vector Register (IVR
|
||
|
|
[95:64])</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IVR3</name>
|
||
|
|
<displayName>IVR3</displayName>
|
||
|
|
<description>initialization vector register
|
||
|
|
3</description>
|
||
|
|
<addressOffset>0x2C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AES_IVR3</name>
|
||
|
|
<description>Initialization Vector Register (MSB IVR
|
||
|
|
[127:96])</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>DMA1</name>
|
||
|
|
<description>Direct memory access controller</description>
|
||
|
|
<groupName>DMA</groupName>
|
||
|
|
<baseAddress>0x40020000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>DMA1_Channel1</name>
|
||
|
|
<description>DMA1 Channel1 global interrupt</description>
|
||
|
|
<value>9</value>
|
||
|
|
</interrupt>
|
||
|
|
<interrupt>
|
||
|
|
<name>DMA1_Channel2_3</name>
|
||
|
|
<description>DMA1 Channel2 and 3 interrupts</description>
|
||
|
|
<value>10</value>
|
||
|
|
</interrupt>
|
||
|
|
<interrupt>
|
||
|
|
<name>DMA1_Channel4_7</name>
|
||
|
|
<description>DMA1 Channel4 to 7 interrupts</description>
|
||
|
|
<value>11</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>ISR</name>
|
||
|
|
<displayName>ISR</displayName>
|
||
|
|
<description>interrupt status register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TEIF7</name>
|
||
|
|
<description>Channel x transfer error flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>27</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIF7</name>
|
||
|
|
<description>Channel x half transfer flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIF7</name>
|
||
|
|
<description>Channel x transfer complete flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>GIF7</name>
|
||
|
|
<description>Channel x global interrupt flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIF6</name>
|
||
|
|
<description>Channel x transfer error flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIF6</name>
|
||
|
|
<description>Channel x half transfer flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIF6</name>
|
||
|
|
<description>Channel x transfer complete flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>GIF6</name>
|
||
|
|
<description>Channel x global interrupt flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIF5</name>
|
||
|
|
<description>Channel x transfer error flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIF5</name>
|
||
|
|
<description>Channel x half transfer flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIF5</name>
|
||
|
|
<description>Channel x transfer complete flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>GIF5</name>
|
||
|
|
<description>Channel x global interrupt flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIF4</name>
|
||
|
|
<description>Channel x transfer error flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIF4</name>
|
||
|
|
<description>Channel x half transfer flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIF4</name>
|
||
|
|
<description>Channel x transfer complete flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>GIF4</name>
|
||
|
|
<description>Channel x global interrupt flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIF3</name>
|
||
|
|
<description>Channel x transfer error flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIF3</name>
|
||
|
|
<description>Channel x half transfer flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIF3</name>
|
||
|
|
<description>Channel x transfer complete flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>GIF3</name>
|
||
|
|
<description>Channel x global interrupt flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIF2</name>
|
||
|
|
<description>Channel x transfer error flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIF2</name>
|
||
|
|
<description>Channel x half transfer flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIF2</name>
|
||
|
|
<description>Channel x transfer complete flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>GIF2</name>
|
||
|
|
<description>Channel x global interrupt flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIF1</name>
|
||
|
|
<description>Channel x transfer error flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIF1</name>
|
||
|
|
<description>Channel x half transfer flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIF1</name>
|
||
|
|
<description>Channel x transfer complete flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>GIF1</name>
|
||
|
|
<description>Channel x global interrupt flag (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IFCR</name>
|
||
|
|
<displayName>IFCR</displayName>
|
||
|
|
<description>interrupt flag clear register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CTEIF7</name>
|
||
|
|
<description>Channel x transfer error clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>27</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHTIF7</name>
|
||
|
|
<description>Channel x half transfer clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTCIF7</name>
|
||
|
|
<description>Channel x transfer complete clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CGIF7</name>
|
||
|
|
<description>Channel x global interrupt clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTEIF6</name>
|
||
|
|
<description>Channel x transfer error clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHTIF6</name>
|
||
|
|
<description>Channel x half transfer clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTCIF6</name>
|
||
|
|
<description>Channel x transfer complete clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CGIF6</name>
|
||
|
|
<description>Channel x global interrupt clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTEIF5</name>
|
||
|
|
<description>Channel x transfer error clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHTIF5</name>
|
||
|
|
<description>Channel x half transfer clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTCIF5</name>
|
||
|
|
<description>Channel x transfer complete clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CGIF5</name>
|
||
|
|
<description>Channel x global interrupt clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTEIF4</name>
|
||
|
|
<description>Channel x transfer error clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHTIF4</name>
|
||
|
|
<description>Channel x half transfer clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTCIF4</name>
|
||
|
|
<description>Channel x transfer complete clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CGIF4</name>
|
||
|
|
<description>Channel x global interrupt clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTEIF3</name>
|
||
|
|
<description>Channel x transfer error clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHTIF3</name>
|
||
|
|
<description>Channel x half transfer clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTCIF3</name>
|
||
|
|
<description>Channel x transfer complete clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CGIF3</name>
|
||
|
|
<description>Channel x global interrupt clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTEIF2</name>
|
||
|
|
<description>Channel x transfer error clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHTIF2</name>
|
||
|
|
<description>Channel x half transfer clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTCIF2</name>
|
||
|
|
<description>Channel x transfer complete clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CGIF2</name>
|
||
|
|
<description>Channel x global interrupt clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTEIF1</name>
|
||
|
|
<description>Channel x transfer error clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHTIF1</name>
|
||
|
|
<description>Channel x half transfer clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTCIF1</name>
|
||
|
|
<description>Channel x transfer complete clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CGIF1</name>
|
||
|
|
<description>Channel x global interrupt clear (x = 1
|
||
|
|
..7)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR1</name>
|
||
|
|
<displayName>CCR1</displayName>
|
||
|
|
<description>channel x configuration
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MEM2MEM</name>
|
||
|
|
<description>Memory to memory mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PL</name>
|
||
|
|
<description>Channel priority level</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIZE</name>
|
||
|
|
<description>Memory size</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PSIZE</name>
|
||
|
|
<description>Peripheral size</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MINC</name>
|
||
|
|
<description>Memory increment mode</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PINC</name>
|
||
|
|
<description>Peripheral increment mode</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CIRC</name>
|
||
|
|
<description>Circular mode</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIR</name>
|
||
|
|
<description>Data transfer direction</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIE</name>
|
||
|
|
<description>Transfer error interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIE</name>
|
||
|
|
<description>Half transfer interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIE</name>
|
||
|
|
<description>Transfer complete interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EN</name>
|
||
|
|
<description>Channel enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNDTR1</name>
|
||
|
|
<displayName>CNDTR1</displayName>
|
||
|
|
<description>channel x number of data
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>NDT</name>
|
||
|
|
<description>Number of data to transfer</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CPAR1</name>
|
||
|
|
<displayName>CPAR1</displayName>
|
||
|
|
<description>channel x peripheral address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PA</name>
|
||
|
|
<description>Peripheral address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CMAR1</name>
|
||
|
|
<displayName>CMAR1</displayName>
|
||
|
|
<description>channel x memory address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MA</name>
|
||
|
|
<description>Memory address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR2</name>
|
||
|
|
<displayName>CCR2</displayName>
|
||
|
|
<description>channel x configuration
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MEM2MEM</name>
|
||
|
|
<description>Memory to memory mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PL</name>
|
||
|
|
<description>Channel priority level</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIZE</name>
|
||
|
|
<description>Memory size</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PSIZE</name>
|
||
|
|
<description>Peripheral size</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MINC</name>
|
||
|
|
<description>Memory increment mode</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PINC</name>
|
||
|
|
<description>Peripheral increment mode</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CIRC</name>
|
||
|
|
<description>Circular mode</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIR</name>
|
||
|
|
<description>Data transfer direction</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIE</name>
|
||
|
|
<description>Transfer error interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIE</name>
|
||
|
|
<description>Half transfer interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIE</name>
|
||
|
|
<description>Transfer complete interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EN</name>
|
||
|
|
<description>Channel enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNDTR2</name>
|
||
|
|
<displayName>CNDTR2</displayName>
|
||
|
|
<description>channel x number of data
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>NDT</name>
|
||
|
|
<description>Number of data to transfer</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CPAR2</name>
|
||
|
|
<displayName>CPAR2</displayName>
|
||
|
|
<description>channel x peripheral address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PA</name>
|
||
|
|
<description>Peripheral address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CMAR2</name>
|
||
|
|
<displayName>CMAR2</displayName>
|
||
|
|
<description>channel x memory address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MA</name>
|
||
|
|
<description>Memory address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR3</name>
|
||
|
|
<displayName>CCR3</displayName>
|
||
|
|
<description>channel x configuration
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x30</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MEM2MEM</name>
|
||
|
|
<description>Memory to memory mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PL</name>
|
||
|
|
<description>Channel priority level</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIZE</name>
|
||
|
|
<description>Memory size</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PSIZE</name>
|
||
|
|
<description>Peripheral size</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MINC</name>
|
||
|
|
<description>Memory increment mode</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PINC</name>
|
||
|
|
<description>Peripheral increment mode</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CIRC</name>
|
||
|
|
<description>Circular mode</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIR</name>
|
||
|
|
<description>Data transfer direction</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIE</name>
|
||
|
|
<description>Transfer error interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIE</name>
|
||
|
|
<description>Half transfer interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIE</name>
|
||
|
|
<description>Transfer complete interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EN</name>
|
||
|
|
<description>Channel enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNDTR3</name>
|
||
|
|
<displayName>CNDTR3</displayName>
|
||
|
|
<description>channel x number of data
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x34</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>NDT</name>
|
||
|
|
<description>Number of data to transfer</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CPAR3</name>
|
||
|
|
<displayName>CPAR3</displayName>
|
||
|
|
<description>channel x peripheral address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x38</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PA</name>
|
||
|
|
<description>Peripheral address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CMAR3</name>
|
||
|
|
<displayName>CMAR3</displayName>
|
||
|
|
<description>channel x memory address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x3C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MA</name>
|
||
|
|
<description>Memory address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR4</name>
|
||
|
|
<displayName>CCR4</displayName>
|
||
|
|
<description>channel x configuration
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x44</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MEM2MEM</name>
|
||
|
|
<description>Memory to memory mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PL</name>
|
||
|
|
<description>Channel priority level</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIZE</name>
|
||
|
|
<description>Memory size</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PSIZE</name>
|
||
|
|
<description>Peripheral size</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MINC</name>
|
||
|
|
<description>Memory increment mode</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PINC</name>
|
||
|
|
<description>Peripheral increment mode</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CIRC</name>
|
||
|
|
<description>Circular mode</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIR</name>
|
||
|
|
<description>Data transfer direction</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIE</name>
|
||
|
|
<description>Transfer error interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIE</name>
|
||
|
|
<description>Half transfer interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIE</name>
|
||
|
|
<description>Transfer complete interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EN</name>
|
||
|
|
<description>Channel enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNDTR4</name>
|
||
|
|
<displayName>CNDTR4</displayName>
|
||
|
|
<description>channel x number of data
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x48</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>NDT</name>
|
||
|
|
<description>Number of data to transfer</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CPAR4</name>
|
||
|
|
<displayName>CPAR4</displayName>
|
||
|
|
<description>channel x peripheral address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x4C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PA</name>
|
||
|
|
<description>Peripheral address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CMAR4</name>
|
||
|
|
<displayName>CMAR4</displayName>
|
||
|
|
<description>channel x memory address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x50</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MA</name>
|
||
|
|
<description>Memory address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR5</name>
|
||
|
|
<displayName>CCR5</displayName>
|
||
|
|
<description>channel x configuration
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x58</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MEM2MEM</name>
|
||
|
|
<description>Memory to memory mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PL</name>
|
||
|
|
<description>Channel priority level</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIZE</name>
|
||
|
|
<description>Memory size</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PSIZE</name>
|
||
|
|
<description>Peripheral size</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MINC</name>
|
||
|
|
<description>Memory increment mode</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PINC</name>
|
||
|
|
<description>Peripheral increment mode</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CIRC</name>
|
||
|
|
<description>Circular mode</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIR</name>
|
||
|
|
<description>Data transfer direction</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIE</name>
|
||
|
|
<description>Transfer error interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIE</name>
|
||
|
|
<description>Half transfer interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIE</name>
|
||
|
|
<description>Transfer complete interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EN</name>
|
||
|
|
<description>Channel enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNDTR5</name>
|
||
|
|
<displayName>CNDTR5</displayName>
|
||
|
|
<description>channel x number of data
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x5C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>NDT</name>
|
||
|
|
<description>Number of data to transfer</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CPAR5</name>
|
||
|
|
<displayName>CPAR5</displayName>
|
||
|
|
<description>channel x peripheral address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x60</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PA</name>
|
||
|
|
<description>Peripheral address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CMAR5</name>
|
||
|
|
<displayName>CMAR5</displayName>
|
||
|
|
<description>channel x memory address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x64</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MA</name>
|
||
|
|
<description>Memory address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR6</name>
|
||
|
|
<displayName>CCR6</displayName>
|
||
|
|
<description>channel x configuration
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x6C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MEM2MEM</name>
|
||
|
|
<description>Memory to memory mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PL</name>
|
||
|
|
<description>Channel priority level</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIZE</name>
|
||
|
|
<description>Memory size</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PSIZE</name>
|
||
|
|
<description>Peripheral size</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MINC</name>
|
||
|
|
<description>Memory increment mode</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PINC</name>
|
||
|
|
<description>Peripheral increment mode</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CIRC</name>
|
||
|
|
<description>Circular mode</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIR</name>
|
||
|
|
<description>Data transfer direction</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIE</name>
|
||
|
|
<description>Transfer error interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIE</name>
|
||
|
|
<description>Half transfer interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIE</name>
|
||
|
|
<description>Transfer complete interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EN</name>
|
||
|
|
<description>Channel enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNDTR6</name>
|
||
|
|
<displayName>CNDTR6</displayName>
|
||
|
|
<description>channel x number of data
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x70</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>NDT</name>
|
||
|
|
<description>Number of data to transfer</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CPAR6</name>
|
||
|
|
<displayName>CPAR6</displayName>
|
||
|
|
<description>channel x peripheral address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x74</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PA</name>
|
||
|
|
<description>Peripheral address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CMAR6</name>
|
||
|
|
<displayName>CMAR6</displayName>
|
||
|
|
<description>channel x memory address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x78</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MA</name>
|
||
|
|
<description>Memory address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR7</name>
|
||
|
|
<displayName>CCR7</displayName>
|
||
|
|
<description>channel x configuration
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x80</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MEM2MEM</name>
|
||
|
|
<description>Memory to memory mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PL</name>
|
||
|
|
<description>Channel priority level</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIZE</name>
|
||
|
|
<description>Memory size</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PSIZE</name>
|
||
|
|
<description>Peripheral size</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MINC</name>
|
||
|
|
<description>Memory increment mode</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PINC</name>
|
||
|
|
<description>Peripheral increment mode</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CIRC</name>
|
||
|
|
<description>Circular mode</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIR</name>
|
||
|
|
<description>Data transfer direction</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEIE</name>
|
||
|
|
<description>Transfer error interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HTIE</name>
|
||
|
|
<description>Half transfer interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIE</name>
|
||
|
|
<description>Transfer complete interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EN</name>
|
||
|
|
<description>Channel enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNDTR7</name>
|
||
|
|
<displayName>CNDTR7</displayName>
|
||
|
|
<description>channel x number of data
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x84</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>NDT</name>
|
||
|
|
<description>Number of data to transfer</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CPAR7</name>
|
||
|
|
<displayName>CPAR7</displayName>
|
||
|
|
<description>channel x peripheral address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x88</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PA</name>
|
||
|
|
<description>Peripheral address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CMAR7</name>
|
||
|
|
<displayName>CMAR7</displayName>
|
||
|
|
<description>channel x memory address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x8C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MA</name>
|
||
|
|
<description>Memory address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CSELR</name>
|
||
|
|
<displayName>CSELR</displayName>
|
||
|
|
<description>channel selection register</description>
|
||
|
|
<addressOffset>0xA8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>C7S</name>
|
||
|
|
<description>DMA channel 7 selection</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>C6S</name>
|
||
|
|
<description>DMA channel 6 selection</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>C5S</name>
|
||
|
|
<description>DMA channel 5 selection</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>C4S</name>
|
||
|
|
<description>DMA channel 4 selection</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>C3S</name>
|
||
|
|
<description>DMA channel 3 selection</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>C2S</name>
|
||
|
|
<description>DMA channel 2 selection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>C1S</name>
|
||
|
|
<description>DMA channel 1 selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>CRC</name>
|
||
|
|
<description>Cyclic redundancy check calculation
|
||
|
|
unit</description>
|
||
|
|
<groupName>CRC</groupName>
|
||
|
|
<baseAddress>0x40023000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>DR</name>
|
||
|
|
<displayName>DR</displayName>
|
||
|
|
<description>Data register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DR</name>
|
||
|
|
<description>Data register bits</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IDR</name>
|
||
|
|
<displayName>IDR</displayName>
|
||
|
|
<description>Independent data register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>IDR</name>
|
||
|
|
<description>General-purpose 8-bit data register
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR</name>
|
||
|
|
<displayName>CR</displayName>
|
||
|
|
<description>Control register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>REV_OUT</name>
|
||
|
|
<description>Reverse output data</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>REV_IN</name>
|
||
|
|
<description>Reverse input data</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>POLYSIZE</name>
|
||
|
|
<description>Polynomial size</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RESET</name>
|
||
|
|
<description>RESET bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>write-only</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>INIT</name>
|
||
|
|
<displayName>INIT</displayName>
|
||
|
|
<description>Initial CRC value</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CRC_INIT</name>
|
||
|
|
<description>Programmable initial CRC
|
||
|
|
value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>POL</name>
|
||
|
|
<displayName>POL</displayName>
|
||
|
|
<description>polynomial</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x04C11DB7</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>Polynomialcoefficients</name>
|
||
|
|
<description>Programmable polynomial</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>GPIOA</name>
|
||
|
|
<description>General-purpose I/Os</description>
|
||
|
|
<groupName>GPIO</groupName>
|
||
|
|
<baseAddress>0x50000000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>MODER</name>
|
||
|
|
<displayName>MODER</displayName>
|
||
|
|
<description>GPIO port mode register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0xEBFFFCFF</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MODE0</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE1</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE2</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE3</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE4</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE5</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE6</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE7</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE8</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE9</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE10</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE11</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE12</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE13</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE14</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE15</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OTYPER</name>
|
||
|
|
<displayName>OTYPER</displayName>
|
||
|
|
<description>GPIO port output type register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OT15</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT14</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT13</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT12</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT11</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT10</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT9</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT8</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT7</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT6</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT5</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT4</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT3</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT2</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT1</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT0</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OSPEEDR</name>
|
||
|
|
<displayName>OSPEEDR</displayName>
|
||
|
|
<description>GPIO port output speed
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED15</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED14</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED13</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED12</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED11</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED10</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED9</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED8</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED7</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED6</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED5</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED4</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED3</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED2</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED1</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED0</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PUPDR</name>
|
||
|
|
<displayName>PUPDR</displayName>
|
||
|
|
<description>GPIO port pull-up/pull-down
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x24000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PUPD15</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD14</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD13</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD12</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD11</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD10</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD9</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD8</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD7</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD6</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD5</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD4</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD3</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD2</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD1</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD0</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IDR</name>
|
||
|
|
<displayName>IDR</displayName>
|
||
|
|
<description>GPIO port input data register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ID15</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID14</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID13</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID12</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID11</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID10</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID9</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID8</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID7</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID6</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID5</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID4</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID3</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID2</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID1</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID0</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ODR</name>
|
||
|
|
<displayName>ODR</displayName>
|
||
|
|
<description>GPIO port output data register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OD15</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD14</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD13</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD12</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD11</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD10</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD9</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD8</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD7</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD6</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD5</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD4</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD3</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD2</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD1</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD0</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>BSRR</name>
|
||
|
|
<displayName>BSRR</displayName>
|
||
|
|
<description>GPIO port bit set/reset
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BR15</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR14</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR13</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>29</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR12</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR11</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>27</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR10</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR9</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR8</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR7</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR6</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR5</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR4</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR3</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR2</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR1</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR0</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS15</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS14</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS13</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS12</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS11</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS10</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS9</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS8</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS7</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS6</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS5</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS4</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS3</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS2</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS1</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS0</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>LCKR</name>
|
||
|
|
<displayName>LCKR</displayName>
|
||
|
|
<description>GPIO port configuration lock
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LCKK</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK15</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK14</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK13</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK12</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK11</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK10</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK9</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK8</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK7</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK6</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK5</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK4</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK3</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK2</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK1</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK0</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>AFRL</name>
|
||
|
|
<displayName>AFRL</displayName>
|
||
|
|
<description>GPIO alternate function low
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL7</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL6</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL5</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL4</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL3</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL2</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL1</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL0</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>AFRH</name>
|
||
|
|
<displayName>AFRH</displayName>
|
||
|
|
<description>GPIO alternate function high
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL15</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL14</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL13</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL12</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL11</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL10</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL9</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL8</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>BRR</name>
|
||
|
|
<displayName>BRR</displayName>
|
||
|
|
<description>GPIO port bit reset register</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BR15</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR14</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR13</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR12</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR11</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR10</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR9</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR8</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR7</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR6</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR5</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR4</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR3</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR2</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR1</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR0</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>GPIOB</name>
|
||
|
|
<description>General-purpose I/Os</description>
|
||
|
|
<groupName>GPIO</groupName>
|
||
|
|
<baseAddress>0x50000400</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>MODER</name>
|
||
|
|
<displayName>MODER</displayName>
|
||
|
|
<description>GPIO port mode register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MODE15</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE14</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE13</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE12</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE11</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE10</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE9</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE8</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE7</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE6</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE5</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE4</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE3</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE2</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE1</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODE0</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OTYPER</name>
|
||
|
|
<displayName>OTYPER</displayName>
|
||
|
|
<description>GPIO port output type register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OT15</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT14</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT13</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT12</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT11</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT10</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT9</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT8</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT7</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT6</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT5</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT4</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT3</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT2</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT1</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OT0</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OSPEEDR</name>
|
||
|
|
<displayName>OSPEEDR</displayName>
|
||
|
|
<description>GPIO port output speed
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED15</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED14</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED13</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED12</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED11</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED10</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED9</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED8</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED7</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED6</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED5</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED4</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED3</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED2</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED1</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSPEED0</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PUPDR</name>
|
||
|
|
<displayName>PUPDR</displayName>
|
||
|
|
<description>GPIO port pull-up/pull-down
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PUPD15</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD14</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD13</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD12</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD11</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD10</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD9</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD8</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD7</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD6</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD5</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD4</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD3</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD2</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD1</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PUPD0</name>
|
||
|
|
<description>Port x configuration bits (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IDR</name>
|
||
|
|
<displayName>IDR</displayName>
|
||
|
|
<description>GPIO port input data register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ID15</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID14</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID13</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID12</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID11</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID10</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID9</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID8</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID7</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID6</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID5</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID4</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID3</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID2</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID1</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ID0</name>
|
||
|
|
<description>Port input data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ODR</name>
|
||
|
|
<displayName>ODR</displayName>
|
||
|
|
<description>GPIO port output data register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OD15</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD14</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD13</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD12</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD11</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD10</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD9</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD8</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD7</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD6</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD5</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD4</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD3</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD2</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD1</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OD0</name>
|
||
|
|
<description>Port output data bit (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>BSRR</name>
|
||
|
|
<displayName>BSRR</displayName>
|
||
|
|
<description>GPIO port bit set/reset
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BR15</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR14</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR13</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>29</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR12</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR11</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>27</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR10</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR9</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR8</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR7</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR6</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR5</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR4</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR3</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR2</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR1</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR0</name>
|
||
|
|
<description>Port x reset bit y (y =
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS15</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS14</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS13</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS12</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS11</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS10</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS9</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS8</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS7</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS6</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS5</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS4</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS3</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS2</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS1</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BS0</name>
|
||
|
|
<description>Port x set bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>LCKR</name>
|
||
|
|
<displayName>LCKR</displayName>
|
||
|
|
<description>GPIO port configuration lock
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LCKK</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK15</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK14</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK13</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK12</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK11</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK10</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK9</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK8</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK7</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK6</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK5</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK4</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK3</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK2</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK1</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LCK0</name>
|
||
|
|
<description>Port x lock bit y (y=
|
||
|
|
0..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>AFRL</name>
|
||
|
|
<displayName>AFRL</displayName>
|
||
|
|
<description>GPIO alternate function low
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL7</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL6</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL5</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL4</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL3</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL2</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL1</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL0</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 0..7)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>AFRH</name>
|
||
|
|
<displayName>AFRH</displayName>
|
||
|
|
<description>GPIO alternate function high
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL15</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL14</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL13</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL12</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL11</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL10</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL9</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AFSEL8</name>
|
||
|
|
<description>Alternate function selection for port x
|
||
|
|
pin y (y = 8..15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>BRR</name>
|
||
|
|
<displayName>BRR</displayName>
|
||
|
|
<description>GPIO port bit reset register</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BR15</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR14</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR13</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR12</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR11</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR10</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR9</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR8</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR7</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR6</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR5</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR4</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR3</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR2</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR1</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR0</name>
|
||
|
|
<description>Port x Reset bit y (y= 0 ..
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="GPIOB">
|
||
|
|
<name>GPIOC</name>
|
||
|
|
<baseAddress>0x50000800</baseAddress>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="GPIOB">
|
||
|
|
<name>GPIOD</name>
|
||
|
|
<baseAddress>0x50000C00</baseAddress>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="GPIOB">
|
||
|
|
<name>GPIOH</name>
|
||
|
|
<baseAddress>0x50001C00</baseAddress>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="GPIOB">
|
||
|
|
<name>GPIOE</name>
|
||
|
|
<baseAddress>0x50001000</baseAddress>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>LPTIM</name>
|
||
|
|
<description>Low power timer</description>
|
||
|
|
<groupName>LPTIM</groupName>
|
||
|
|
<baseAddress>0x40007C00</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>LPTIM1</name>
|
||
|
|
<description>LPTIMER1 interrupt through
|
||
|
|
EXTI29</description>
|
||
|
|
<value>13</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>ISR</name>
|
||
|
|
<displayName>ISR</displayName>
|
||
|
|
<description>Interrupt and Status Register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DOWN</name>
|
||
|
|
<description>Counter direction change up to
|
||
|
|
down</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UP</name>
|
||
|
|
<description>Counter direction change down to
|
||
|
|
up</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARROK</name>
|
||
|
|
<description>Autoreload register update
|
||
|
|
OK</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMPOK</name>
|
||
|
|
<description>Compare register update OK</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTTRIG</name>
|
||
|
|
<description>External trigger edge
|
||
|
|
event</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARRM</name>
|
||
|
|
<description>Autoreload match</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMPM</name>
|
||
|
|
<description>Compare match</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ICR</name>
|
||
|
|
<displayName>ICR</displayName>
|
||
|
|
<description>Interrupt Clear Register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DOWNCF</name>
|
||
|
|
<description>Direction change to down Clear
|
||
|
|
Flag</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UPCF</name>
|
||
|
|
<description>Direction change to UP Clear
|
||
|
|
Flag</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARROKCF</name>
|
||
|
|
<description>Autoreload register update OK Clear
|
||
|
|
Flag</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMPOKCF</name>
|
||
|
|
<description>Compare register update OK Clear
|
||
|
|
Flag</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTTRIGCF</name>
|
||
|
|
<description>External trigger valid edge Clear
|
||
|
|
Flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARRMCF</name>
|
||
|
|
<description>Autoreload match Clear
|
||
|
|
Flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMPMCF</name>
|
||
|
|
<description>compare match Clear Flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IER</name>
|
||
|
|
<displayName>IER</displayName>
|
||
|
|
<description>Interrupt Enable Register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DOWNIE</name>
|
||
|
|
<description>Direction change to down Interrupt
|
||
|
|
Enable</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UPIE</name>
|
||
|
|
<description>Direction change to UP Interrupt
|
||
|
|
Enable</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARROKIE</name>
|
||
|
|
<description>Autoreload register update OK Interrupt
|
||
|
|
Enable</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMPOKIE</name>
|
||
|
|
<description>Compare register update OK Interrupt
|
||
|
|
Enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTTRIGIE</name>
|
||
|
|
<description>External trigger valid edge Interrupt
|
||
|
|
Enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARRMIE</name>
|
||
|
|
<description>Autoreload match Interrupt
|
||
|
|
Enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMPMIE</name>
|
||
|
|
<description>Compare match Interrupt
|
||
|
|
Enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CFGR</name>
|
||
|
|
<displayName>CFGR</displayName>
|
||
|
|
<description>Configuration Register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ENC</name>
|
||
|
|
<description>Encoder mode enable</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COUNTMODE</name>
|
||
|
|
<description>counter mode enabled</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRELOAD</name>
|
||
|
|
<description>Registers update mode</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WAVPOL</name>
|
||
|
|
<description>Waveform shape polarity</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WAVE</name>
|
||
|
|
<description>Waveform shape</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIMOUT</name>
|
||
|
|
<description>Timeout enable</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TRIGEN</name>
|
||
|
|
<description>Trigger enable and
|
||
|
|
polarity</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TRIGSEL</name>
|
||
|
|
<description>Trigger selector</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRESC</name>
|
||
|
|
<description>Clock prescaler</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TRGFLT</name>
|
||
|
|
<description>Configurable digital filter for
|
||
|
|
trigger</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CKFLT</name>
|
||
|
|
<description>Configurable digital filter for external
|
||
|
|
clock</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CKPOL</name>
|
||
|
|
<description>Clock Polarity</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CKSEL</name>
|
||
|
|
<description>Clock selector</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR</name>
|
||
|
|
<displayName>CR</displayName>
|
||
|
|
<description>Control Register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CNTSTRT</name>
|
||
|
|
<description>Timer start in continuous
|
||
|
|
mode</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SNGSTRT</name>
|
||
|
|
<description>LPTIM start in single mode</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ENABLE</name>
|
||
|
|
<description>LPTIM Enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CMP</name>
|
||
|
|
<displayName>CMP</displayName>
|
||
|
|
<description>Compare Register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CMP</name>
|
||
|
|
<description>Compare value.</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ARR</name>
|
||
|
|
<displayName>ARR</displayName>
|
||
|
|
<description>Autoreload Register</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000001</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ARR</name>
|
||
|
|
<description>Auto reload value.</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNT</name>
|
||
|
|
<displayName>CNT</displayName>
|
||
|
|
<description>Counter Register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CNT</name>
|
||
|
|
<description>Counter value.</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>RTC</name>
|
||
|
|
<description>Real-time clock</description>
|
||
|
|
<groupName>RTC</groupName>
|
||
|
|
<baseAddress>0x40002800</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>RTC</name>
|
||
|
|
<description>RTC global interrupt</description>
|
||
|
|
<value>2</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>TR</name>
|
||
|
|
<displayName>TR</displayName>
|
||
|
|
<description>RTC time register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PM</name>
|
||
|
|
<description>AM/PM notation</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HT</name>
|
||
|
|
<description>Hour tens in BCD format</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HU</name>
|
||
|
|
<description>Hour units in BCD format</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MNT</name>
|
||
|
|
<description>Minute tens in BCD format</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MNU</name>
|
||
|
|
<description>Minute units in BCD format</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ST</name>
|
||
|
|
<description>Second tens in BCD format</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SU</name>
|
||
|
|
<description>Second units in BCD format</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>DR</name>
|
||
|
|
<displayName>DR</displayName>
|
||
|
|
<description>RTC date register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>YT</name>
|
||
|
|
<description>Year tens in BCD format</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>YU</name>
|
||
|
|
<description>Year units in BCD format</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WDU</name>
|
||
|
|
<description>Week day units</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MT</name>
|
||
|
|
<description>Month tens in BCD format</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MU</name>
|
||
|
|
<description>Month units in BCD format</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DT</name>
|
||
|
|
<description>Date tens in BCD format</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DU</name>
|
||
|
|
<description>Date units in BCD format</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR</name>
|
||
|
|
<displayName>CR</displayName>
|
||
|
|
<description>RTC control register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>COE</name>
|
||
|
|
<description>Calibration output enable</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OSEL</name>
|
||
|
|
<description>Output selection</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>POL</name>
|
||
|
|
<description>Output polarity</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COSEL</name>
|
||
|
|
<description>Calibration output
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BKP</name>
|
||
|
|
<description>Backup</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SUB1H</name>
|
||
|
|
<description>Subtract 1 hour (winter time
|
||
|
|
change)</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>write-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADD1H</name>
|
||
|
|
<description>Add 1 hour (summer time
|
||
|
|
change)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>write-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TSIE</name>
|
||
|
|
<description>Time-stamp interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WUTIE</name>
|
||
|
|
<description>Wakeup timer interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ALRBIE</name>
|
||
|
|
<description>Alarm B interrupt enable</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ALRAIE</name>
|
||
|
|
<description>Alarm A interrupt enable</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TSE</name>
|
||
|
|
<description>timestamp enable</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WUTE</name>
|
||
|
|
<description>Wakeup timer enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ALRBE</name>
|
||
|
|
<description>Alarm B enable</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ALRAE</name>
|
||
|
|
<description>Alarm A enable</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FMT</name>
|
||
|
|
<description>Hour format</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BYPSHAD</name>
|
||
|
|
<description>Bypass the shadow
|
||
|
|
registers</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>REFCKON</name>
|
||
|
|
<description>RTC_REFIN reference clock detection
|
||
|
|
enable (50 or 60 Hz)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TSEDGE</name>
|
||
|
|
<description>Time-stamp event active
|
||
|
|
edge</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WUCKSEL</name>
|
||
|
|
<description>Wakeup clock selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ISR</name>
|
||
|
|
<displayName>ISR</displayName>
|
||
|
|
<description>RTC initialization and status
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TAMP2F</name>
|
||
|
|
<description>RTC_TAMP2 detection flag</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMP1F</name>
|
||
|
|
<description>RTC_TAMP1 detection flag</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TSOVF</name>
|
||
|
|
<description>Time-stamp overflow flag</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TSF</name>
|
||
|
|
<description>Time-stamp flag</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WUTF</name>
|
||
|
|
<description>Wakeup timer flag</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ALRBF</name>
|
||
|
|
<description>Alarm B flag</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ALRAF</name>
|
||
|
|
<description>Alarm A flag</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>INIT</name>
|
||
|
|
<description>Initialization mode</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>INITF</name>
|
||
|
|
<description>Initialization flag</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RSF</name>
|
||
|
|
<description>Registers synchronization
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>INITS</name>
|
||
|
|
<description>Initialization status flag</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SHPF</name>
|
||
|
|
<description>Shift operation pending</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WUTWF</name>
|
||
|
|
<description>Wakeup timer write flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ALRBWF</name>
|
||
|
|
<description>Alarm B write flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ALRAWF</name>
|
||
|
|
<description>Alarm A write flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PRER</name>
|
||
|
|
<displayName>PRER</displayName>
|
||
|
|
<description>RTC prescaler register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PREDIV_A</name>
|
||
|
|
<description>Asynchronous prescaler
|
||
|
|
factor</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>7</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PREDIV_S</name>
|
||
|
|
<description>Synchronous prescaler
|
||
|
|
factor</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>WUTR</name>
|
||
|
|
<displayName>WUTR</displayName>
|
||
|
|
<description>RTC wakeup timer register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>WUT</name>
|
||
|
|
<description>Wakeup auto-reload value
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ALRMAR</name>
|
||
|
|
<displayName>ALRMAR</displayName>
|
||
|
|
<description>RTC alarm A register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MSK4</name>
|
||
|
|
<description>Alarm A date mask</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WDSEL</name>
|
||
|
|
<description>Week day selection</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DT</name>
|
||
|
|
<description>Date tens in BCD format.</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DU</name>
|
||
|
|
<description>Date units or day in BCD
|
||
|
|
format.</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSK3</name>
|
||
|
|
<description>Alarm A hours mask</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PM</name>
|
||
|
|
<description>AM/PM notation</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HT</name>
|
||
|
|
<description>Hour tens in BCD format.</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HU</name>
|
||
|
|
<description>Hour units in BCD format.</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSK2</name>
|
||
|
|
<description>Alarm A minutes mask</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MNT</name>
|
||
|
|
<description>Minute tens in BCD format.</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MNU</name>
|
||
|
|
<description>Minute units in BCD
|
||
|
|
format.</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSK1</name>
|
||
|
|
<description>Alarm A seconds mask</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ST</name>
|
||
|
|
<description>Second tens in BCD format.</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SU</name>
|
||
|
|
<description>Second units in BCD
|
||
|
|
format.</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ALRMBR</name>
|
||
|
|
<displayName>ALRMBR</displayName>
|
||
|
|
<description>RTC alarm B register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MSK4</name>
|
||
|
|
<description>Alarm B date mask</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WDSEL</name>
|
||
|
|
<description>Week day selection</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DT</name>
|
||
|
|
<description>Date tens in BCD format</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DU</name>
|
||
|
|
<description>Date units or day in BCD
|
||
|
|
format</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSK3</name>
|
||
|
|
<description>Alarm B hours mask</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PM</name>
|
||
|
|
<description>AM/PM notation</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HT</name>
|
||
|
|
<description>Hour tens in BCD format</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HU</name>
|
||
|
|
<description>Hour units in BCD format</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSK2</name>
|
||
|
|
<description>Alarm B minutes mask</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MNT</name>
|
||
|
|
<description>Minute tens in BCD format</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MNU</name>
|
||
|
|
<description>Minute units in BCD format</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSK1</name>
|
||
|
|
<description>Alarm B seconds mask</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ST</name>
|
||
|
|
<description>Second tens in BCD format</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SU</name>
|
||
|
|
<description>Second units in BCD format</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>WPR</name>
|
||
|
|
<displayName>WPR</displayName>
|
||
|
|
<description>write protection register</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>KEY</name>
|
||
|
|
<description>Write protection key</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SSR</name>
|
||
|
|
<displayName>SSR</displayName>
|
||
|
|
<description>RTC sub second register</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>SS</name>
|
||
|
|
<description>Sub second value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SHIFTR</name>
|
||
|
|
<displayName>SHIFTR</displayName>
|
||
|
|
<description>RTC shift control register</description>
|
||
|
|
<addressOffset>0x2C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ADD1S</name>
|
||
|
|
<description>Add one second</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SUBFS</name>
|
||
|
|
<description>Subtract a fraction of a
|
||
|
|
second</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>15</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>TSTR</name>
|
||
|
|
<displayName>TSTR</displayName>
|
||
|
|
<description>RTC timestamp time register</description>
|
||
|
|
<addressOffset>0x30</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PM</name>
|
||
|
|
<description>AM/PM notation</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HT</name>
|
||
|
|
<description>Hour tens in BCD format.</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HU</name>
|
||
|
|
<description>Hour units in BCD format.</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MNT</name>
|
||
|
|
<description>Minute tens in BCD format.</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MNU</name>
|
||
|
|
<description>Minute units in BCD
|
||
|
|
format.</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ST</name>
|
||
|
|
<description>Second tens in BCD format.</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SU</name>
|
||
|
|
<description>Second units in BCD
|
||
|
|
format.</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>TSDR</name>
|
||
|
|
<displayName>TSDR</displayName>
|
||
|
|
<description>RTC timestamp date register</description>
|
||
|
|
<addressOffset>0x34</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>WDU</name>
|
||
|
|
<description>Week day units</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MT</name>
|
||
|
|
<description>Month tens in BCD format</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MU</name>
|
||
|
|
<description>Month units in BCD format</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DT</name>
|
||
|
|
<description>Date tens in BCD format</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DU</name>
|
||
|
|
<description>Date units in BCD format</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>TSSSR</name>
|
||
|
|
<displayName>TSSSR</displayName>
|
||
|
|
<description>RTC time-stamp sub second
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x38</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>SS</name>
|
||
|
|
<description>Sub second value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CALR</name>
|
||
|
|
<displayName>CALR</displayName>
|
||
|
|
<description>RTC calibration register</description>
|
||
|
|
<addressOffset>0x3C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CALP</name>
|
||
|
|
<description>Increase frequency of RTC by 488.5
|
||
|
|
ppm</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CALW8</name>
|
||
|
|
<description>Use an 8-second calibration cycle
|
||
|
|
period</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CALW16</name>
|
||
|
|
<description>Use a 16-second calibration cycle
|
||
|
|
period</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CALM</name>
|
||
|
|
<description>Calibration minus</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>9</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>TAMPCR</name>
|
||
|
|
<displayName>TAMPCR</displayName>
|
||
|
|
<description>RTC tamper configuration
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x40</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TAMP2MF</name>
|
||
|
|
<description>Tamper 2 mask flag</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMP2NOERASE</name>
|
||
|
|
<description>Tamper 2 no erase</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMP2IE</name>
|
||
|
|
<description>Tamper 2 interrupt enable</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMP1MF</name>
|
||
|
|
<description>Tamper 1 mask flag</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMP1NOERASE</name>
|
||
|
|
<description>Tamper 1 no erase</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMP1IE</name>
|
||
|
|
<description>Tamper 1 interrupt enable</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMPPUDIS</name>
|
||
|
|
<description>RTC_TAMPx pull-up disable</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMPPRCH</name>
|
||
|
|
<description>RTC_TAMPx precharge
|
||
|
|
duration</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMPFLT</name>
|
||
|
|
<description>RTC_TAMPx filter count</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMPFREQ</name>
|
||
|
|
<description>Tamper sampling frequency</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMPTS</name>
|
||
|
|
<description>Activate timestamp on tamper detection
|
||
|
|
event</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMP2_TRG</name>
|
||
|
|
<description>Active level for RTC_TAMP2
|
||
|
|
input</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMP2E</name>
|
||
|
|
<description>RTC_TAMP2 input detection
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMPIE</name>
|
||
|
|
<description>Tamper interrupt enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMP1TRG</name>
|
||
|
|
<description>Active level for RTC_TAMP1
|
||
|
|
input</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAMP1E</name>
|
||
|
|
<description>RTC_TAMP1 input detection
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ALRMASSR</name>
|
||
|
|
<displayName>ALRMASSR</displayName>
|
||
|
|
<description>RTC alarm A sub second
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x44</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MASKSS</name>
|
||
|
|
<description>Mask the most-significant bits starting
|
||
|
|
at this bit</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SS</name>
|
||
|
|
<description>Sub seconds value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>15</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ALRMBSSR</name>
|
||
|
|
<displayName>ALRMBSSR</displayName>
|
||
|
|
<description>RTC alarm B sub second
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x48</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MASKSS</name>
|
||
|
|
<description>Mask the most-significant bits starting
|
||
|
|
at this bit</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SS</name>
|
||
|
|
<description>Sub seconds value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>15</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OR</name>
|
||
|
|
<displayName>OR</displayName>
|
||
|
|
<description>option register</description>
|
||
|
|
<addressOffset>0x4C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RTC_OUT_RMP</name>
|
||
|
|
<description>RTC_ALARM on PC13 output
|
||
|
|
type</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTC_ALARM_TYPE</name>
|
||
|
|
<description>RTC_ALARM on PC13 output
|
||
|
|
type</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>BKP0R</name>
|
||
|
|
<displayName>BKP0R</displayName>
|
||
|
|
<description>RTC backup registers</description>
|
||
|
|
<addressOffset>0x50</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BKP</name>
|
||
|
|
<description>BKP</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>BKP1R</name>
|
||
|
|
<displayName>BKP1R</displayName>
|
||
|
|
<description>RTC backup registers</description>
|
||
|
|
<addressOffset>0x54</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BKP</name>
|
||
|
|
<description>BKP</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>BKP2R</name>
|
||
|
|
<displayName>BKP2R</displayName>
|
||
|
|
<description>RTC backup registers</description>
|
||
|
|
<addressOffset>0x58</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BKP</name>
|
||
|
|
<description>BKP</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>BKP3R</name>
|
||
|
|
<displayName>BKP3R</displayName>
|
||
|
|
<description>RTC backup registers</description>
|
||
|
|
<addressOffset>0x5C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BKP</name>
|
||
|
|
<description>BKP</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>BKP4R</name>
|
||
|
|
<displayName>BKP4R</displayName>
|
||
|
|
<description>RTC backup registers</description>
|
||
|
|
<addressOffset>0x60</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BKP</name>
|
||
|
|
<description>BKP</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>USART1</name>
|
||
|
|
<description>Universal synchronous asynchronous receiver
|
||
|
|
transmitter</description>
|
||
|
|
<groupName>USART</groupName>
|
||
|
|
<baseAddress>0x40013800</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>USART1</name>
|
||
|
|
<description>USART1 global interrupt</description>
|
||
|
|
<value>27</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR1</name>
|
||
|
|
<displayName>CR1</displayName>
|
||
|
|
<description>Control register 1</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>M1</name>
|
||
|
|
<description>Word length</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOBIE</name>
|
||
|
|
<description>End of Block interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>27</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTOIE</name>
|
||
|
|
<description>Receiver timeout interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEAT4</name>
|
||
|
|
<description>Driver Enable assertion
|
||
|
|
time</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEAT3</name>
|
||
|
|
<description>DEAT3</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEAT2</name>
|
||
|
|
<description>DEAT2</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEAT1</name>
|
||
|
|
<description>DEAT1</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEAT0</name>
|
||
|
|
<description>DEAT0</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEDT4</name>
|
||
|
|
<description>Driver Enable de-assertion
|
||
|
|
time</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEDT3</name>
|
||
|
|
<description>DEDT3</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEDT2</name>
|
||
|
|
<description>DEDT2</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEDT1</name>
|
||
|
|
<description>DEDT1</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEDT0</name>
|
||
|
|
<description>DEDT0</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OVER8</name>
|
||
|
|
<description>Oversampling mode</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMIE</name>
|
||
|
|
<description>Character match interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MME</name>
|
||
|
|
<description>Mute mode enable</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>M0</name>
|
||
|
|
<description>Word length</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WAKE</name>
|
||
|
|
<description>Receiver wakeup method</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PCE</name>
|
||
|
|
<description>Parity control enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PS</name>
|
||
|
|
<description>Parity selection</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PEIE</name>
|
||
|
|
<description>PE interrupt enable</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXEIE</name>
|
||
|
|
<description>interrupt enable</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIE</name>
|
||
|
|
<description>Transmission complete interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXNEIE</name>
|
||
|
|
<description>RXNE interrupt enable</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IDLEIE</name>
|
||
|
|
<description>IDLE interrupt enable</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TE</name>
|
||
|
|
<description>Transmitter enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RE</name>
|
||
|
|
<description>Receiver enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UESM</name>
|
||
|
|
<description>USART enable in Stop mode</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UE</name>
|
||
|
|
<description>USART enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR2</name>
|
||
|
|
<displayName>CR2</displayName>
|
||
|
|
<description>Control register 2</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ADD4_7</name>
|
||
|
|
<description>Address of the USART node</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADD0_3</name>
|
||
|
|
<description>Address of the USART node</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTOEN</name>
|
||
|
|
<description>Receiver timeout enable</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ABRMOD1</name>
|
||
|
|
<description>Auto baud rate mode</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ABRMOD0</name>
|
||
|
|
<description>ABRMOD0</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ABREN</name>
|
||
|
|
<description>Auto baud rate enable</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSBFIRST</name>
|
||
|
|
<description>Most significant bit first</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAINV</name>
|
||
|
|
<description>Binary data inversion</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXINV</name>
|
||
|
|
<description>TX pin active level
|
||
|
|
inversion</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXINV</name>
|
||
|
|
<description>RX pin active level
|
||
|
|
inversion</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWAP</name>
|
||
|
|
<description>Swap TX/RX pins</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LINEN</name>
|
||
|
|
<description>LIN mode enable</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>STOP</name>
|
||
|
|
<description>STOP bits</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CLKEN</name>
|
||
|
|
<description>Clock enable</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CPOL</name>
|
||
|
|
<description>Clock polarity</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CPHA</name>
|
||
|
|
<description>Clock phase</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LBCL</name>
|
||
|
|
<description>Last bit clock pulse</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LBDIE</name>
|
||
|
|
<description>LIN break detection interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LBDL</name>
|
||
|
|
<description>LIN break detection length</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADDM7</name>
|
||
|
|
<description>7-bit Address Detection/4-bit Address
|
||
|
|
Detection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR3</name>
|
||
|
|
<displayName>CR3</displayName>
|
||
|
|
<description>Control register 3</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>WUFIE</name>
|
||
|
|
<description>Wakeup from Stop mode interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WUS</name>
|
||
|
|
<description>Wakeup from Stop mode interrupt flag
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SCARCNT</name>
|
||
|
|
<description>Smartcard auto-retry count</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEP</name>
|
||
|
|
<description>Driver enable polarity
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEM</name>
|
||
|
|
<description>Driver enable mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DDRE</name>
|
||
|
|
<description>DMA Disable on Reception
|
||
|
|
Error</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OVRDIS</name>
|
||
|
|
<description>Overrun Disable</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ONEBIT</name>
|
||
|
|
<description>One sample bit method
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTSIE</name>
|
||
|
|
<description>CTS interrupt enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTSE</name>
|
||
|
|
<description>CTS enable</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTSE</name>
|
||
|
|
<description>RTS enable</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DMAT</name>
|
||
|
|
<description>DMA enable transmitter</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DMAR</name>
|
||
|
|
<description>DMA enable receiver</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SCEN</name>
|
||
|
|
<description>Smartcard mode enable</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NACK</name>
|
||
|
|
<description>Smartcard NACK enable</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HDSEL</name>
|
||
|
|
<description>Half-duplex selection</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IRLP</name>
|
||
|
|
<description>Ir low-power</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IREN</name>
|
||
|
|
<description>Ir mode enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EIE</name>
|
||
|
|
<description>Error interrupt enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>BRR</name>
|
||
|
|
<displayName>BRR</displayName>
|
||
|
|
<description>Baud rate register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DIV_Mantissa</name>
|
||
|
|
<description>DIV_Mantissa</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>12</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIV_Fraction</name>
|
||
|
|
<description>DIV_Fraction</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>GTPR</name>
|
||
|
|
<displayName>GTPR</displayName>
|
||
|
|
<description>Guard time and prescaler
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>GT</name>
|
||
|
|
<description>Guard time value</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PSC</name>
|
||
|
|
<description>Prescaler value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>RTOR</name>
|
||
|
|
<displayName>RTOR</displayName>
|
||
|
|
<description>Receiver timeout register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BLEN</name>
|
||
|
|
<description>Block Length</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTO</name>
|
||
|
|
<description>Receiver timeout value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>24</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>RQR</name>
|
||
|
|
<displayName>RQR</displayName>
|
||
|
|
<description>Request register</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TXFRQ</name>
|
||
|
|
<description>Transmit data flush
|
||
|
|
request</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXFRQ</name>
|
||
|
|
<description>Receive data flush request</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MMRQ</name>
|
||
|
|
<description>Mute mode request</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SBKRQ</name>
|
||
|
|
<description>Send break request</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ABRRQ</name>
|
||
|
|
<description>Auto baud rate request</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ISR</name>
|
||
|
|
<displayName>ISR</displayName>
|
||
|
|
<description>Interrupt & status
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00C0</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>REACK</name>
|
||
|
|
<description>REACK</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEACK</name>
|
||
|
|
<description>TEACK</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WUF</name>
|
||
|
|
<description>WUF</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RWU</name>
|
||
|
|
<description>RWU</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SBKF</name>
|
||
|
|
<description>SBKF</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMF</name>
|
||
|
|
<description>CMF</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BUSY</name>
|
||
|
|
<description>BUSY</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ABRF</name>
|
||
|
|
<description>ABRF</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ABRE</name>
|
||
|
|
<description>ABRE</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOBF</name>
|
||
|
|
<description>EOBF</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTOF</name>
|
||
|
|
<description>RTOF</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTS</name>
|
||
|
|
<description>CTS</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTSIF</name>
|
||
|
|
<description>CTSIF</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LBDF</name>
|
||
|
|
<description>LBDF</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXE</name>
|
||
|
|
<description>TXE</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TC</name>
|
||
|
|
<description>TC</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXNE</name>
|
||
|
|
<description>RXNE</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IDLE</name>
|
||
|
|
<description>IDLE</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ORE</name>
|
||
|
|
<description>ORE</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NF</name>
|
||
|
|
<description>NF</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FE</name>
|
||
|
|
<description>FE</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PE</name>
|
||
|
|
<description>PE</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ICR</name>
|
||
|
|
<displayName>ICR</displayName>
|
||
|
|
<description>Interrupt flag clear register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>WUCF</name>
|
||
|
|
<description>Wakeup from Stop mode clear
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMCF</name>
|
||
|
|
<description>Character match clear flag</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOBCF</name>
|
||
|
|
<description>End of block clear flag</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTOCF</name>
|
||
|
|
<description>Receiver timeout clear
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTSCF</name>
|
||
|
|
<description>CTS clear flag</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LBDCF</name>
|
||
|
|
<description>LIN break detection clear
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCCF</name>
|
||
|
|
<description>Transmission complete clear
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IDLECF</name>
|
||
|
|
<description>Idle line detected clear
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ORECF</name>
|
||
|
|
<description>Overrun error clear flag</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NCF</name>
|
||
|
|
<description>Noise detected clear flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FECF</name>
|
||
|
|
<description>Framing error clear flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PECF</name>
|
||
|
|
<description>Parity error clear flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>RDR</name>
|
||
|
|
<displayName>RDR</displayName>
|
||
|
|
<description>Receive data register</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RDR</name>
|
||
|
|
<description>Receive data value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>9</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>TDR</name>
|
||
|
|
<displayName>TDR</displayName>
|
||
|
|
<description>Transmit data register</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TDR</name>
|
||
|
|
<description>Transmit data value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>9</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="USART1">
|
||
|
|
<name>USART2</name>
|
||
|
|
<baseAddress>0x40004400</baseAddress>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="USART1">
|
||
|
|
<name>USART4</name>
|
||
|
|
<baseAddress>0x40004C00</baseAddress>
|
||
|
|
<interrupt>
|
||
|
|
<name>USART4_USART5</name>
|
||
|
|
<description>USART4/USART5 global interrupt</description>
|
||
|
|
<value>14</value>
|
||
|
|
</interrupt>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="USART1">
|
||
|
|
<name>USART5</name>
|
||
|
|
<baseAddress>0x40005000</baseAddress>
|
||
|
|
<interrupt>
|
||
|
|
<name>USART2</name>
|
||
|
|
<description>USART2 global interrupt</description>
|
||
|
|
<value>28</value>
|
||
|
|
</interrupt>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>IWDG</name>
|
||
|
|
<description>Independent watchdog</description>
|
||
|
|
<groupName>IWDG</groupName>
|
||
|
|
<baseAddress>0x40003000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>KR</name>
|
||
|
|
<displayName>KR</displayName>
|
||
|
|
<description>Key register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>KEY</name>
|
||
|
|
<description>Key value (write only, read
|
||
|
|
0x0000)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PR</name>
|
||
|
|
<displayName>PR</displayName>
|
||
|
|
<description>Prescaler register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PR</name>
|
||
|
|
<description>Prescaler divider</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>RLR</name>
|
||
|
|
<displayName>RLR</displayName>
|
||
|
|
<description>Reload register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000FFF</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RL</name>
|
||
|
|
<description>Watchdog counter reload
|
||
|
|
value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>12</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SR</name>
|
||
|
|
<displayName>SR</displayName>
|
||
|
|
<description>Status register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>WVU</name>
|
||
|
|
<description>Watchdog counter window value
|
||
|
|
update</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RVU</name>
|
||
|
|
<description>Watchdog counter reload value
|
||
|
|
update</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PVU</name>
|
||
|
|
<description>Watchdog prescaler value
|
||
|
|
update</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>WINR</name>
|
||
|
|
<displayName>WINR</displayName>
|
||
|
|
<description>Window register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000FFF</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>WIN</name>
|
||
|
|
<description>Watchdog counter window
|
||
|
|
value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>12</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>WWDG</name>
|
||
|
|
<description>System window watchdog</description>
|
||
|
|
<groupName>WWDG</groupName>
|
||
|
|
<baseAddress>0x40002C00</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>WWDG</name>
|
||
|
|
<description>Window Watchdog interrupt</description>
|
||
|
|
<value>0</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR</name>
|
||
|
|
<displayName>CR</displayName>
|
||
|
|
<description>Control register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000007F</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>WDGA</name>
|
||
|
|
<description>Activation bit</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>T</name>
|
||
|
|
<description>7-bit counter (MSB to LSB)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>7</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CFR</name>
|
||
|
|
<displayName>CFR</displayName>
|
||
|
|
<description>Configuration register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000007F</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>EWI</name>
|
||
|
|
<description>Early wakeup interrupt</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WDGTB1</name>
|
||
|
|
<description>Timer base</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WDGTB0</name>
|
||
|
|
<description>WDGTB0</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>W</name>
|
||
|
|
<description>7-bit window value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>7</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SR</name>
|
||
|
|
<displayName>SR</displayName>
|
||
|
|
<description>Status register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>EWIF</name>
|
||
|
|
<description>Early wakeup interrupt
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>Firewall</name>
|
||
|
|
<description>Firewall</description>
|
||
|
|
<groupName>Firewall</groupName>
|
||
|
|
<baseAddress>0x40011C00</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>FIREWALL_CSSA</name>
|
||
|
|
<displayName>FIREWALL_CSSA</displayName>
|
||
|
|
<description>Code segment start address</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ADD</name>
|
||
|
|
<description>code segment start address</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>FIREWALL_CSL</name>
|
||
|
|
<displayName>FIREWALL_CSL</displayName>
|
||
|
|
<description>Code segment length</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LENG</name>
|
||
|
|
<description>code segment length</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>14</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>FIREWALL_NVDSSA</name>
|
||
|
|
<displayName>FIREWALL_NVDSSA</displayName>
|
||
|
|
<description>Non-volatile data segment start
|
||
|
|
address</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ADD</name>
|
||
|
|
<description>Non-volatile data segment start
|
||
|
|
address</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>FIREWALL_NVDSL</name>
|
||
|
|
<displayName>FIREWALL_NVDSL</displayName>
|
||
|
|
<description>Non-volatile data segment
|
||
|
|
length</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LENG</name>
|
||
|
|
<description>Non-volatile data segment
|
||
|
|
length</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>14</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>FIREWALL_VDSSA</name>
|
||
|
|
<displayName>FIREWALL_VDSSA</displayName>
|
||
|
|
<description>Volatile data segment start
|
||
|
|
address</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ADD</name>
|
||
|
|
<description>Volatile data segment start
|
||
|
|
address</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>10</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>FIREWALL_VDSL</name>
|
||
|
|
<displayName>FIREWALL_VDSL</displayName>
|
||
|
|
<description>Volatile data segment length</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LENG</name>
|
||
|
|
<description>Non-volatile data segment
|
||
|
|
length</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>10</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>FIREWALL_CR</name>
|
||
|
|
<displayName>FIREWALL_CR</displayName>
|
||
|
|
<description>Configuration register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>VDE</name>
|
||
|
|
<description>Volatile data execution</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>VDS</name>
|
||
|
|
<description>Volatile data shared</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FPA</name>
|
||
|
|
<description>Firewall pre alarm</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>RCC</name>
|
||
|
|
<description>Reset and clock control</description>
|
||
|
|
<groupName>RCC</groupName>
|
||
|
|
<baseAddress>0x40021000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>RCC</name>
|
||
|
|
<description>RCC global interrupt</description>
|
||
|
|
<value>4</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR</name>
|
||
|
|
<displayName>CR</displayName>
|
||
|
|
<description>Clock control register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x00000300</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PLLRDY</name>
|
||
|
|
<description>PLL clock ready flag</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PLLON</name>
|
||
|
|
<description>PLL enable bit</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTCPRE</name>
|
||
|
|
<description>TC/LCD prescaler</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CSSLSEON</name>
|
||
|
|
<description>Clock security system on HSE enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSEBYP</name>
|
||
|
|
<description>HSE clock bypass bit</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSERDY</name>
|
||
|
|
<description>HSE clock ready flag</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSEON</name>
|
||
|
|
<description>HSE clock enable bit</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIRDY</name>
|
||
|
|
<description>MSI clock ready flag</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSION</name>
|
||
|
|
<description>MSI clock enable bit</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSI16DIVF</name>
|
||
|
|
<description>HSI16DIVF</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSI16DIVEN</name>
|
||
|
|
<description>HSI16DIVEN</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSI16RDYF</name>
|
||
|
|
<description>Internal high-speed clock ready
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSI16KERON</name>
|
||
|
|
<description>High-speed internal clock enable bit for
|
||
|
|
some IP kernels</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSI16ON</name>
|
||
|
|
<description>16 MHz high-speed internal clock
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSI16OUTEN</name>
|
||
|
|
<description>16 MHz high-speed internal clock output
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ICSCR</name>
|
||
|
|
<displayName>ICSCR</displayName>
|
||
|
|
<description>Internal clock sources calibration
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x0000B000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MSITRIM</name>
|
||
|
|
<description>MSI clock trimming</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSICAL</name>
|
||
|
|
<description>MSI clock calibration</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIRANGE</name>
|
||
|
|
<description>MSI clock ranges</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSI16TRIM</name>
|
||
|
|
<description>High speed internal clock
|
||
|
|
trimming</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>5</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSI16CAL</name>
|
||
|
|
<description>nternal high speed clock
|
||
|
|
calibration</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CFGR</name>
|
||
|
|
<displayName>CFGR</displayName>
|
||
|
|
<description>Clock configuration register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MCOPRE</name>
|
||
|
|
<description>Microcontroller clock output
|
||
|
|
prescaler</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MCOSEL</name>
|
||
|
|
<description>Microcontroller clock output
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PLLDIV</name>
|
||
|
|
<description>PLL output division</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PLLMUL</name>
|
||
|
|
<description>PLL multiplication factor</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PLLSRC</name>
|
||
|
|
<description>PLL entry clock source</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>STOPWUCK</name>
|
||
|
|
<description>Wake-up from stop clock
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PPRE2</name>
|
||
|
|
<description>APB high-speed prescaler
|
||
|
|
(APB2)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PPRE1</name>
|
||
|
|
<description>APB low-speed prescaler
|
||
|
|
(APB1)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HPRE</name>
|
||
|
|
<description>AHB prescaler</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWS</name>
|
||
|
|
<description>System clock switch status</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SW</name>
|
||
|
|
<description>System clock switch</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CIER</name>
|
||
|
|
<displayName>CIER</displayName>
|
||
|
|
<description>Clock interrupt enable
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CSSLSE</name>
|
||
|
|
<description>LSE CSS interrupt flag</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIRDYIE</name>
|
||
|
|
<description>MSI ready interrupt flag</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PLLRDYIE</name>
|
||
|
|
<description>PLL ready interrupt flag</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSERDYIE</name>
|
||
|
|
<description>HSE ready interrupt flag</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSI16RDYIE</name>
|
||
|
|
<description>HSI16 ready interrupt flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSERDYIE</name>
|
||
|
|
<description>LSE ready interrupt flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSIRDYIE</name>
|
||
|
|
<description>LSI ready interrupt flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CIFR</name>
|
||
|
|
<displayName>CIFR</displayName>
|
||
|
|
<description>Clock interrupt flag register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CSSHSEF</name>
|
||
|
|
<description>Clock Security System Interrupt
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CSSLSEF</name>
|
||
|
|
<description>LSE Clock Security System Interrupt
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIRDYF</name>
|
||
|
|
<description>MSI ready interrupt flag</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PLLRDYF</name>
|
||
|
|
<description>PLL ready interrupt flag</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSERDYF</name>
|
||
|
|
<description>HSE ready interrupt flag</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSI16RDYF</name>
|
||
|
|
<description>HSI16 ready interrupt flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSERDYF</name>
|
||
|
|
<description>LSE ready interrupt flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSIRDYF</name>
|
||
|
|
<description>LSI ready interrupt flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CICR</name>
|
||
|
|
<displayName>CICR</displayName>
|
||
|
|
<description>Clock interrupt clear register</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CSSHSEC</name>
|
||
|
|
<description>Clock Security System Interrupt
|
||
|
|
clear</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CSSLSEC</name>
|
||
|
|
<description>LSE Clock Security System Interrupt
|
||
|
|
clear</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSIRDYC</name>
|
||
|
|
<description>MSI ready Interrupt clear</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PLLRDYC</name>
|
||
|
|
<description>PLL ready Interrupt clear</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSERDYC</name>
|
||
|
|
<description>HSE ready Interrupt clear</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HSI16RDYC</name>
|
||
|
|
<description>HSI16 ready Interrupt
|
||
|
|
clear</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSERDYC</name>
|
||
|
|
<description>LSE ready Interrupt clear</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSIRDYC</name>
|
||
|
|
<description>LSI ready Interrupt clear</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IOPRSTR</name>
|
||
|
|
<displayName>IOPRSTR</displayName>
|
||
|
|
<description>GPIO reset register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>IOPHRST</name>
|
||
|
|
<description>I/O port H reset</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPDRST</name>
|
||
|
|
<description>I/O port D reset</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPCRST</name>
|
||
|
|
<description>I/O port A reset</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPBRST</name>
|
||
|
|
<description>I/O port B reset</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPARST</name>
|
||
|
|
<description>I/O port A reset</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPERST</name>
|
||
|
|
<description>I/O port E reset</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>AHBRSTR</name>
|
||
|
|
<displayName>AHBRSTR</displayName>
|
||
|
|
<description>AHB peripheral reset register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CRYPRST</name>
|
||
|
|
<description>Crypto module reset</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CRCRST</name>
|
||
|
|
<description>Test integration module
|
||
|
|
reset</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MIFRST</name>
|
||
|
|
<description>Memory interface reset</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DMARST</name>
|
||
|
|
<description>DMA reset</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>APB2RSTR</name>
|
||
|
|
<displayName>APB2RSTR</displayName>
|
||
|
|
<description>APB2 peripheral reset register</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x000000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DBGRST</name>
|
||
|
|
<description>DBG reset</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART1RST</name>
|
||
|
|
<description>USART1 reset</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SPI1RST</name>
|
||
|
|
<description>SPI 1 reset</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADCRST</name>
|
||
|
|
<description>ADC interface reset</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM22RST</name>
|
||
|
|
<description>TIM22 timer reset</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM21RST</name>
|
||
|
|
<description>TIM21 timer reset</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SYSCFGRST</name>
|
||
|
|
<description>System configuration controller
|
||
|
|
reset</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>APB1RSTR</name>
|
||
|
|
<displayName>APB1RSTR</displayName>
|
||
|
|
<description>APB1 peripheral reset register</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LPTIM1RST</name>
|
||
|
|
<description>Low power timer reset</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PWRRST</name>
|
||
|
|
<description>Power interface reset</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C2RST</name>
|
||
|
|
<description>I2C2 reset</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C1RST</name>
|
||
|
|
<description>I2C1 reset</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LPUART1RST</name>
|
||
|
|
<description>LPUART1 reset</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART2RST</name>
|
||
|
|
<description>USART2 reset</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SPI2RST</name>
|
||
|
|
<description>SPI2 reset</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WWDGRST</name>
|
||
|
|
<description>Window watchdog reset</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM6RST</name>
|
||
|
|
<description>Timer 6 reset</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM2RST</name>
|
||
|
|
<description>Timer 2 reset</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM3RST</name>
|
||
|
|
<description>Timer 3 reset</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM7RST</name>
|
||
|
|
<description>Timer 7 reset</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART4RST</name>
|
||
|
|
<description>USART4 reset</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART5RST</name>
|
||
|
|
<description>USART5 reset</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CRCRST</name>
|
||
|
|
<description>CRC reset</description>
|
||
|
|
<bitOffset>27</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C3</name>
|
||
|
|
<description>I2C3 reset</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IOPENR</name>
|
||
|
|
<displayName>IOPENR</displayName>
|
||
|
|
<description>GPIO clock enable register</description>
|
||
|
|
<addressOffset>0x2C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>IOPHEN</name>
|
||
|
|
<description>I/O port H clock enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPDEN</name>
|
||
|
|
<description>I/O port D clock enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPCEN</name>
|
||
|
|
<description>IO port A clock enable bit</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPBEN</name>
|
||
|
|
<description>IO port B clock enable bit</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPAEN</name>
|
||
|
|
<description>IO port A clock enable bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPEEN</name>
|
||
|
|
<description>IO port E clock enable bit</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>AHBENR</name>
|
||
|
|
<displayName>AHBENR</displayName>
|
||
|
|
<description>AHB peripheral clock enable
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x30</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000100</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CRYPEN</name>
|
||
|
|
<description>Crypto clock enable bit</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CRCEN</name>
|
||
|
|
<description>CRC clock enable bit</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MIFEN</name>
|
||
|
|
<description>NVM interface clock enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DMAEN</name>
|
||
|
|
<description>DMA clock enable bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>APB2ENR</name>
|
||
|
|
<displayName>APB2ENR</displayName>
|
||
|
|
<description>APB2 peripheral clock enable
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x34</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DBGEN</name>
|
||
|
|
<description>DBG clock enable bit</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART1EN</name>
|
||
|
|
<description>USART1 clock enable bit</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SPI1EN</name>
|
||
|
|
<description>SPI1 clock enable bit</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADCEN</name>
|
||
|
|
<description>ADC clock enable bit</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FWEN</name>
|
||
|
|
<description>Firewall clock enable bit</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM22EN</name>
|
||
|
|
<description>TIM22 timer clock enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM21EN</name>
|
||
|
|
<description>TIM21 timer clock enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SYSCFGEN</name>
|
||
|
|
<description>System configuration controller clock
|
||
|
|
enable bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>APB1ENR</name>
|
||
|
|
<displayName>APB1ENR</displayName>
|
||
|
|
<description>APB1 peripheral clock enable
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x38</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LPTIM1EN</name>
|
||
|
|
<description>Low power timer clock enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PWREN</name>
|
||
|
|
<description>Power interface clock enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C2EN</name>
|
||
|
|
<description>I2C2 clock enable bit</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C1EN</name>
|
||
|
|
<description>I2C1 clock enable bit</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LPUART1EN</name>
|
||
|
|
<description>LPUART1 clock enable bit</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART2EN</name>
|
||
|
|
<description>UART2 clock enable bit</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SPI2EN</name>
|
||
|
|
<description>SPI2 clock enable bit</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WWDGEN</name>
|
||
|
|
<description>Window watchdog clock enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM6EN</name>
|
||
|
|
<description>Timer 6 clock enable bit</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM2EN</name>
|
||
|
|
<description>Timer2 clock enable bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM3EN</name>
|
||
|
|
<description>Timer 3 clock enbale bit</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM7EN</name>
|
||
|
|
<description>Timer 7 clock enable bit</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART4EN</name>
|
||
|
|
<description>USART4 clock enable bit</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART5EN</name>
|
||
|
|
<description>USART5 clock enable bit</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C3EN</name>
|
||
|
|
<description>I2C3 clock enable bit</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IOPSMEN</name>
|
||
|
|
<displayName>IOPSMEN</displayName>
|
||
|
|
<description>GPIO clock enable in sleep mode
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x3C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000008F</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>IOPHSMEN</name>
|
||
|
|
<description>Port H clock enable during Sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPDSMEN</name>
|
||
|
|
<description>Port D clock enable during Sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPCSMEN</name>
|
||
|
|
<description>Port C clock enable during Sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPBSMEN</name>
|
||
|
|
<description>Port B clock enable during Sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPASMEN</name>
|
||
|
|
<description>Port A clock enable during Sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IOPESMEN</name>
|
||
|
|
<description>Port E clock enable during Sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>AHBSMENR</name>
|
||
|
|
<displayName>AHBSMENR</displayName>
|
||
|
|
<description>AHB peripheral clock enable in sleep mode
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x40</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x01111301</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CRYPTSMEN</name>
|
||
|
|
<description>Crypto clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CRCSMEN</name>
|
||
|
|
<description>CRC clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SRAMSMEN</name>
|
||
|
|
<description>SRAM interface clock enable during sleep
|
||
|
|
mode bit</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MIFSMEN</name>
|
||
|
|
<description>NVM interface clock enable during sleep
|
||
|
|
mode bit</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DMASMEN</name>
|
||
|
|
<description>DMA clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>APB2SMENR</name>
|
||
|
|
<displayName>APB2SMENR</displayName>
|
||
|
|
<description>APB2 peripheral clock enable in sleep mode
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x44</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00405225</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DBGSMEN</name>
|
||
|
|
<description>DBG clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART1SMEN</name>
|
||
|
|
<description>USART1 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SPI1SMEN</name>
|
||
|
|
<description>SPI1 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADCSMEN</name>
|
||
|
|
<description>ADC clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM22SMEN</name>
|
||
|
|
<description>TIM22 timer clock enable during sleep
|
||
|
|
mode bit</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM21SMEN</name>
|
||
|
|
<description>TIM21 timer clock enable during sleep
|
||
|
|
mode bit</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SYSCFGSMEN</name>
|
||
|
|
<description>System configuration controller clock
|
||
|
|
enable during sleep mode bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>APB1SMENR</name>
|
||
|
|
<displayName>APB1SMENR</displayName>
|
||
|
|
<description>APB1 peripheral clock enable in sleep mode
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x48</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0xB8E64A11</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LPTIM1SMEN</name>
|
||
|
|
<description>Low power timer clock enable during
|
||
|
|
sleep mode bit</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PWRSMEN</name>
|
||
|
|
<description>Power interface clock enable during
|
||
|
|
sleep mode bit</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CRSSMEN</name>
|
||
|
|
<description>Clock recovery system clock enable
|
||
|
|
during sleep mode bit</description>
|
||
|
|
<bitOffset>27</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C2SMEN</name>
|
||
|
|
<description>I2C2 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C1SMEN</name>
|
||
|
|
<description>I2C1 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LPUART1SMEN</name>
|
||
|
|
<description>LPUART1 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART2SMEN</name>
|
||
|
|
<description>UART2 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SPI2SMEN</name>
|
||
|
|
<description>SPI2 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WWDGSMEN</name>
|
||
|
|
<description>Window watchdog clock enable during
|
||
|
|
sleep mode bit</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM6SMEN</name>
|
||
|
|
<description>Timer 6 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM2SMEN</name>
|
||
|
|
<description>Timer2 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM3SMEN</name>
|
||
|
|
<description>Timer 3 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIM7SMEN</name>
|
||
|
|
<description>Timer 7 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART4SMEN</name>
|
||
|
|
<description>USART4 clock enabe during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART5SMEN</name>
|
||
|
|
<description>USART5 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C3SMEN</name>
|
||
|
|
<description>I2C3 clock enable during sleep mode
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCIPR</name>
|
||
|
|
<displayName>CCIPR</displayName>
|
||
|
|
<description>Clock configuration register</description>
|
||
|
|
<addressOffset>0x4C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LPTIM1SEL1</name>
|
||
|
|
<description>Low Power Timer clock source selection
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LPTIM1SEL0</name>
|
||
|
|
<description>LPTIM1SEL0</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C1SEL1</name>
|
||
|
|
<description>I2C1 clock source selection
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C1SEL0</name>
|
||
|
|
<description>I2C1SEL0</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LPUART1SEL1</name>
|
||
|
|
<description>LPUART1 clock source selection
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LPUART1SEL0</name>
|
||
|
|
<description>LPUART1SEL0</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART2SEL1</name>
|
||
|
|
<description>USART2 clock source selection
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART2SEL0</name>
|
||
|
|
<description>USART2SEL0</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART1SEL1</name>
|
||
|
|
<description>USART1 clock source selection
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USART1SEL0</name>
|
||
|
|
<description>USART1SEL0</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C3SEL0</name>
|
||
|
|
<description>I2C3 clock source selection
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C3SEL1</name>
|
||
|
|
<description>I2C3 clock source selection
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CSR</name>
|
||
|
|
<displayName>CSR</displayName>
|
||
|
|
<description>Control and status register</description>
|
||
|
|
<addressOffset>0x50</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x0C000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LPWRSTF</name>
|
||
|
|
<description>Low-power reset flag</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WWDGRSTF</name>
|
||
|
|
<description>Window watchdog reset flag</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IWDGRSTF</name>
|
||
|
|
<description>Independent watchdog reset
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>29</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SFTRSTF</name>
|
||
|
|
<description>Software reset flag</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PORRSTF</name>
|
||
|
|
<description>POR/PDR reset flag</description>
|
||
|
|
<bitOffset>27</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PINRSTF</name>
|
||
|
|
<description>PIN reset flag</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OBLRSTF</name>
|
||
|
|
<description>OBLRSTF</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FWRSTF</name>
|
||
|
|
<description>Firewall reset flag</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTCRST</name>
|
||
|
|
<description>RTC software reset bit</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTCEN</name>
|
||
|
|
<description>RTC clock enable bit</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTCSEL</name>
|
||
|
|
<description>RTC and LCD clock source selection
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CSSLSED</name>
|
||
|
|
<description>CSS on LSE failure detection
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CSSLSEON</name>
|
||
|
|
<description>CSSLSEON</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSEDRV</name>
|
||
|
|
<description>LSEDRV</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSEBYP</name>
|
||
|
|
<description>External low-speed oscillator bypass
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSERDY</name>
|
||
|
|
<description>External low-speed oscillator ready
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSEON</name>
|
||
|
|
<description>External low-speed oscillator enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSIRDY</name>
|
||
|
|
<description>Internal low-speed oscillator ready
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSION</name>
|
||
|
|
<description>Internal low-speed oscillator
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSIIWDGLP</name>
|
||
|
|
<description>LSI clock input to IWDG in
|
||
|
|
Ultra-low-power mode (Stop and Standby) enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RMVF</name>
|
||
|
|
<description>Remove reset flag</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>SYSCFG_COMP</name>
|
||
|
|
<description>System configuration controller and COMP
|
||
|
|
register</description>
|
||
|
|
<groupName>SYSCFG</groupName>
|
||
|
|
<baseAddress>0x40010000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CFGR1</name>
|
||
|
|
<displayName>CFGR1</displayName>
|
||
|
|
<description>SYSCFG configuration register
|
||
|
|
1</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BOOT_MODE</name>
|
||
|
|
<description>Boot mode selected by the boot pins
|
||
|
|
status bits</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MEM_MODE</name>
|
||
|
|
<description>Memory mapping selection
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CFGR2</name>
|
||
|
|
<displayName>CFGR2</displayName>
|
||
|
|
<description>SYSCFG configuration register
|
||
|
|
2</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>I2C2_FMP</name>
|
||
|
|
<description>I2C2 Fm+ drive capability enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C1_FMP</name>
|
||
|
|
<description>I2C1 Fm+ drive capability enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C_PB9_FMP</name>
|
||
|
|
<description>Fm+ drive capability on PB9 enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C_PB8_FMP</name>
|
||
|
|
<description>Fm+ drive capability on PB8 enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C_PB7_FMP</name>
|
||
|
|
<description>Fm+ drive capability on PB7 enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2C_PB6_FMP</name>
|
||
|
|
<description>Fm+ drive capability on PB6 enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CAPA</name>
|
||
|
|
<description>Configuration of internal VLCD rail
|
||
|
|
connection to optional external
|
||
|
|
capacitor</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FWDISEN</name>
|
||
|
|
<description>Firewall disable bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>EXTICR1</name>
|
||
|
|
<displayName>EXTICR1</displayName>
|
||
|
|
<description>external interrupt configuration register
|
||
|
|
1</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>EXTI3</name>
|
||
|
|
<description>EXTI x configuration (x = 0 to
|
||
|
|
3)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI2</name>
|
||
|
|
<description>EXTI x configuration (x = 0 to
|
||
|
|
3)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI1</name>
|
||
|
|
<description>EXTI x configuration (x = 0 to
|
||
|
|
3)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI0</name>
|
||
|
|
<description>EXTI x configuration (x = 0 to
|
||
|
|
3)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>EXTICR2</name>
|
||
|
|
<displayName>EXTICR2</displayName>
|
||
|
|
<description>external interrupt configuration register
|
||
|
|
2</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>EXTI7</name>
|
||
|
|
<description>EXTI x configuration (x = 4 to
|
||
|
|
7)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI6</name>
|
||
|
|
<description>EXTI x configuration (x = 4 to
|
||
|
|
7)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI5</name>
|
||
|
|
<description>EXTI x configuration (x = 4 to
|
||
|
|
7)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI4</name>
|
||
|
|
<description>EXTI x configuration (x = 4 to
|
||
|
|
7)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>EXTICR3</name>
|
||
|
|
<displayName>EXTICR3</displayName>
|
||
|
|
<description>external interrupt configuration register
|
||
|
|
3</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>EXTI11</name>
|
||
|
|
<description>EXTI x configuration (x = 8 to
|
||
|
|
11)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI10</name>
|
||
|
|
<description>EXTI10</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI9</name>
|
||
|
|
<description>EXTI x configuration (x = 8 to
|
||
|
|
11)</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI8</name>
|
||
|
|
<description>EXTI x configuration (x = 8 to
|
||
|
|
11)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>EXTICR4</name>
|
||
|
|
<displayName>EXTICR4</displayName>
|
||
|
|
<description>external interrupt configuration register
|
||
|
|
4</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>EXTI15</name>
|
||
|
|
<description>EXTI x configuration (x = 12 to
|
||
|
|
15)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI14</name>
|
||
|
|
<description>EXTI14</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI13</name>
|
||
|
|
<description>EXTI13</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTI12</name>
|
||
|
|
<description>EXTI12</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CFGR3</name>
|
||
|
|
<displayName>CFGR3</displayName>
|
||
|
|
<description>SYSCFG configuration register
|
||
|
|
3</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>REF_LOCK</name>
|
||
|
|
<description>REF_CTRL lock bit</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>write-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>VREFINT_RDYF</name>
|
||
|
|
<description>VREFINT ready flag</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>VREFINT_COMP_RDYF</name>
|
||
|
|
<description>VREFINT for comparator ready
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>29</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>VREFINT_ADC_RDYF</name>
|
||
|
|
<description>VREFINT for ADC ready flag</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SENSOR_ADC_RDYF</name>
|
||
|
|
<description>Sensor for ADC ready flag</description>
|
||
|
|
<bitOffset>27</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>REF_RC48MHz_RDYF</name>
|
||
|
|
<description>VREFINT for 48 MHz RC oscillator ready
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ENREF_RC48MHz</name>
|
||
|
|
<description>VREFINT reference for 48 MHz RC
|
||
|
|
oscillator enable bit</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ENBUF_VREFINT_COMP</name>
|
||
|
|
<description>VREFINT reference for comparator 2
|
||
|
|
enable bit</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ENBUF_SENSOR_ADC</name>
|
||
|
|
<description>Sensor reference for ADC enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ENBUF_BGAP_ADC</name>
|
||
|
|
<description>VREFINT reference for ADC enable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SEL_VREF_OUT</name>
|
||
|
|
<description>BGAP_ADC connection bit</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EN_BGAP</name>
|
||
|
|
<description>Vref Enable bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>COMP1_CTRL</name>
|
||
|
|
<displayName>COMP1_CTRL</displayName>
|
||
|
|
<description>Comparator 1 control and status
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>COMP1EN</name>
|
||
|
|
<description>Comparator 1 enable bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP1INNSEL</name>
|
||
|
|
<description>Comparator 1 Input Minus connection
|
||
|
|
configuration bit</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP1WM</name>
|
||
|
|
<description>Comparator 1 window mode selection
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP1LPTIMIN1</name>
|
||
|
|
<description>Comparator 1 LPTIM input propagation
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP1POLARITY</name>
|
||
|
|
<description>Comparator 1 polarity selection
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP1VALUE</name>
|
||
|
|
<description>Comparator 1 output status
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP1LOCK</name>
|
||
|
|
<description>COMP1_CSR register lock
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>COMP2_CTRL</name>
|
||
|
|
<displayName>COMP2_CTRL</displayName>
|
||
|
|
<description>Comparator 2 control and status
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>COMP2EN</name>
|
||
|
|
<description>Comparator 2 enable bit</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP2SPEED</name>
|
||
|
|
<description>Comparator 2 power mode selection
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP2INNSEL</name>
|
||
|
|
<description>Comparator 2 Input Minus connection
|
||
|
|
configuration bit</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP2INPSEL</name>
|
||
|
|
<description>Comparator 2 Input Plus connection
|
||
|
|
configuration bit</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP2LPTIMIN2</name>
|
||
|
|
<description>Comparator 2 LPTIM input 2 propagation
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP2LPTIMIN1</name>
|
||
|
|
<description>Comparator 2 LPTIM input 1 propagation
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP2POLARITY</name>
|
||
|
|
<description>Comparator 2 polarity selection
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP2VALUE</name>
|
||
|
|
<description>Comparator 2 output status
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COMP2LOCK</name>
|
||
|
|
<description>COMP2_CSR register lock
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>SPI1</name>
|
||
|
|
<description>Serial peripheral interface</description>
|
||
|
|
<groupName>SPI</groupName>
|
||
|
|
<baseAddress>0x40013000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>SPI1</name>
|
||
|
|
<description>SPI1_global_interrupt</description>
|
||
|
|
<value>25</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR1</name>
|
||
|
|
<displayName>CR1</displayName>
|
||
|
|
<description>control register 1</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BIDIMODE</name>
|
||
|
|
<description>Bidirectional data mode
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BIDIOE</name>
|
||
|
|
<description>Output enable in bidirectional
|
||
|
|
mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CRCEN</name>
|
||
|
|
<description>Hardware CRC calculation
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CRCNEXT</name>
|
||
|
|
<description>CRC transfer next</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DFF</name>
|
||
|
|
<description>Data frame format</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXONLY</name>
|
||
|
|
<description>Receive only</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SSM</name>
|
||
|
|
<description>Software slave management</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SSI</name>
|
||
|
|
<description>Internal slave select</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LSBFIRST</name>
|
||
|
|
<description>Frame format</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SPE</name>
|
||
|
|
<description>SPI enable</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BR</name>
|
||
|
|
<description>Baud rate control</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSTR</name>
|
||
|
|
<description>Master selection</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CPOL</name>
|
||
|
|
<description>Clock polarity</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CPHA</name>
|
||
|
|
<description>Clock phase</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR2</name>
|
||
|
|
<displayName>CR2</displayName>
|
||
|
|
<description>control register 2</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RXDMAEN</name>
|
||
|
|
<description>Rx buffer DMA enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXDMAEN</name>
|
||
|
|
<description>Tx buffer DMA enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SSOE</name>
|
||
|
|
<description>SS output enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FRF</name>
|
||
|
|
<description>Frame format</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ERRIE</name>
|
||
|
|
<description>Error interrupt enable</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXNEIE</name>
|
||
|
|
<description>RX buffer not empty interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXEIE</name>
|
||
|
|
<description>Tx buffer empty interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SR</name>
|
||
|
|
<displayName>SR</displayName>
|
||
|
|
<description>status register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x0002</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RXNE</name>
|
||
|
|
<description>Receive buffer not empty</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXE</name>
|
||
|
|
<description>Transmit buffer empty</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSIDE</name>
|
||
|
|
<description>Channel side</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UDR</name>
|
||
|
|
<description>Underrun flag</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CRCERR</name>
|
||
|
|
<description>CRC error flag</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MODF</name>
|
||
|
|
<description>Mode fault</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OVR</name>
|
||
|
|
<description>Overrun flag</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BSY</name>
|
||
|
|
<description>Busy flag</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIFRFE</name>
|
||
|
|
<description>TI frame format error</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>DR</name>
|
||
|
|
<displayName>DR</displayName>
|
||
|
|
<description>data register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DR</name>
|
||
|
|
<description>Data register</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CRCPR</name>
|
||
|
|
<displayName>CRCPR</displayName>
|
||
|
|
<description>CRC polynomial register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0007</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CRCPOLY</name>
|
||
|
|
<description>CRC polynomial register</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>RXCRCR</name>
|
||
|
|
<displayName>RXCRCR</displayName>
|
||
|
|
<description>RX CRC register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RxCRC</name>
|
||
|
|
<description>Rx CRC register</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>TXCRCR</name>
|
||
|
|
<displayName>TXCRCR</displayName>
|
||
|
|
<description>TX CRC register</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TxCRC</name>
|
||
|
|
<description>Tx CRC register</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>I2SCFGR</name>
|
||
|
|
<displayName>I2SCFGR</displayName>
|
||
|
|
<description>I2S configuration register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>I2SMOD</name>
|
||
|
|
<description>I2S mode selection</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2SE</name>
|
||
|
|
<description>I2S Enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2SCFG</name>
|
||
|
|
<description>I2S configuration mode</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PCMSYNC</name>
|
||
|
|
<description>PCM frame synchronization</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2SSTD</name>
|
||
|
|
<description>I2S standard selection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CKPOL</name>
|
||
|
|
<description>Steady state clock
|
||
|
|
polarity</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DATLEN</name>
|
||
|
|
<description>Data length to be
|
||
|
|
transferred</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHLEN</name>
|
||
|
|
<description>Channel length (number of bits per audio
|
||
|
|
channel)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>I2SPR</name>
|
||
|
|
<displayName>I2SPR</displayName>
|
||
|
|
<description>I2S prescaler register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000010</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MCKOE</name>
|
||
|
|
<description>Master clock output enable</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ODD</name>
|
||
|
|
<description>Odd factor for the
|
||
|
|
prescaler</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>I2SDIV</name>
|
||
|
|
<description>I2S Linear prescaler</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="SPI1">
|
||
|
|
<name>SPI2</name>
|
||
|
|
<baseAddress>0x40003800</baseAddress>
|
||
|
|
<interrupt>
|
||
|
|
<name>SPI2</name>
|
||
|
|
<description>SPI2 global interrupt</description>
|
||
|
|
<value>26</value>
|
||
|
|
</interrupt>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>I2C1</name>
|
||
|
|
<description>Inter-integrated circuit</description>
|
||
|
|
<groupName>I2C</groupName>
|
||
|
|
<baseAddress>0x40005400</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>I2C1</name>
|
||
|
|
<description>I2C1 global interrupt</description>
|
||
|
|
<value>23</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR1</name>
|
||
|
|
<displayName>CR1</displayName>
|
||
|
|
<description>Control register 1</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PE</name>
|
||
|
|
<description>Peripheral enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXIE</name>
|
||
|
|
<description>TX Interrupt enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXIE</name>
|
||
|
|
<description>RX Interrupt enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADDRIE</name>
|
||
|
|
<description>Address match interrupt enable (slave
|
||
|
|
only)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NACKIE</name>
|
||
|
|
<description>Not acknowledge received interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>STOPIE</name>
|
||
|
|
<description>STOP detection Interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIE</name>
|
||
|
|
<description>Transfer Complete interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ERRIE</name>
|
||
|
|
<description>Error interrupts enable</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DNF</name>
|
||
|
|
<description>Digital noise filter</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ANFOFF</name>
|
||
|
|
<description>Analog noise filter OFF</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXDMAEN</name>
|
||
|
|
<description>DMA transmission requests
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXDMAEN</name>
|
||
|
|
<description>DMA reception requests
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SBC</name>
|
||
|
|
<description>Slave byte control</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NOSTRETCH</name>
|
||
|
|
<description>Clock stretching disable</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WUPEN</name>
|
||
|
|
<description>Wakeup from STOP enable</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>GCEN</name>
|
||
|
|
<description>General call enable</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SMBHEN</name>
|
||
|
|
<description>SMBus Host address enable</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SMBDEN</name>
|
||
|
|
<description>SMBus Device Default address
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ALERTEN</name>
|
||
|
|
<description>SMBUS alert enable</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PECEN</name>
|
||
|
|
<description>PEC enable</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR2</name>
|
||
|
|
<displayName>CR2</displayName>
|
||
|
|
<description>Control register 2</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PECBYTE</name>
|
||
|
|
<description>Packet error checking byte</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AUTOEND</name>
|
||
|
|
<description>Automatic end mode (master
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RELOAD</name>
|
||
|
|
<description>NBYTES reload mode</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NBYTES</name>
|
||
|
|
<description>Number of bytes</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NACK</name>
|
||
|
|
<description>NACK generation (slave
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>STOP</name>
|
||
|
|
<description>Stop generation (master
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>START</name>
|
||
|
|
<description>Start generation</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HEAD10R</name>
|
||
|
|
<description>10-bit address header only read
|
||
|
|
direction (master receiver mode)</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADD10</name>
|
||
|
|
<description>10-bit addressing mode (master
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RD_WRN</name>
|
||
|
|
<description>Transfer direction (master
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SADD</name>
|
||
|
|
<description>Slave address bit (master
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>10</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OAR1</name>
|
||
|
|
<displayName>OAR1</displayName>
|
||
|
|
<description>Own address register 1</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OA1</name>
|
||
|
|
<description>Interface address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>10</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OA1MODE</name>
|
||
|
|
<description>Own Address 1 10-bit mode</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OA1EN</name>
|
||
|
|
<description>Own Address 1 enable</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OAR2</name>
|
||
|
|
<displayName>OAR2</displayName>
|
||
|
|
<description>Own address register 2</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OA2</name>
|
||
|
|
<description>Interface address</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>7</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OA2MSK</name>
|
||
|
|
<description>Own Address 2 masks</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OA2EN</name>
|
||
|
|
<description>Own Address 2 enable</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>TIMINGR</name>
|
||
|
|
<displayName>TIMINGR</displayName>
|
||
|
|
<description>Timing register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>SCLL</name>
|
||
|
|
<description>SCL low period (master
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SCLH</name>
|
||
|
|
<description>SCL high period (master
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SDADEL</name>
|
||
|
|
<description>Data hold time</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SCLDEL</name>
|
||
|
|
<description>Data setup time</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRESC</name>
|
||
|
|
<description>Timing prescaler</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>TIMEOUTR</name>
|
||
|
|
<displayName>TIMEOUTR</displayName>
|
||
|
|
<description>Status register 1</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TIMEOUTA</name>
|
||
|
|
<description>Bus timeout A</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>12</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIDLE</name>
|
||
|
|
<description>Idle clock timeout
|
||
|
|
detection</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIMOUTEN</name>
|
||
|
|
<description>Clock timeout enable</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIMEOUTB</name>
|
||
|
|
<description>Bus timeout B</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>12</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEXTEN</name>
|
||
|
|
<description>Extended clock timeout
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ISR</name>
|
||
|
|
<displayName>ISR</displayName>
|
||
|
|
<description>Interrupt and Status register</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x00000001</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ADDCODE</name>
|
||
|
|
<description>Address match code (Slave
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>7</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIR</name>
|
||
|
|
<description>Transfer direction (Slave
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BUSY</name>
|
||
|
|
<description>Bus busy</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ALERT</name>
|
||
|
|
<description>SMBus alert</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIMEOUT</name>
|
||
|
|
<description>Timeout or t_low detection
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PECERR</name>
|
||
|
|
<description>PEC Error in reception</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OVR</name>
|
||
|
|
<description>Overrun/Underrun (slave
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARLO</name>
|
||
|
|
<description>Arbitration lost</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BERR</name>
|
||
|
|
<description>Bus error</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCR</name>
|
||
|
|
<description>Transfer Complete Reload</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TC</name>
|
||
|
|
<description>Transfer Complete (master
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>STOPF</name>
|
||
|
|
<description>Stop detection flag</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NACKF</name>
|
||
|
|
<description>Not acknowledge received
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADDR</name>
|
||
|
|
<description>Address matched (slave
|
||
|
|
mode)</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXNE</name>
|
||
|
|
<description>Receive data register not empty
|
||
|
|
(receivers)</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXIS</name>
|
||
|
|
<description>Transmit interrupt status
|
||
|
|
(transmitters)</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXE</name>
|
||
|
|
<description>Transmit data register empty
|
||
|
|
(transmitters)</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ICR</name>
|
||
|
|
<displayName>ICR</displayName>
|
||
|
|
<description>Interrupt clear register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ALERTCF</name>
|
||
|
|
<description>Alert flag clear</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIMOUTCF</name>
|
||
|
|
<description>Timeout detection flag
|
||
|
|
clear</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PECCF</name>
|
||
|
|
<description>PEC Error flag clear</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OVRCF</name>
|
||
|
|
<description>Overrun/Underrun flag
|
||
|
|
clear</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARLOCF</name>
|
||
|
|
<description>Arbitration lost flag
|
||
|
|
clear</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BERRCF</name>
|
||
|
|
<description>Bus error flag clear</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>STOPCF</name>
|
||
|
|
<description>Stop detection flag clear</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NACKCF</name>
|
||
|
|
<description>Not Acknowledge flag clear</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADDRCF</name>
|
||
|
|
<description>Address Matched flag clear</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PECR</name>
|
||
|
|
<displayName>PECR</displayName>
|
||
|
|
<description>PEC register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PEC</name>
|
||
|
|
<description>Packet error checking
|
||
|
|
register</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>RXDR</name>
|
||
|
|
<displayName>RXDR</displayName>
|
||
|
|
<description>Receive data register</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RXDATA</name>
|
||
|
|
<description>8-bit receive data</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>TXDR</name>
|
||
|
|
<displayName>TXDR</displayName>
|
||
|
|
<description>Transmit data register</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TXDATA</name>
|
||
|
|
<description>8-bit transmit data</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="I2C1">
|
||
|
|
<name>I2C2</name>
|
||
|
|
<baseAddress>0x40005800</baseAddress>
|
||
|
|
<interrupt>
|
||
|
|
<name>I2C2</name>
|
||
|
|
<description>I2C2 global interrupt</description>
|
||
|
|
<value>24</value>
|
||
|
|
</interrupt>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="I2C1">
|
||
|
|
<name>I2C3</name>
|
||
|
|
<baseAddress>0x40007800</baseAddress>
|
||
|
|
<interrupt>
|
||
|
|
<name>I2C3</name>
|
||
|
|
<description>I2C3 global interrupt</description>
|
||
|
|
<value>21</value>
|
||
|
|
</interrupt>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>PWR</name>
|
||
|
|
<description>Power control</description>
|
||
|
|
<groupName>PWR</groupName>
|
||
|
|
<baseAddress>0x40007000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR</name>
|
||
|
|
<displayName>CR</displayName>
|
||
|
|
<description>power control register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00001000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LPDS</name>
|
||
|
|
<description>Low-power deep sleep</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PDDS</name>
|
||
|
|
<description>Power down deepsleep</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CWUF</name>
|
||
|
|
<description>Clear wakeup flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CSBF</name>
|
||
|
|
<description>Clear standby flag</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PVDE</name>
|
||
|
|
<description>Power voltage detector
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PLS</name>
|
||
|
|
<description>PVD level selection</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBP</name>
|
||
|
|
<description>Disable backup domain write
|
||
|
|
protection</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ULP</name>
|
||
|
|
<description>Ultra-low-power mode</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FWU</name>
|
||
|
|
<description>Fast wakeup</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>VOS</name>
|
||
|
|
<description>Voltage scaling range
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DS_EE_KOFF</name>
|
||
|
|
<description>Deep sleep mode with Flash memory kept
|
||
|
|
off</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LPRUN</name>
|
||
|
|
<description>Low power run mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CSR</name>
|
||
|
|
<displayName>CSR</displayName>
|
||
|
|
<description>power control/status register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BRE</name>
|
||
|
|
<description>Backup regulator enable</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EWUP</name>
|
||
|
|
<description>Enable WKUP pin</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BRR</name>
|
||
|
|
<description>Backup regulator ready</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PVDO</name>
|
||
|
|
<description>PVD output</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SBF</name>
|
||
|
|
<description>Standby flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WUF</name>
|
||
|
|
<description>Wakeup flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>VOSF</name>
|
||
|
|
<description>Voltage Scaling select
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>REGLPF</name>
|
||
|
|
<description>Regulator LP flag</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>Flash</name>
|
||
|
|
<description>Flash</description>
|
||
|
|
<groupName>Flash</groupName>
|
||
|
|
<baseAddress>0x40022000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>FLASH</name>
|
||
|
|
<description>Flash global interrupt</description>
|
||
|
|
<value>3</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>ACR</name>
|
||
|
|
<displayName>ACR</displayName>
|
||
|
|
<description>Access control register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>LATENCY</name>
|
||
|
|
<description>Latency</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRFTEN</name>
|
||
|
|
<description>Prefetch enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SLEEP_PD</name>
|
||
|
|
<description>Flash mode during Sleep</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RUN_PD</name>
|
||
|
|
<description>Flash mode during Run</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DESAB_BUF</name>
|
||
|
|
<description>Disable Buffer</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRE_READ</name>
|
||
|
|
<description>Pre-read data address</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PECR</name>
|
||
|
|
<displayName>PECR</displayName>
|
||
|
|
<description>Program/erase control register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000007</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PELOCK</name>
|
||
|
|
<description>FLASH_PECR and data EEPROM
|
||
|
|
lock</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRGLOCK</name>
|
||
|
|
<description>Program memory lock</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OPTLOCK</name>
|
||
|
|
<description>Option bytes block lock</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PROG</name>
|
||
|
|
<description>Program memory selection</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DATA</name>
|
||
|
|
<description>Data EEPROM selection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FTDW</name>
|
||
|
|
<description>Fixed time data write for Byte, Half
|
||
|
|
Word and Word programming</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ERASE</name>
|
||
|
|
<description>Page or Double Word erase
|
||
|
|
mode</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FPRG</name>
|
||
|
|
<description>Half Page/Double Word programming
|
||
|
|
mode</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PARALLELBANK</name>
|
||
|
|
<description>Parallel bank mode</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOPIE</name>
|
||
|
|
<description>End of programming interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ERRIE</name>
|
||
|
|
<description>Error interrupt enable</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OBL_LAUNCH</name>
|
||
|
|
<description>Launch the option byte
|
||
|
|
loading</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PDKEYR</name>
|
||
|
|
<displayName>PDKEYR</displayName>
|
||
|
|
<description>Power down key register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PDKEYR</name>
|
||
|
|
<description>RUN_PD in FLASH_ACR key</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PEKEYR</name>
|
||
|
|
<displayName>PEKEYR</displayName>
|
||
|
|
<description>Program/erase key register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PEKEYR</name>
|
||
|
|
<description>FLASH_PEC and data EEPROM
|
||
|
|
key</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PRGKEYR</name>
|
||
|
|
<displayName>PRGKEYR</displayName>
|
||
|
|
<description>Program memory key register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRGKEYR</name>
|
||
|
|
<description>Program memory key</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OPTKEYR</name>
|
||
|
|
<displayName>OPTKEYR</displayName>
|
||
|
|
<description>Option byte key register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OPTKEYR</name>
|
||
|
|
<description>Option byte key</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SR</name>
|
||
|
|
<displayName>SR</displayName>
|
||
|
|
<description>Status register</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<resetValue>0x00000004</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BSY</name>
|
||
|
|
<description>Write/erase operations in
|
||
|
|
progress</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOP</name>
|
||
|
|
<description>End of operation</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ENDHV</name>
|
||
|
|
<description>End of high voltage</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>READY</name>
|
||
|
|
<description>Flash memory module ready after low
|
||
|
|
power mode</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-only</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WRPERR</name>
|
||
|
|
<description>Write protected error</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PGAERR</name>
|
||
|
|
<description>Programming alignment
|
||
|
|
error</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SIZERR</name>
|
||
|
|
<description>Size error</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OPTVERR</name>
|
||
|
|
<description>Option validity error</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RDERR</name>
|
||
|
|
<description>RDERR</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NOTZEROERR</name>
|
||
|
|
<description>NOTZEROERR</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FWWERR</name>
|
||
|
|
<description>FWWERR</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
<access>read-write</access>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OBR</name>
|
||
|
|
<displayName>OBR</displayName>
|
||
|
|
<description>Option byte register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00F80000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RDPRT</name>
|
||
|
|
<description>Read protection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BOR_LEV</name>
|
||
|
|
<description>BOR_LEV</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SPRMOD</name>
|
||
|
|
<description>Selection of protection mode of WPR
|
||
|
|
bits</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>WRPR</name>
|
||
|
|
<displayName>WRPR</displayName>
|
||
|
|
<description>Write protection register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>WRP</name>
|
||
|
|
<description>Write protection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>EXTI</name>
|
||
|
|
<description>External interrupt/event
|
||
|
|
controller</description>
|
||
|
|
<groupName>EXTI</groupName>
|
||
|
|
<baseAddress>0x40010400</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>PVD</name>
|
||
|
|
<description>PVD through EXTI line detection</description>
|
||
|
|
<value>1</value>
|
||
|
|
</interrupt>
|
||
|
|
<interrupt>
|
||
|
|
<name>EXTI0_1</name>
|
||
|
|
<description>EXTI Line[1:0] interrupts</description>
|
||
|
|
<value>5</value>
|
||
|
|
</interrupt>
|
||
|
|
<interrupt>
|
||
|
|
<name>EXTI2_3</name>
|
||
|
|
<description>EXTI Line[3:2] interrupts</description>
|
||
|
|
<value>6</value>
|
||
|
|
</interrupt>
|
||
|
|
<interrupt>
|
||
|
|
<name>EXTI4_15</name>
|
||
|
|
<description>EXTI Line15 and EXTI4 interrupts</description>
|
||
|
|
<value>7</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>IMR</name>
|
||
|
|
<displayName>IMR</displayName>
|
||
|
|
<description>Interrupt mask register
|
||
|
|
(EXTI_IMR)</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0xFF840000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>IM0</name>
|
||
|
|
<description>Interrupt Mask on line 0</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM1</name>
|
||
|
|
<description>Interrupt Mask on line 1</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM2</name>
|
||
|
|
<description>Interrupt Mask on line 2</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM3</name>
|
||
|
|
<description>Interrupt Mask on line 3</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM4</name>
|
||
|
|
<description>Interrupt Mask on line 4</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM5</name>
|
||
|
|
<description>Interrupt Mask on line 5</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM6</name>
|
||
|
|
<description>Interrupt Mask on line 6</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM7</name>
|
||
|
|
<description>Interrupt Mask on line 7</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM8</name>
|
||
|
|
<description>Interrupt Mask on line 8</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM9</name>
|
||
|
|
<description>Interrupt Mask on line 9</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM10</name>
|
||
|
|
<description>Interrupt Mask on line 10</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM11</name>
|
||
|
|
<description>Interrupt Mask on line 11</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM12</name>
|
||
|
|
<description>Interrupt Mask on line 12</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM13</name>
|
||
|
|
<description>Interrupt Mask on line 13</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM14</name>
|
||
|
|
<description>Interrupt Mask on line 14</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM15</name>
|
||
|
|
<description>Interrupt Mask on line 15</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM16</name>
|
||
|
|
<description>Interrupt Mask on line 16</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM17</name>
|
||
|
|
<description>Interrupt Mask on line 17</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM18</name>
|
||
|
|
<description>Interrupt Mask on line 18</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM19</name>
|
||
|
|
<description>Interrupt Mask on line 19</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM20</name>
|
||
|
|
<description>Interrupt Mask on line 20</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM21</name>
|
||
|
|
<description>Interrupt Mask on line 21</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM22</name>
|
||
|
|
<description>Interrupt Mask on line 22</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM23</name>
|
||
|
|
<description>Interrupt Mask on line 23</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM24</name>
|
||
|
|
<description>Interrupt Mask on line 24</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM25</name>
|
||
|
|
<description>Interrupt Mask on line 25</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM26</name>
|
||
|
|
<description>Interrupt Mask on line 27</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM28</name>
|
||
|
|
<description>Interrupt Mask on line 27</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IM29</name>
|
||
|
|
<description>Interrupt Mask on line 27</description>
|
||
|
|
<bitOffset>29</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>EMR</name>
|
||
|
|
<displayName>EMR</displayName>
|
||
|
|
<description>Event mask register (EXTI_EMR)</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>EM0</name>
|
||
|
|
<description>Event Mask on line 0</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM1</name>
|
||
|
|
<description>Event Mask on line 1</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM2</name>
|
||
|
|
<description>Event Mask on line 2</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM3</name>
|
||
|
|
<description>Event Mask on line 3</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM4</name>
|
||
|
|
<description>Event Mask on line 4</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM5</name>
|
||
|
|
<description>Event Mask on line 5</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM6</name>
|
||
|
|
<description>Event Mask on line 6</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM7</name>
|
||
|
|
<description>Event Mask on line 7</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM8</name>
|
||
|
|
<description>Event Mask on line 8</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM9</name>
|
||
|
|
<description>Event Mask on line 9</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM10</name>
|
||
|
|
<description>Event Mask on line 10</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM11</name>
|
||
|
|
<description>Event Mask on line 11</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM12</name>
|
||
|
|
<description>Event Mask on line 12</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM13</name>
|
||
|
|
<description>Event Mask on line 13</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM14</name>
|
||
|
|
<description>Event Mask on line 14</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM15</name>
|
||
|
|
<description>Event Mask on line 15</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM16</name>
|
||
|
|
<description>Event Mask on line 16</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM17</name>
|
||
|
|
<description>Event Mask on line 17</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM18</name>
|
||
|
|
<description>Event Mask on line 18</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM19</name>
|
||
|
|
<description>Event Mask on line 19</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM20</name>
|
||
|
|
<description>Event Mask on line 20</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM21</name>
|
||
|
|
<description>Event Mask on line 21</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM22</name>
|
||
|
|
<description>Event Mask on line 22</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM23</name>
|
||
|
|
<description>Event Mask on line 23</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM24</name>
|
||
|
|
<description>Event Mask on line 24</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM25</name>
|
||
|
|
<description>Event Mask on line 25</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM26</name>
|
||
|
|
<description>Event Mask on line 26</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM28</name>
|
||
|
|
<description>Event Mask on line 28</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EM29</name>
|
||
|
|
<description>Event Mask on line 29</description>
|
||
|
|
<bitOffset>29</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>RTSR</name>
|
||
|
|
<displayName>RTSR</displayName>
|
||
|
|
<description>Rising Trigger selection register
|
||
|
|
(EXTI_RTSR)</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RT0</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 0</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT1</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 1</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT2</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 2</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT3</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 3</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT4</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 4</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT5</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 5</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT6</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 6</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT7</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 7</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT8</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 8</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT9</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 9</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT10</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 10</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT11</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 11</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT12</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 12</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT13</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 13</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT14</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 14</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT15</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 15</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT16</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 16</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT17</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 17</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT19</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 19</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT20</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 20</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT21</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 21</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RT22</name>
|
||
|
|
<description>Rising trigger event configuration of
|
||
|
|
line 22</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>FTSR</name>
|
||
|
|
<displayName>FTSR</displayName>
|
||
|
|
<description>Falling Trigger selection register
|
||
|
|
(EXTI_FTSR)</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>FT0</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 0</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT1</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 1</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT2</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 2</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT3</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 3</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT4</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 4</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT5</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 5</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT6</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 6</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT7</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 7</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT8</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 8</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT9</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 9</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT10</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 10</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT11</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 11</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT12</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 12</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT13</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 13</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT14</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 14</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT15</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 15</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT16</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 16</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT17</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 17</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT19</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 19</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT20</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 20</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT21</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 21</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FT22</name>
|
||
|
|
<description>Falling trigger event configuration of
|
||
|
|
line 22</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SWIER</name>
|
||
|
|
<displayName>SWIER</displayName>
|
||
|
|
<description>Software interrupt event register
|
||
|
|
(EXTI_SWIER)</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>SWI0</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
0</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI1</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
1</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI2</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
2</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI3</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
3</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI4</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
4</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI5</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
5</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI6</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
6</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI7</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
7</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI8</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
8</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI9</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
9</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI10</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
10</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI11</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
11</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI12</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
12</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI13</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
13</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI14</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
14</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI15</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
15</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI16</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
16</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI17</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
17</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI19</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
19</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI20</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
20</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI21</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
21</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWI22</name>
|
||
|
|
<description>Software Interrupt on line
|
||
|
|
22</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PR</name>
|
||
|
|
<displayName>PR</displayName>
|
||
|
|
<description>Pending register (EXTI_PR)</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PIF0</name>
|
||
|
|
<description>Pending bit 0</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF1</name>
|
||
|
|
<description>Pending bit 1</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF2</name>
|
||
|
|
<description>Pending bit 2</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF3</name>
|
||
|
|
<description>Pending bit 3</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF4</name>
|
||
|
|
<description>Pending bit 4</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF5</name>
|
||
|
|
<description>Pending bit 5</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF6</name>
|
||
|
|
<description>Pending bit 6</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF7</name>
|
||
|
|
<description>Pending bit 7</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF8</name>
|
||
|
|
<description>Pending bit 8</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF9</name>
|
||
|
|
<description>Pending bit 9</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF10</name>
|
||
|
|
<description>Pending bit 10</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF11</name>
|
||
|
|
<description>Pending bit 11</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF12</name>
|
||
|
|
<description>Pending bit 12</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF13</name>
|
||
|
|
<description>Pending bit 13</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF14</name>
|
||
|
|
<description>Pending bit 14</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF15</name>
|
||
|
|
<description>Pending bit 15</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF16</name>
|
||
|
|
<description>Pending bit 16</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF17</name>
|
||
|
|
<description>Pending bit 17</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF19</name>
|
||
|
|
<description>Pending bit 19</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF20</name>
|
||
|
|
<description>Pending bit 20</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF21</name>
|
||
|
|
<description>Pending bit 21</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PIF22</name>
|
||
|
|
<description>Pending bit 22</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>ADC</name>
|
||
|
|
<description>Analog-to-digital converter</description>
|
||
|
|
<groupName>ADC</groupName>
|
||
|
|
<baseAddress>0x40012400</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>ADC_COMP</name>
|
||
|
|
<description>ADC and comparator 1 and 2</description>
|
||
|
|
<value>12</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>ISR</name>
|
||
|
|
<displayName>ISR</displayName>
|
||
|
|
<description>interrupt and status register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ADRDY</name>
|
||
|
|
<description>ADC ready</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOSMP</name>
|
||
|
|
<description>End of sampling flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOC</name>
|
||
|
|
<description>End of conversion flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOS</name>
|
||
|
|
<description>End of sequence flag</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OVR</name>
|
||
|
|
<description>ADC overrun</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AWD</name>
|
||
|
|
<description>Analog watchdog flag</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOCAL</name>
|
||
|
|
<description>End Of Calibration flag</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IER</name>
|
||
|
|
<displayName>IER</displayName>
|
||
|
|
<description>interrupt enable register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ADRDYIE</name>
|
||
|
|
<description>ADC ready interrupt enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOSMPIE</name>
|
||
|
|
<description>End of sampling flag interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOCIE</name>
|
||
|
|
<description>End of conversion interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOSIE</name>
|
||
|
|
<description>End of conversion sequence interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OVRIE</name>
|
||
|
|
<description>Overrun interrupt enable</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AWDIE</name>
|
||
|
|
<description>Analog watchdog interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EOCALIE</name>
|
||
|
|
<description>End of calibration interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR</name>
|
||
|
|
<displayName>CR</displayName>
|
||
|
|
<description>control register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ADEN</name>
|
||
|
|
<description>ADC enable command</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADDIS</name>
|
||
|
|
<description>ADC disable command</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADSTART</name>
|
||
|
|
<description>ADC start conversion
|
||
|
|
command</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADSTP</name>
|
||
|
|
<description>ADC stop conversion
|
||
|
|
command</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADVREGEN</name>
|
||
|
|
<description>ADC Voltage Regulator
|
||
|
|
Enable</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADCAL</name>
|
||
|
|
<description>ADC calibration</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CFGR1</name>
|
||
|
|
<displayName>CFGR1</displayName>
|
||
|
|
<description>configuration register 1</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>AWDCH</name>
|
||
|
|
<description>Analog watchdog channel
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>5</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AWDEN</name>
|
||
|
|
<description>Analog watchdog enable</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AWDSGL</name>
|
||
|
|
<description>Enable the watchdog on a single channel
|
||
|
|
or on all channels</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DISCEN</name>
|
||
|
|
<description>Discontinuous mode</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AUTOFF</name>
|
||
|
|
<description>Auto-off mode</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AUTDLY</name>
|
||
|
|
<description>Auto-delayed conversion
|
||
|
|
mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CONT</name>
|
||
|
|
<description>Single / continuous conversion
|
||
|
|
mode</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OVRMOD</name>
|
||
|
|
<description>Overrun management mode</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTEN</name>
|
||
|
|
<description>External trigger enable and polarity
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EXTSEL</name>
|
||
|
|
<description>External trigger selection</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ALIGN</name>
|
||
|
|
<description>Data alignment</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RES</name>
|
||
|
|
<description>Data resolution</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SCANDIR</name>
|
||
|
|
<description>Scan sequence direction</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DMACFG</name>
|
||
|
|
<description>Direct memery access
|
||
|
|
configuration</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DMAEN</name>
|
||
|
|
<description>Direct memory access
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CFGR2</name>
|
||
|
|
<displayName>CFGR2</displayName>
|
||
|
|
<description>configuration register 2</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OVSE</name>
|
||
|
|
<description>Oversampler Enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OVSR</name>
|
||
|
|
<description>Oversampling ratio</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OVSS</name>
|
||
|
|
<description>Oversampling shift</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TOVS</name>
|
||
|
|
<description>Triggered Oversampling</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CKMODE</name>
|
||
|
|
<description>ADC clock mode</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SMPR</name>
|
||
|
|
<displayName>SMPR</displayName>
|
||
|
|
<description>sampling time register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>SMPR</name>
|
||
|
|
<description>Sampling time selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>TR</name>
|
||
|
|
<displayName>TR</displayName>
|
||
|
|
<description>watchdog threshold register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0FFF0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>HT</name>
|
||
|
|
<description>Analog watchdog higher
|
||
|
|
threshold</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>12</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LT</name>
|
||
|
|
<description>Analog watchdog lower
|
||
|
|
threshold</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>12</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CHSELR</name>
|
||
|
|
<displayName>CHSELR</displayName>
|
||
|
|
<description>channel selection register</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL18</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL17</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL16</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL15</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL14</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL13</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL12</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL11</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL10</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL9</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL8</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL7</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL6</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL5</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL4</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL3</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL2</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL1</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CHSEL0</name>
|
||
|
|
<description>Channel-x selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>DR</name>
|
||
|
|
<displayName>DR</displayName>
|
||
|
|
<description>data register</description>
|
||
|
|
<addressOffset>0x40</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DATA</name>
|
||
|
|
<description>Converted data</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CALFACT</name>
|
||
|
|
<displayName>CALFACT</displayName>
|
||
|
|
<description>ADC Calibration factor</description>
|
||
|
|
<addressOffset>0xB4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CALFACT</name>
|
||
|
|
<description>Calibration factor</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>7</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR</name>
|
||
|
|
<displayName>CCR</displayName>
|
||
|
|
<description>ADC common configuration
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x308</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRESC</name>
|
||
|
|
<description>ADC prescaler</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>VREFEN</name>
|
||
|
|
<description>VREFINT enable</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TSEN</name>
|
||
|
|
<description>Temperature sensor enable</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>VLCDEN</name>
|
||
|
|
<description>VLCD enable</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>LFMEN</name>
|
||
|
|
<description>Low Frequency Mode enable</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>DBG</name>
|
||
|
|
<description>Debug support</description>
|
||
|
|
<groupName>DBGMCU</groupName>
|
||
|
|
<baseAddress>0x40015800</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>IDCODE</name>
|
||
|
|
<displayName>IDCODE</displayName>
|
||
|
|
<description>MCU Device ID Code Register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x0</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DEV_ID</name>
|
||
|
|
<description>Device Identifier</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>12</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>REV_ID</name>
|
||
|
|
<description>Revision Identifier</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR</name>
|
||
|
|
<displayName>CR</displayName>
|
||
|
|
<description>Debug MCU Configuration
|
||
|
|
Register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DBG_STOP</name>
|
||
|
|
<description>Debug Stop Mode</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBG_STANDBY</name>
|
||
|
|
<description>Debug Standby Mode</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBG_SLEEP</name>
|
||
|
|
<description>Debug Sleep Mode</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>APB1_FZ</name>
|
||
|
|
<displayName>APB1_FZ</displayName>
|
||
|
|
<description>APB Low Freeze Register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DBG_TIMER2_STOP</name>
|
||
|
|
<description>Debug Timer 2 stopped when Core is
|
||
|
|
halted</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBG_TIMER6_STOP</name>
|
||
|
|
<description>Debug Timer 6 stopped when Core is
|
||
|
|
halted</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBG_RTC_STOP</name>
|
||
|
|
<description>Debug RTC stopped when Core is
|
||
|
|
halted</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBG_WWDG_STOP</name>
|
||
|
|
<description>Debug Window Wachdog stopped when Core
|
||
|
|
is halted</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBG_IWDG_STOP</name>
|
||
|
|
<description>Debug Independent Wachdog stopped when
|
||
|
|
Core is halted</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBG_I2C1_STOP</name>
|
||
|
|
<description>I2C1 SMBUS timeout mode stopped when
|
||
|
|
core is halted</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBG_I2C2_STOP</name>
|
||
|
|
<description>I2C2 SMBUS timeout mode stopped when
|
||
|
|
core is halted</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBG_LPTIMER_STOP</name>
|
||
|
|
<description>LPTIM1 counter stopped when core is
|
||
|
|
halted</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>APB2_FZ</name>
|
||
|
|
<displayName>APB2_FZ</displayName>
|
||
|
|
<description>APB High Freeze Register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DBG_TIMER21_STOP</name>
|
||
|
|
<description>Debug Timer 21 stopped when Core is
|
||
|
|
halted</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBG_TIMER22_STO</name>
|
||
|
|
<description>Debug Timer 22 stopped when Core is
|
||
|
|
halted</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>TIM2</name>
|
||
|
|
<description>General-purpose-timers</description>
|
||
|
|
<groupName>TIM</groupName>
|
||
|
|
<baseAddress>0x40000000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>TIM2</name>
|
||
|
|
<description>TIM2 global interrupt</description>
|
||
|
|
<value>15</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR1</name>
|
||
|
|
<displayName>CR1</displayName>
|
||
|
|
<description>control register 1</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CKD</name>
|
||
|
|
<description>Clock division</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARPE</name>
|
||
|
|
<description>Auto-reload preload enable</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMS</name>
|
||
|
|
<description>Center-aligned mode
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIR</name>
|
||
|
|
<description>Direction</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OPM</name>
|
||
|
|
<description>One-pulse mode</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>URS</name>
|
||
|
|
<description>Update request source</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UDIS</name>
|
||
|
|
<description>Update disable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CEN</name>
|
||
|
|
<description>Counter enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR2</name>
|
||
|
|
<displayName>CR2</displayName>
|
||
|
|
<description>control register 2</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TI1S</name>
|
||
|
|
<description>TI1 selection</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MMS</name>
|
||
|
|
<description>Master mode selection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CCDS</name>
|
||
|
|
<description>Capture/compare DMA
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SMCR</name>
|
||
|
|
<displayName>SMCR</displayName>
|
||
|
|
<description>slave mode control register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ETP</name>
|
||
|
|
<description>External trigger polarity</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ECE</name>
|
||
|
|
<description>External clock enable</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ETPS</name>
|
||
|
|
<description>External trigger prescaler</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ETF</name>
|
||
|
|
<description>External trigger filter</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSM</name>
|
||
|
|
<description>Master/Slave mode</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TS</name>
|
||
|
|
<description>Trigger selection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SMS</name>
|
||
|
|
<description>Slave mode selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>DIER</name>
|
||
|
|
<displayName>DIER</displayName>
|
||
|
|
<description>DMA/Interrupt enable register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TDE</name>
|
||
|
|
<description>Trigger DMA request enable</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC4DE</name>
|
||
|
|
<description>Capture/Compare 4 DMA request
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC3DE</name>
|
||
|
|
<description>Capture/Compare 3 DMA request
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2DE</name>
|
||
|
|
<description>Capture/Compare 2 DMA request
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1DE</name>
|
||
|
|
<description>Capture/Compare 1 DMA request
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UDE</name>
|
||
|
|
<description>Update DMA request enable</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIE</name>
|
||
|
|
<description>Trigger interrupt enable</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC4IE</name>
|
||
|
|
<description>Capture/Compare 4 interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC3IE</name>
|
||
|
|
<description>Capture/Compare 3 interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2IE</name>
|
||
|
|
<description>Capture/Compare 2 interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1IE</name>
|
||
|
|
<description>Capture/Compare 1 interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UIE</name>
|
||
|
|
<description>Update interrupt enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SR</name>
|
||
|
|
<displayName>SR</displayName>
|
||
|
|
<description>status register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CC4OF</name>
|
||
|
|
<description>Capture/Compare 4 overcapture
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC3OF</name>
|
||
|
|
<description>Capture/Compare 3 overcapture
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2OF</name>
|
||
|
|
<description>Capture/compare 2 overcapture
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1OF</name>
|
||
|
|
<description>Capture/Compare 1 overcapture
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIF</name>
|
||
|
|
<description>Trigger interrupt flag</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC4IF</name>
|
||
|
|
<description>Capture/Compare 4 interrupt
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC3IF</name>
|
||
|
|
<description>Capture/Compare 3 interrupt
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2IF</name>
|
||
|
|
<description>Capture/Compare 2 interrupt
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1IF</name>
|
||
|
|
<description>Capture/compare 1 interrupt
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UIF</name>
|
||
|
|
<description>Update interrupt flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>EGR</name>
|
||
|
|
<displayName>EGR</displayName>
|
||
|
|
<description>event generation register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TG</name>
|
||
|
|
<description>Trigger generation</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC4G</name>
|
||
|
|
<description>Capture/compare 4
|
||
|
|
generation</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC3G</name>
|
||
|
|
<description>Capture/compare 3
|
||
|
|
generation</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2G</name>
|
||
|
|
<description>Capture/compare 2
|
||
|
|
generation</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1G</name>
|
||
|
|
<description>Capture/compare 1
|
||
|
|
generation</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UG</name>
|
||
|
|
<description>Update generation</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCMR1_Output</name>
|
||
|
|
<displayName>CCMR1_Output</displayName>
|
||
|
|
<description>capture/compare mode register 1 (output
|
||
|
|
mode)</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OC2CE</name>
|
||
|
|
<description>Output compare 2 clear
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC2M</name>
|
||
|
|
<description>Output compare 2 mode</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC2PE</name>
|
||
|
|
<description>Output compare 2 preload
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC2FE</name>
|
||
|
|
<description>Output compare 2 fast
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2S</name>
|
||
|
|
<description>Capture/Compare 2
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC1CE</name>
|
||
|
|
<description>Output compare 1 clear
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC1M</name>
|
||
|
|
<description>Output compare 1 mode</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC1PE</name>
|
||
|
|
<description>Output compare 1 preload
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC1FE</name>
|
||
|
|
<description>Output compare 1 fast
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1S</name>
|
||
|
|
<description>Capture/Compare 1
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCMR1_Input</name>
|
||
|
|
<displayName>CCMR1_Input</displayName>
|
||
|
|
<description>capture/compare mode register 1 (input
|
||
|
|
mode)</description>
|
||
|
|
<alternateRegister>CCMR1_Output</alternateRegister>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>IC2F</name>
|
||
|
|
<description>Input capture 2 filter</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC2PSC</name>
|
||
|
|
<description>Input capture 2 prescaler</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2S</name>
|
||
|
|
<description>Capture/compare 2
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC1F</name>
|
||
|
|
<description>Input capture 1 filter</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC1PSC</name>
|
||
|
|
<description>Input capture 1 prescaler</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1S</name>
|
||
|
|
<description>Capture/Compare 1
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCMR2_Output</name>
|
||
|
|
<displayName>CCMR2_Output</displayName>
|
||
|
|
<description>capture/compare mode register 2 (output
|
||
|
|
mode)</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OC4CE</name>
|
||
|
|
<description>Output compare 4 clear
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC4M</name>
|
||
|
|
<description>Output compare 4 mode</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC4PE</name>
|
||
|
|
<description>Output compare 4 preload
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC4FE</name>
|
||
|
|
<description>Output compare 4 fast
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC4S</name>
|
||
|
|
<description>Capture/Compare 4
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC3CE</name>
|
||
|
|
<description>Output compare 3 clear
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC3M</name>
|
||
|
|
<description>Output compare 3 mode</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC3PE</name>
|
||
|
|
<description>Output compare 3 preload
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC3FE</name>
|
||
|
|
<description>Output compare 3 fast
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC3S</name>
|
||
|
|
<description>Capture/Compare 3
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCMR2_Input</name>
|
||
|
|
<displayName>CCMR2_Input</displayName>
|
||
|
|
<description>capture/compare mode register 2 (input
|
||
|
|
mode)</description>
|
||
|
|
<alternateRegister>CCMR2_Output</alternateRegister>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>IC4F</name>
|
||
|
|
<description>Input capture 4 filter</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC4PSC</name>
|
||
|
|
<description>Input capture 4 prescaler</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC4S</name>
|
||
|
|
<description>Capture/Compare 4
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC3F</name>
|
||
|
|
<description>Input capture 3 filter</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC3PSC</name>
|
||
|
|
<description>Input capture 3 prescaler</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC3S</name>
|
||
|
|
<description>Capture/Compare 3
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCER</name>
|
||
|
|
<displayName>CCER</displayName>
|
||
|
|
<description>capture/compare enable
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CC4NP</name>
|
||
|
|
<description>Capture/Compare 4 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC4P</name>
|
||
|
|
<description>Capture/Compare 3 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC4E</name>
|
||
|
|
<description>Capture/Compare 4 output
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC3NP</name>
|
||
|
|
<description>Capture/Compare 3 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC3P</name>
|
||
|
|
<description>Capture/Compare 3 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC3E</name>
|
||
|
|
<description>Capture/Compare 3 output
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2NP</name>
|
||
|
|
<description>Capture/Compare 2 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2P</name>
|
||
|
|
<description>Capture/Compare 2 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2E</name>
|
||
|
|
<description>Capture/Compare 2 output
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1NP</name>
|
||
|
|
<description>Capture/Compare 1 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1P</name>
|
||
|
|
<description>Capture/Compare 1 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1E</name>
|
||
|
|
<description>Capture/Compare 1 output
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNT</name>
|
||
|
|
<displayName>CNT</displayName>
|
||
|
|
<description>counter</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CNT_H</name>
|
||
|
|
<description>High counter value (TIM2
|
||
|
|
only)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CNT_L</name>
|
||
|
|
<description>Low counter value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PSC</name>
|
||
|
|
<displayName>PSC</displayName>
|
||
|
|
<description>prescaler</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PSC</name>
|
||
|
|
<description>Prescaler value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ARR</name>
|
||
|
|
<displayName>ARR</displayName>
|
||
|
|
<description>auto-reload register</description>
|
||
|
|
<addressOffset>0x2C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ARR_H</name>
|
||
|
|
<description>High Auto-reload value (TIM2
|
||
|
|
only)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARR_L</name>
|
||
|
|
<description>Low Auto-reload value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR1</name>
|
||
|
|
<displayName>CCR1</displayName>
|
||
|
|
<description>capture/compare register 1</description>
|
||
|
|
<addressOffset>0x34</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CCR1_H</name>
|
||
|
|
<description>High Capture/Compare 1 value (TIM2
|
||
|
|
only)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CCR1_L</name>
|
||
|
|
<description>Low Capture/Compare 1
|
||
|
|
value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR2</name>
|
||
|
|
<displayName>CCR2</displayName>
|
||
|
|
<description>capture/compare register 2</description>
|
||
|
|
<addressOffset>0x38</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CCR2_H</name>
|
||
|
|
<description>High Capture/Compare 2 value (TIM2
|
||
|
|
only)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CCR2_L</name>
|
||
|
|
<description>Low Capture/Compare 2
|
||
|
|
value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR3</name>
|
||
|
|
<displayName>CCR3</displayName>
|
||
|
|
<description>capture/compare register 3</description>
|
||
|
|
<addressOffset>0x3C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CCR3_H</name>
|
||
|
|
<description>High Capture/Compare value (TIM2
|
||
|
|
only)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CCR3_L</name>
|
||
|
|
<description>Low Capture/Compare value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR4</name>
|
||
|
|
<displayName>CCR4</displayName>
|
||
|
|
<description>capture/compare register 4</description>
|
||
|
|
<addressOffset>0x40</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CCR4_H</name>
|
||
|
|
<description>High Capture/Compare value (TIM2
|
||
|
|
only)</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CCR4_L</name>
|
||
|
|
<description>Low Capture/Compare value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>DCR</name>
|
||
|
|
<displayName>DCR</displayName>
|
||
|
|
<description>DMA control register</description>
|
||
|
|
<addressOffset>0x48</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DBL</name>
|
||
|
|
<description>DMA burst length</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>5</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DBA</name>
|
||
|
|
<description>DMA base address</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>5</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>DMAR</name>
|
||
|
|
<displayName>DMAR</displayName>
|
||
|
|
<description>DMA address for full transfer</description>
|
||
|
|
<addressOffset>0x4C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>DMAB</name>
|
||
|
|
<description>DMA register for burst
|
||
|
|
accesses</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OR</name>
|
||
|
|
<displayName>OR</displayName>
|
||
|
|
<description>TIM2 option register</description>
|
||
|
|
<addressOffset>0x50</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ETR_RMP</name>
|
||
|
|
<description>Timer2 ETR remap</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TI4_RMP</name>
|
||
|
|
<description>Internal trigger</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="TIM2">
|
||
|
|
<name>TIM3</name>
|
||
|
|
<baseAddress>0x40000400</baseAddress>
|
||
|
|
<interrupt>
|
||
|
|
<name>TIM3</name>
|
||
|
|
<description>TIM3 global interrupt</description>
|
||
|
|
<value>16</value>
|
||
|
|
</interrupt>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>TIM6</name>
|
||
|
|
<description>Basic-timers</description>
|
||
|
|
<groupName>TIM</groupName>
|
||
|
|
<baseAddress>0x40001000</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>TIM6</name>
|
||
|
|
<description>TIM6 global interrupt and DAC</description>
|
||
|
|
<value>17</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR1</name>
|
||
|
|
<displayName>CR1</displayName>
|
||
|
|
<description>control register 1</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ARPE</name>
|
||
|
|
<description>Auto-reload preload enable</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OPM</name>
|
||
|
|
<description>One-pulse mode</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>URS</name>
|
||
|
|
<description>Update request source</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UDIS</name>
|
||
|
|
<description>Update disable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CEN</name>
|
||
|
|
<description>Counter enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR2</name>
|
||
|
|
<displayName>CR2</displayName>
|
||
|
|
<description>control register 2</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MMS</name>
|
||
|
|
<description>Master mode selection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>DIER</name>
|
||
|
|
<displayName>DIER</displayName>
|
||
|
|
<description>DMA/Interrupt enable register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>UDE</name>
|
||
|
|
<description>Update DMA request enable</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UIE</name>
|
||
|
|
<description>Update interrupt enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SR</name>
|
||
|
|
<displayName>SR</displayName>
|
||
|
|
<description>status register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>UIF</name>
|
||
|
|
<description>Update interrupt flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>EGR</name>
|
||
|
|
<displayName>EGR</displayName>
|
||
|
|
<description>event generation register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>UG</name>
|
||
|
|
<description>Update generation</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNT</name>
|
||
|
|
<displayName>CNT</displayName>
|
||
|
|
<description>counter</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CNT</name>
|
||
|
|
<description>Low counter value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PSC</name>
|
||
|
|
<displayName>PSC</displayName>
|
||
|
|
<description>prescaler</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PSC</name>
|
||
|
|
<description>Prescaler value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ARR</name>
|
||
|
|
<displayName>ARR</displayName>
|
||
|
|
<description>auto-reload register</description>
|
||
|
|
<addressOffset>0x2C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ARR</name>
|
||
|
|
<description>Low Auto-reload value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral derivedFrom="TIM6">
|
||
|
|
<name>TIM7</name>
|
||
|
|
<baseAddress>0x40001400</baseAddress>
|
||
|
|
<interrupt>
|
||
|
|
<name>TIM7</name>
|
||
|
|
<description>TIM7 global interrupt and DAC</description>
|
||
|
|
<value>18</value>
|
||
|
|
</interrupt>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>TIM21</name>
|
||
|
|
<description>General-purpose-timers</description>
|
||
|
|
<groupName>TIM</groupName>
|
||
|
|
<baseAddress>0x40010800</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>TIM21</name>
|
||
|
|
<description>TIMER21 global interrupt</description>
|
||
|
|
<value>20</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR1</name>
|
||
|
|
<displayName>CR1</displayName>
|
||
|
|
<description>control register 1</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CEN</name>
|
||
|
|
<description>Counter enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UDIS</name>
|
||
|
|
<description>Update disable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>URS</name>
|
||
|
|
<description>Update request source</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OPM</name>
|
||
|
|
<description>One-pulse mode</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIR</name>
|
||
|
|
<description>Direction</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMS</name>
|
||
|
|
<description>Center-aligned mode
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARPE</name>
|
||
|
|
<description>Auto-reload preload enable</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CKD</name>
|
||
|
|
<description>Clock division</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR2</name>
|
||
|
|
<displayName>CR2</displayName>
|
||
|
|
<description>control register 2</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MMS</name>
|
||
|
|
<description>Master mode selection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SMCR</name>
|
||
|
|
<displayName>SMCR</displayName>
|
||
|
|
<description>slave mode control register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>SMS</name>
|
||
|
|
<description>Slave mode selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TS</name>
|
||
|
|
<description>Trigger selection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSM</name>
|
||
|
|
<description>Master/Slave mode</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ETF</name>
|
||
|
|
<description>External trigger filter</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ETPS</name>
|
||
|
|
<description>External trigger prescaler</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ECE</name>
|
||
|
|
<description>External clock enable</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ETP</name>
|
||
|
|
<description>External trigger polarity</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>DIER</name>
|
||
|
|
<displayName>DIER</displayName>
|
||
|
|
<description>DMA/Interrupt enable register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TIE</name>
|
||
|
|
<description>Trigger interrupt enable</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2IE</name>
|
||
|
|
<description>Capture/Compare 2 interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1IE</name>
|
||
|
|
<description>Capture/Compare 1 interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UIE</name>
|
||
|
|
<description>Update interrupt enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SR</name>
|
||
|
|
<displayName>SR</displayName>
|
||
|
|
<description>status register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CC2OF</name>
|
||
|
|
<description>Capture/compare 2 overcapture
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1OF</name>
|
||
|
|
<description>Capture/Compare 1 overcapture
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIF</name>
|
||
|
|
<description>Trigger interrupt flag</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2IF</name>
|
||
|
|
<description>Capture/Compare 2 interrupt
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1IF</name>
|
||
|
|
<description>Capture/compare 1 interrupt
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UIF</name>
|
||
|
|
<description>Update interrupt flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>EGR</name>
|
||
|
|
<displayName>EGR</displayName>
|
||
|
|
<description>event generation register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TG</name>
|
||
|
|
<description>Trigger generation</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2G</name>
|
||
|
|
<description>Capture/compare 2
|
||
|
|
generation</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1G</name>
|
||
|
|
<description>Capture/compare 1
|
||
|
|
generation</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UG</name>
|
||
|
|
<description>Update generation</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCMR1_Output</name>
|
||
|
|
<displayName>CCMR1_Output</displayName>
|
||
|
|
<description>capture/compare mode register (output
|
||
|
|
mode)</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OC2M</name>
|
||
|
|
<description>Output Compare 2 mode</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC2PE</name>
|
||
|
|
<description>Output Compare 2 preload
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC2FE</name>
|
||
|
|
<description>Output Compare 2 fast
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2S</name>
|
||
|
|
<description>Capture/Compare 2
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC1M</name>
|
||
|
|
<description>Output Compare 1 mode</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC1PE</name>
|
||
|
|
<description>Output Compare 1 preload
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC1FE</name>
|
||
|
|
<description>Output Compare 1 fast
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1S</name>
|
||
|
|
<description>Capture/Compare 1
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCMR1_Input</name>
|
||
|
|
<displayName>CCMR1_Input</displayName>
|
||
|
|
<description>capture/compare mode register 1 (input
|
||
|
|
mode)</description>
|
||
|
|
<alternateRegister>CCMR1_Output</alternateRegister>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>IC2F</name>
|
||
|
|
<description>Input capture 2 filter</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC2PSC</name>
|
||
|
|
<description>Input capture 2 prescaler</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2S</name>
|
||
|
|
<description>Capture/Compare 2
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC1F</name>
|
||
|
|
<description>Input capture 1 filter</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC1PSC</name>
|
||
|
|
<description>Input capture 1 prescaler</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1S</name>
|
||
|
|
<description>Capture/Compare 1
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCER</name>
|
||
|
|
<displayName>CCER</displayName>
|
||
|
|
<description>capture/compare enable
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CC2NP</name>
|
||
|
|
<description>Capture/Compare 2 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2P</name>
|
||
|
|
<description>Capture/Compare 2 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2E</name>
|
||
|
|
<description>Capture/Compare 2 output
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1NP</name>
|
||
|
|
<description>Capture/Compare 1 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1P</name>
|
||
|
|
<description>Capture/Compare 1 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1E</name>
|
||
|
|
<description>Capture/Compare 1 output
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNT</name>
|
||
|
|
<displayName>CNT</displayName>
|
||
|
|
<description>counter</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CNT</name>
|
||
|
|
<description>counter value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PSC</name>
|
||
|
|
<displayName>PSC</displayName>
|
||
|
|
<description>prescaler</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PSC</name>
|
||
|
|
<description>Prescaler value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ARR</name>
|
||
|
|
<displayName>ARR</displayName>
|
||
|
|
<description>auto-reload register</description>
|
||
|
|
<addressOffset>0x2C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ARR</name>
|
||
|
|
<description>Auto-reload value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR1</name>
|
||
|
|
<displayName>CCR1</displayName>
|
||
|
|
<description>capture/compare register 1</description>
|
||
|
|
<addressOffset>0x34</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CCR1</name>
|
||
|
|
<description>Capture/Compare 1 value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR2</name>
|
||
|
|
<displayName>CCR2</displayName>
|
||
|
|
<description>capture/compare register 2</description>
|
||
|
|
<addressOffset>0x38</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CCR2</name>
|
||
|
|
<description>Capture/Compare 2 value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OR</name>
|
||
|
|
<displayName>OR</displayName>
|
||
|
|
<description>TIM21 option register</description>
|
||
|
|
<addressOffset>0x50</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ETR_RMP</name>
|
||
|
|
<description>Timer21 ETR remap</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TI1_RMP</name>
|
||
|
|
<description>Timer21 TI1</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TI2_RMP</name>
|
||
|
|
<description>Timer21 TI2</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>TIM22</name>
|
||
|
|
<description>General-purpose-timers</description>
|
||
|
|
<groupName>TIM</groupName>
|
||
|
|
<baseAddress>0x40011400</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<interrupt>
|
||
|
|
<name>TIM22</name>
|
||
|
|
<description>TIMER22 global interrupt</description>
|
||
|
|
<value>22</value>
|
||
|
|
</interrupt>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR1</name>
|
||
|
|
<displayName>CR1</displayName>
|
||
|
|
<description>control register 1</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CEN</name>
|
||
|
|
<description>Counter enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UDIS</name>
|
||
|
|
<description>Update disable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>URS</name>
|
||
|
|
<description>Update request source</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OPM</name>
|
||
|
|
<description>One-pulse mode</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIR</name>
|
||
|
|
<description>Direction</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMS</name>
|
||
|
|
<description>Center-aligned mode
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ARPE</name>
|
||
|
|
<description>Auto-reload preload enable</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CKD</name>
|
||
|
|
<description>Clock division</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR2</name>
|
||
|
|
<displayName>CR2</displayName>
|
||
|
|
<description>control register 2</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>MMS</name>
|
||
|
|
<description>Master mode selection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SMCR</name>
|
||
|
|
<displayName>SMCR</displayName>
|
||
|
|
<description>slave mode control register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>SMS</name>
|
||
|
|
<description>Slave mode selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TS</name>
|
||
|
|
<description>Trigger selection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSM</name>
|
||
|
|
<description>Master/Slave mode</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ETF</name>
|
||
|
|
<description>External trigger filter</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ETPS</name>
|
||
|
|
<description>External trigger prescaler</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ECE</name>
|
||
|
|
<description>External clock enable</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ETP</name>
|
||
|
|
<description>External trigger polarity</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>DIER</name>
|
||
|
|
<displayName>DIER</displayName>
|
||
|
|
<description>DMA/Interrupt enable register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TIE</name>
|
||
|
|
<description>Trigger interrupt enable</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2IE</name>
|
||
|
|
<description>Capture/Compare 2 interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1IE</name>
|
||
|
|
<description>Capture/Compare 1 interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UIE</name>
|
||
|
|
<description>Update interrupt enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SR</name>
|
||
|
|
<displayName>SR</displayName>
|
||
|
|
<description>status register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CC2OF</name>
|
||
|
|
<description>Capture/compare 2 overcapture
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1OF</name>
|
||
|
|
<description>Capture/Compare 1 overcapture
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TIF</name>
|
||
|
|
<description>Trigger interrupt flag</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2IF</name>
|
||
|
|
<description>Capture/Compare 2 interrupt
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1IF</name>
|
||
|
|
<description>Capture/compare 1 interrupt
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UIF</name>
|
||
|
|
<description>Update interrupt flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>EGR</name>
|
||
|
|
<displayName>EGR</displayName>
|
||
|
|
<description>event generation register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TG</name>
|
||
|
|
<description>Trigger generation</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2G</name>
|
||
|
|
<description>Capture/compare 2
|
||
|
|
generation</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1G</name>
|
||
|
|
<description>Capture/compare 1
|
||
|
|
generation</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UG</name>
|
||
|
|
<description>Update generation</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCMR1_Output</name>
|
||
|
|
<displayName>CCMR1_Output</displayName>
|
||
|
|
<description>capture/compare mode register (output
|
||
|
|
mode)</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>OC2M</name>
|
||
|
|
<description>Output Compare 2 mode</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC2PE</name>
|
||
|
|
<description>Output Compare 2 preload
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC2FE</name>
|
||
|
|
<description>Output Compare 2 fast
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2S</name>
|
||
|
|
<description>Capture/Compare 2
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC1M</name>
|
||
|
|
<description>Output Compare 1 mode</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC1PE</name>
|
||
|
|
<description>Output Compare 1 preload
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OC1FE</name>
|
||
|
|
<description>Output Compare 1 fast
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1S</name>
|
||
|
|
<description>Capture/Compare 1
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCMR1_Input</name>
|
||
|
|
<displayName>CCMR1_Input</displayName>
|
||
|
|
<description>capture/compare mode register 1 (input
|
||
|
|
mode)</description>
|
||
|
|
<alternateRegister>CCMR1_Output</alternateRegister>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>IC2F</name>
|
||
|
|
<description>Input capture 2 filter</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC2PSC</name>
|
||
|
|
<description>Input capture 2 prescaler</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2S</name>
|
||
|
|
<description>Capture/Compare 2
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC1F</name>
|
||
|
|
<description>Input capture 1 filter</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IC1PSC</name>
|
||
|
|
<description>Input capture 1 prescaler</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1S</name>
|
||
|
|
<description>Capture/Compare 1
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCER</name>
|
||
|
|
<displayName>CCER</displayName>
|
||
|
|
<description>capture/compare enable
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CC2NP</name>
|
||
|
|
<description>Capture/Compare 2 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2P</name>
|
||
|
|
<description>Capture/Compare 2 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC2E</name>
|
||
|
|
<description>Capture/Compare 2 output
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1NP</name>
|
||
|
|
<description>Capture/Compare 1 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1P</name>
|
||
|
|
<description>Capture/Compare 1 output
|
||
|
|
Polarity</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CC1E</name>
|
||
|
|
<description>Capture/Compare 1 output
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CNT</name>
|
||
|
|
<displayName>CNT</displayName>
|
||
|
|
<description>counter</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CNT</name>
|
||
|
|
<description>counter value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>PSC</name>
|
||
|
|
<displayName>PSC</displayName>
|
||
|
|
<description>prescaler</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PSC</name>
|
||
|
|
<description>Prescaler value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ARR</name>
|
||
|
|
<displayName>ARR</displayName>
|
||
|
|
<description>auto-reload register</description>
|
||
|
|
<addressOffset>0x2C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ARR</name>
|
||
|
|
<description>Auto-reload value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR1</name>
|
||
|
|
<displayName>CCR1</displayName>
|
||
|
|
<description>capture/compare register 1</description>
|
||
|
|
<addressOffset>0x34</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CCR1</name>
|
||
|
|
<description>Capture/Compare 1 value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR2</name>
|
||
|
|
<displayName>CCR2</displayName>
|
||
|
|
<description>capture/compare register 2</description>
|
||
|
|
<addressOffset>0x38</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CCR2</name>
|
||
|
|
<description>Capture/Compare 2 value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>OR</name>
|
||
|
|
<displayName>OR</displayName>
|
||
|
|
<description>TIM22 option register</description>
|
||
|
|
<addressOffset>0x50</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ETR_RMP</name>
|
||
|
|
<description>Timer22 ETR remap</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TI1_RMP</name>
|
||
|
|
<description>Timer22 TI1</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>LPUART1</name>
|
||
|
|
<description>Lower power Universal asynchronous receiver
|
||
|
|
transmitter</description>
|
||
|
|
<groupName>USART</groupName>
|
||
|
|
<baseAddress>0x40004800</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x400</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CR1</name>
|
||
|
|
<displayName>CR1</displayName>
|
||
|
|
<description>Control register 1</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>M1</name>
|
||
|
|
<description>Word length</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEAT4</name>
|
||
|
|
<description>Driver Enable assertion
|
||
|
|
time</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEAT3</name>
|
||
|
|
<description>DEAT3</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEAT2</name>
|
||
|
|
<description>DEAT2</description>
|
||
|
|
<bitOffset>23</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEAT1</name>
|
||
|
|
<description>DEAT1</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEAT0</name>
|
||
|
|
<description>DEAT0</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEDT4</name>
|
||
|
|
<description>Driver Enable de-assertion
|
||
|
|
time</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEDT3</name>
|
||
|
|
<description>DEDT3</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEDT2</name>
|
||
|
|
<description>DEDT2</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEDT1</name>
|
||
|
|
<description>DEDT1</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEDT0</name>
|
||
|
|
<description>DEDT0</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMIE</name>
|
||
|
|
<description>Character match interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MME</name>
|
||
|
|
<description>Mute mode enable</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>M0</name>
|
||
|
|
<description>Word length</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WAKE</name>
|
||
|
|
<description>Receiver wakeup method</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PCE</name>
|
||
|
|
<description>Parity control enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PS</name>
|
||
|
|
<description>Parity selection</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PEIE</name>
|
||
|
|
<description>PE interrupt enable</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXEIE</name>
|
||
|
|
<description>interrupt enable</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCIE</name>
|
||
|
|
<description>Transmission complete interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXNEIE</name>
|
||
|
|
<description>RXNE interrupt enable</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IDLEIE</name>
|
||
|
|
<description>IDLE interrupt enable</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TE</name>
|
||
|
|
<description>Transmitter enable</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RE</name>
|
||
|
|
<description>Receiver enable</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UESM</name>
|
||
|
|
<description>USART enable in Stop mode</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UE</name>
|
||
|
|
<description>USART enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR2</name>
|
||
|
|
<displayName>CR2</displayName>
|
||
|
|
<description>Control register 2</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ADD4_7</name>
|
||
|
|
<description>Address of the USART node</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADD0_3</name>
|
||
|
|
<description>Address of the USART node</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MSBFIRST</name>
|
||
|
|
<description>Most significant bit first</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TAINV</name>
|
||
|
|
<description>Binary data inversion</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXINV</name>
|
||
|
|
<description>TX pin active level
|
||
|
|
inversion</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXINV</name>
|
||
|
|
<description>RX pin active level
|
||
|
|
inversion</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SWAP</name>
|
||
|
|
<description>Swap TX/RX pins</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>STOP</name>
|
||
|
|
<description>STOP bits</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CLKEN</name>
|
||
|
|
<description>Clock enable</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADDM7</name>
|
||
|
|
<description>7-bit Address Detection/4-bit Address
|
||
|
|
Detection</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CR3</name>
|
||
|
|
<displayName>CR3</displayName>
|
||
|
|
<description>Control register 3</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>WUFIE</name>
|
||
|
|
<description>Wakeup from Stop mode interrupt
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WUS</name>
|
||
|
|
<description>Wakeup from Stop mode interrupt flag
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>2</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEP</name>
|
||
|
|
<description>Driver enable polarity
|
||
|
|
selection</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DEM</name>
|
||
|
|
<description>Driver enable mode</description>
|
||
|
|
<bitOffset>14</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DDRE</name>
|
||
|
|
<description>DMA Disable on Reception
|
||
|
|
Error</description>
|
||
|
|
<bitOffset>13</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>OVRDIS</name>
|
||
|
|
<description>Overrun Disable</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTSIE</name>
|
||
|
|
<description>CTS interrupt enable</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTSE</name>
|
||
|
|
<description>CTS enable</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RTSE</name>
|
||
|
|
<description>RTS enable</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DMAT</name>
|
||
|
|
<description>DMA enable transmitter</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DMAR</name>
|
||
|
|
<description>DMA enable receiver</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HDSEL</name>
|
||
|
|
<description>Half-duplex selection</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>EIE</name>
|
||
|
|
<description>Error interrupt enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>BRR</name>
|
||
|
|
<displayName>BRR</displayName>
|
||
|
|
<description>Baud rate register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>BRR</name>
|
||
|
|
<description>BRR</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>20</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>RQR</name>
|
||
|
|
<displayName>RQR</displayName>
|
||
|
|
<description>Request register</description>
|
||
|
|
<addressOffset>0x18</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RXFRQ</name>
|
||
|
|
<description>Receive data flush request</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>MMRQ</name>
|
||
|
|
<description>Mute mode request</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SBKRQ</name>
|
||
|
|
<description>Send break request</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ISR</name>
|
||
|
|
<displayName>ISR</displayName>
|
||
|
|
<description>Interrupt & status
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x00C0</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>REACK</name>
|
||
|
|
<description>REACK</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEACK</name>
|
||
|
|
<description>TEACK</description>
|
||
|
|
<bitOffset>21</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>WUF</name>
|
||
|
|
<description>WUF</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RWU</name>
|
||
|
|
<description>RWU</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SBKF</name>
|
||
|
|
<description>SBKF</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMF</name>
|
||
|
|
<description>CMF</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BUSY</name>
|
||
|
|
<description>BUSY</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTS</name>
|
||
|
|
<description>CTS</description>
|
||
|
|
<bitOffset>10</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTSIF</name>
|
||
|
|
<description>CTSIF</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TXE</name>
|
||
|
|
<description>TXE</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TC</name>
|
||
|
|
<description>TC</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RXNE</name>
|
||
|
|
<description>RXNE</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IDLE</name>
|
||
|
|
<description>IDLE</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ORE</name>
|
||
|
|
<description>ORE</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NF</name>
|
||
|
|
<description>NF</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FE</name>
|
||
|
|
<description>FE</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PE</name>
|
||
|
|
<description>PE</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ICR</name>
|
||
|
|
<displayName>ICR</displayName>
|
||
|
|
<description>Interrupt flag clear register</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>write-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>WUCF</name>
|
||
|
|
<description>Wakeup from Stop mode clear
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CMCF</name>
|
||
|
|
<description>Character match clear flag</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CTSCF</name>
|
||
|
|
<description>CTS clear flag</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TCCF</name>
|
||
|
|
<description>Transmission complete clear
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>6</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IDLECF</name>
|
||
|
|
<description>Idle line detected clear
|
||
|
|
flag</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ORECF</name>
|
||
|
|
<description>Overrun error clear flag</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NCF</name>
|
||
|
|
<description>Noise detected clear flag</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>FECF</name>
|
||
|
|
<description>Framing error clear flag</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PECF</name>
|
||
|
|
<description>Parity error clear flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>RDR</name>
|
||
|
|
<displayName>RDR</displayName>
|
||
|
|
<description>Receive data register</description>
|
||
|
|
<addressOffset>0x24</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RDR</name>
|
||
|
|
<description>Receive data value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>9</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>TDR</name>
|
||
|
|
<displayName>TDR</displayName>
|
||
|
|
<description>Transmit data register</description>
|
||
|
|
<addressOffset>0x28</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x0000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TDR</name>
|
||
|
|
<description>Transmit data value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>9</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>NVIC</name>
|
||
|
|
<description>Nested Vectored Interrupt
|
||
|
|
Controller</description>
|
||
|
|
<groupName>NVIC</groupName>
|
||
|
|
<baseAddress>0xE000E100</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x33D</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>ISER</name>
|
||
|
|
<displayName>ISER</displayName>
|
||
|
|
<description>Interrupt Set Enable Register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>SETENA</name>
|
||
|
|
<description>SETENA</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ICER</name>
|
||
|
|
<displayName>ICER</displayName>
|
||
|
|
<description>Interrupt Clear Enable
|
||
|
|
Register</description>
|
||
|
|
<addressOffset>0x80</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CLRENA</name>
|
||
|
|
<description>CLRENA</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ISPR</name>
|
||
|
|
<displayName>ISPR</displayName>
|
||
|
|
<description>Interrupt Set-Pending Register</description>
|
||
|
|
<addressOffset>0x100</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>SETPEND</name>
|
||
|
|
<description>SETPEND</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ICPR</name>
|
||
|
|
<displayName>ICPR</displayName>
|
||
|
|
<description>Interrupt Clear-Pending
|
||
|
|
Register</description>
|
||
|
|
<addressOffset>0x180</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CLRPEND</name>
|
||
|
|
<description>CLRPEND</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>32</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IPR0</name>
|
||
|
|
<displayName>IPR0</displayName>
|
||
|
|
<description>Interrupt Priority Register 0</description>
|
||
|
|
<addressOffset>0x300</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRI_0</name>
|
||
|
|
<description>priority for interrupt 0</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_1</name>
|
||
|
|
<description>priority for interrupt 1</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_2</name>
|
||
|
|
<description>priority for interrupt 2</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_3</name>
|
||
|
|
<description>priority for interrupt 3</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IPR1</name>
|
||
|
|
<displayName>IPR1</displayName>
|
||
|
|
<description>Interrupt Priority Register 1</description>
|
||
|
|
<addressOffset>0x304</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRI_4</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_5</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_6</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_7</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IPR2</name>
|
||
|
|
<displayName>IPR2</displayName>
|
||
|
|
<description>Interrupt Priority Register 2</description>
|
||
|
|
<addressOffset>0x308</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRI_8</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_9</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_10</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_11</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IPR3</name>
|
||
|
|
<displayName>IPR3</displayName>
|
||
|
|
<description>Interrupt Priority Register 3</description>
|
||
|
|
<addressOffset>0x30C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRI_12</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_13</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_14</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_15</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IPR4</name>
|
||
|
|
<displayName>IPR4</displayName>
|
||
|
|
<description>Interrupt Priority Register 4</description>
|
||
|
|
<addressOffset>0x310</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRI_16</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_17</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_18</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_19</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IPR5</name>
|
||
|
|
<displayName>IPR5</displayName>
|
||
|
|
<description>Interrupt Priority Register 5</description>
|
||
|
|
<addressOffset>0x314</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRI_20</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_21</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_22</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_23</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IPR6</name>
|
||
|
|
<displayName>IPR6</displayName>
|
||
|
|
<description>Interrupt Priority Register 6</description>
|
||
|
|
<addressOffset>0x318</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRI_24</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_25</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_26</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_27</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>IPR7</name>
|
||
|
|
<displayName>IPR7</displayName>
|
||
|
|
<description>Interrupt Priority Register 7</description>
|
||
|
|
<addressOffset>0x31C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRI_28</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_29</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_30</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_31</name>
|
||
|
|
<description>priority for interrupt n</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>MPU</name>
|
||
|
|
<description>Memory protection unit</description>
|
||
|
|
<groupName>MPU</groupName>
|
||
|
|
<baseAddress>0xE000ED90</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x15</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>MPU_TYPER</name>
|
||
|
|
<displayName>MPU_TYPER</displayName>
|
||
|
|
<description>MPU type register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0X00000800</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>SEPARATE</name>
|
||
|
|
<description>Separate flag</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DREGION</name>
|
||
|
|
<description>Number of MPU data regions</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>IREGION</name>
|
||
|
|
<description>Number of MPU instruction
|
||
|
|
regions</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>MPU_CTRL</name>
|
||
|
|
<displayName>MPU_CTRL</displayName>
|
||
|
|
<description>MPU control register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0X00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ENABLE</name>
|
||
|
|
<description>Enables the MPU</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>HFNMIENA</name>
|
||
|
|
<description>Enables the operation of MPU during hard
|
||
|
|
fault</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRIVDEFENA</name>
|
||
|
|
<description>Enable priviliged software access to
|
||
|
|
default memory map</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>MPU_RNR</name>
|
||
|
|
<displayName>MPU_RNR</displayName>
|
||
|
|
<description>MPU region number register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0X00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>REGION</name>
|
||
|
|
<description>MPU region</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>MPU_RBAR</name>
|
||
|
|
<displayName>MPU_RBAR</displayName>
|
||
|
|
<description>MPU region base address
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0X00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>REGION</name>
|
||
|
|
<description>MPU region field</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>VALID</name>
|
||
|
|
<description>MPU region number valid</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ADDR</name>
|
||
|
|
<description>Region base address field</description>
|
||
|
|
<bitOffset>5</bitOffset>
|
||
|
|
<bitWidth>27</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>MPU_RASR</name>
|
||
|
|
<displayName>MPU_RASR</displayName>
|
||
|
|
<description>MPU region attribute and size
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0X00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ENABLE</name>
|
||
|
|
<description>Region enable bit.</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SIZE</name>
|
||
|
|
<description>Size of the MPU protection
|
||
|
|
region</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>5</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SRD</name>
|
||
|
|
<description>Subregion disable bits</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>B</name>
|
||
|
|
<description>memory attribute</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>C</name>
|
||
|
|
<description>memory attribute</description>
|
||
|
|
<bitOffset>17</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>S</name>
|
||
|
|
<description>Shareable memory attribute</description>
|
||
|
|
<bitOffset>18</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TEX</name>
|
||
|
|
<description>memory attribute</description>
|
||
|
|
<bitOffset>19</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>AP</name>
|
||
|
|
<description>Access permission</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>3</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>XN</name>
|
||
|
|
<description>Instruction access disable
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>STK</name>
|
||
|
|
<description>SysTick timer</description>
|
||
|
|
<groupName>STK</groupName>
|
||
|
|
<baseAddress>0xE000E010</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x11</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CSR</name>
|
||
|
|
<displayName>CSR</displayName>
|
||
|
|
<description>SysTick control and status
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0X00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>ENABLE</name>
|
||
|
|
<description>Counter enable</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>TICKINT</name>
|
||
|
|
<description>SysTick exception request
|
||
|
|
enable</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>CLKSOURCE</name>
|
||
|
|
<description>Clock source selection</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>COUNTFLAG</name>
|
||
|
|
<description>COUNTFLAG</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>RVR</name>
|
||
|
|
<displayName>RVR</displayName>
|
||
|
|
<description>SysTick reload value register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0X00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>RELOAD</name>
|
||
|
|
<description>RELOAD value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>24</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CVR</name>
|
||
|
|
<displayName>CVR</displayName>
|
||
|
|
<description>SysTick current value register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0X00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>CURRENT</name>
|
||
|
|
<description>Current counter value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>24</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CALIB</name>
|
||
|
|
<displayName>CALIB</displayName>
|
||
|
|
<description>SysTick calibration value
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0X00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TENMS</name>
|
||
|
|
<description>Calibration value</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>24</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SKEW</name>
|
||
|
|
<description>SKEW flag: Indicates whether the TENMS
|
||
|
|
value is exact</description>
|
||
|
|
<bitOffset>30</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NOREF</name>
|
||
|
|
<description>NOREF flag. Reads as zero</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
<peripheral>
|
||
|
|
<name>SCB</name>
|
||
|
|
<description>System control block</description>
|
||
|
|
<groupName>SCB</groupName>
|
||
|
|
<baseAddress>0xE000ED00</baseAddress>
|
||
|
|
<addressBlock>
|
||
|
|
<offset>0x0</offset>
|
||
|
|
<size>0x41</size>
|
||
|
|
<usage>registers</usage>
|
||
|
|
</addressBlock>
|
||
|
|
<registers>
|
||
|
|
<register>
|
||
|
|
<name>CPUID</name>
|
||
|
|
<displayName>CPUID</displayName>
|
||
|
|
<description>CPUID base register</description>
|
||
|
|
<addressOffset>0x0</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-only</access>
|
||
|
|
<resetValue>0x410FC241</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>Revision</name>
|
||
|
|
<description>Revision number</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PartNo</name>
|
||
|
|
<description>Part number of the
|
||
|
|
processor</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>12</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>Architecture</name>
|
||
|
|
<description>Reads as 0xF</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>Variant</name>
|
||
|
|
<description>Variant number</description>
|
||
|
|
<bitOffset>20</bitOffset>
|
||
|
|
<bitWidth>4</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>Implementer</name>
|
||
|
|
<description>Implementer code</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>ICSR</name>
|
||
|
|
<displayName>ICSR</displayName>
|
||
|
|
<description>Interrupt control and state
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x4</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>VECTACTIVE</name>
|
||
|
|
<description>Active vector</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>9</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>RETTOBASE</name>
|
||
|
|
<description>Return to base level</description>
|
||
|
|
<bitOffset>11</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>VECTPENDING</name>
|
||
|
|
<description>Pending vector</description>
|
||
|
|
<bitOffset>12</bitOffset>
|
||
|
|
<bitWidth>7</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ISRPENDING</name>
|
||
|
|
<description>Interrupt pending flag</description>
|
||
|
|
<bitOffset>22</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PENDSTCLR</name>
|
||
|
|
<description>SysTick exception clear-pending
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>25</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PENDSTSET</name>
|
||
|
|
<description>SysTick exception set-pending
|
||
|
|
bit</description>
|
||
|
|
<bitOffset>26</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PENDSVCLR</name>
|
||
|
|
<description>PendSV clear-pending bit</description>
|
||
|
|
<bitOffset>27</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PENDSVSET</name>
|
||
|
|
<description>PendSV set-pending bit</description>
|
||
|
|
<bitOffset>28</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>NMIPENDSET</name>
|
||
|
|
<description>NMI set-pending bit.</description>
|
||
|
|
<bitOffset>31</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>VTOR</name>
|
||
|
|
<displayName>VTOR</displayName>
|
||
|
|
<description>Vector table offset register</description>
|
||
|
|
<addressOffset>0x8</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>TBLOFF</name>
|
||
|
|
<description>Vector table base offset
|
||
|
|
field</description>
|
||
|
|
<bitOffset>7</bitOffset>
|
||
|
|
<bitWidth>25</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>AIRCR</name>
|
||
|
|
<displayName>AIRCR</displayName>
|
||
|
|
<description>Application interrupt and reset control
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0xC</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>VECTCLRACTIVE</name>
|
||
|
|
<description>VECTCLRACTIVE</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SYSRESETREQ</name>
|
||
|
|
<description>SYSRESETREQ</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>ENDIANESS</name>
|
||
|
|
<description>ENDIANESS</description>
|
||
|
|
<bitOffset>15</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>VECTKEYSTAT</name>
|
||
|
|
<description>Register key</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>16</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SCR</name>
|
||
|
|
<displayName>SCR</displayName>
|
||
|
|
<description>System control register</description>
|
||
|
|
<addressOffset>0x10</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>SLEEPONEXIT</name>
|
||
|
|
<description>SLEEPONEXIT</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SLEEPDEEP</name>
|
||
|
|
<description>SLEEPDEEP</description>
|
||
|
|
<bitOffset>2</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>SEVEONPEND</name>
|
||
|
|
<description>Send Event on Pending bit</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>CCR</name>
|
||
|
|
<displayName>CCR</displayName>
|
||
|
|
<description>Configuration and control
|
||
|
|
register</description>
|
||
|
|
<addressOffset>0x14</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>NONBASETHRDENA</name>
|
||
|
|
<description>Configures how the processor enters
|
||
|
|
Thread mode</description>
|
||
|
|
<bitOffset>0</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>USERSETMPEND</name>
|
||
|
|
<description>USERSETMPEND</description>
|
||
|
|
<bitOffset>1</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>UNALIGN__TRP</name>
|
||
|
|
<description>UNALIGN_ TRP</description>
|
||
|
|
<bitOffset>3</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>DIV_0_TRP</name>
|
||
|
|
<description>DIV_0_TRP</description>
|
||
|
|
<bitOffset>4</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>BFHFNMIGN</name>
|
||
|
|
<description>BFHFNMIGN</description>
|
||
|
|
<bitOffset>8</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>STKALIGN</name>
|
||
|
|
<description>STKALIGN</description>
|
||
|
|
<bitOffset>9</bitOffset>
|
||
|
|
<bitWidth>1</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SHPR2</name>
|
||
|
|
<displayName>SHPR2</displayName>
|
||
|
|
<description>System handler priority
|
||
|
|
registers</description>
|
||
|
|
<addressOffset>0x1C</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRI_11</name>
|
||
|
|
<description>Priority of system handler
|
||
|
|
11</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
<register>
|
||
|
|
<name>SHPR3</name>
|
||
|
|
<displayName>SHPR3</displayName>
|
||
|
|
<description>System handler priority
|
||
|
|
registers</description>
|
||
|
|
<addressOffset>0x20</addressOffset>
|
||
|
|
<size>0x20</size>
|
||
|
|
<access>read-write</access>
|
||
|
|
<resetValue>0x00000000</resetValue>
|
||
|
|
<fields>
|
||
|
|
<field>
|
||
|
|
<name>PRI_14</name>
|
||
|
|
<description>Priority of system handler
|
||
|
|
14</description>
|
||
|
|
<bitOffset>16</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
<field>
|
||
|
|
<name>PRI_15</name>
|
||
|
|
<description>Priority of system handler
|
||
|
|
15</description>
|
||
|
|
<bitOffset>24</bitOffset>
|
||
|
|
<bitWidth>8</bitWidth>
|
||
|
|
</field>
|
||
|
|
</fields>
|
||
|
|
</register>
|
||
|
|
</registers>
|
||
|
|
</peripheral>
|
||
|
|
</peripherals>
|
||
|
|
</device>
|