From 9f6219a2cf4dd376ccb2c9dfcdc6f905ba96d1fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mario=20H=C3=BCttel?= Date: Thu, 10 Aug 2023 23:00:40 +0200 Subject: [PATCH] Add files --- firmware/.gitignore | 41 + firmware/LICENSE | 116 + firmware/Makefile | 102 + firmware/README.md | 2 + firmware/eeprom.c | 86 + firmware/eeprom.h | 10 + firmware/include/cmsis/cmsis_gcc.h | 1373 ++ firmware/include/cmsis/core_cm0plus.h | 914 + firmware/include/cmsis/core_cmFunc.h | 87 + firmware/include/cmsis/core_cmInstr.h | 87 + firmware/include/stm32l052xx.h | 7342 ++++++ firmware/include/stm32l0xx.h | 235 + firmware/macro_helpers.h | 13 + firmware/main.c | 506 + firmware/setup/system_init.c | 74 + firmware/startup/startup_stm32l052x8xx.c | 199 + firmware/startup/stm32l052x8xx.ld | 142 + firmware/svd/STM32L0x1.svd | 16671 +++++++++++++ firmware/svd/STM32L0x2.svd | 20698 ++++++++++++++++ firmware/svd/STM32L0x3.svd | 22518 ++++++++++++++++++ firmware/syscalls/syscalls.c | 42 + firmware/unique-id.c | 11 + firmware/unique-id.h | 8 + firmware/usb.c | 668 + firmware/usb.h | 54 + sustain-kbd-config/.gitignore | 60 + sustain-kbd-config/CMakeLists.txt | 74 + sustain-kbd-config/libusbwrapper.cpp | 137 + sustain-kbd-config/libusbwrapper.h | 47 + sustain-kbd-config/main.cpp | 23 + sustain-kbd-config/mainwindow.cpp | 228 + sustain-kbd-config/mainwindow.h | 47 + sustain-kbd-config/mainwindow.ui | 251 + sustain-kbd-config/sustainpedalkeyboard.cpp | 155 + sustain-kbd-config/sustainpedalkeyboard.h | 50 + 35 files changed, 73071 insertions(+) create mode 100644 firmware/.gitignore create mode 100644 firmware/LICENSE create mode 100644 firmware/Makefile create mode 100644 firmware/README.md create mode 100644 firmware/eeprom.c create mode 100644 firmware/eeprom.h create mode 100644 firmware/include/cmsis/cmsis_gcc.h create mode 100644 firmware/include/cmsis/core_cm0plus.h create mode 100644 firmware/include/cmsis/core_cmFunc.h create mode 100644 firmware/include/cmsis/core_cmInstr.h create mode 100644 firmware/include/stm32l052xx.h create mode 100644 firmware/include/stm32l0xx.h create mode 100644 firmware/macro_helpers.h create mode 100644 firmware/main.c create mode 100644 firmware/setup/system_init.c create mode 100644 firmware/startup/startup_stm32l052x8xx.c create mode 100644 firmware/startup/stm32l052x8xx.ld create mode 100644 firmware/svd/STM32L0x1.svd create mode 100644 firmware/svd/STM32L0x2.svd create mode 100644 firmware/svd/STM32L0x3.svd create mode 100644 firmware/syscalls/syscalls.c create mode 100644 firmware/unique-id.c create mode 100644 firmware/unique-id.h create mode 100644 firmware/usb.c create mode 100644 firmware/usb.h create mode 100644 sustain-kbd-config/.gitignore create mode 100644 sustain-kbd-config/CMakeLists.txt create mode 100644 sustain-kbd-config/libusbwrapper.cpp create mode 100644 sustain-kbd-config/libusbwrapper.h create mode 100644 sustain-kbd-config/main.cpp create mode 100644 sustain-kbd-config/mainwindow.cpp create mode 100644 sustain-kbd-config/mainwindow.h create mode 100644 sustain-kbd-config/mainwindow.ui create mode 100644 sustain-kbd-config/sustainpedalkeyboard.cpp create mode 100644 sustain-kbd-config/sustainpedalkeyboard.h diff --git a/firmware/.gitignore b/firmware/.gitignore new file mode 100644 index 0000000..9ec4b44 --- /dev/null +++ b/firmware/.gitignore @@ -0,0 +1,41 @@ +# Created by https://www.toptal.com/developers/gitignore/api/c++ +# Edit at https://www.toptal.com/developers/gitignore?templates=c++ + +### C++ ### +# Prerequisites +*.d + +# Compiled Object files +*.slo +*.lo +*.o +*.obj + +# Precompiled Headers +*.gch +*.pch + +# Compiled Dynamic libraries +*.so +*.dylib +*.dll + +# Fortran module files +*.mod +*.smod + +# Compiled Static libraries +*.lai +*.la +*.a +*.lib + +# Executables +*.exe +*.out +*.app + +# End of https://www.toptal.com/developers/gitignore/api/c++ +*.jdebug + +obj/* diff --git a/firmware/LICENSE b/firmware/LICENSE new file mode 100644 index 0000000..ee27892 --- /dev/null +++ b/firmware/LICENSE @@ -0,0 +1,116 @@ +GNU GENERAL PUBLIC LICENSE +Version 2, June 1991 +Copyright (C) 1989, 1991 Free Software Foundation, Inc. +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. + +Preamble + +The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. + +When we speak of free software, we are referring to freedom, not price. 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You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. + +You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. + +2. 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It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. + +one line to give the program's name and an idea of what it does. Copyright (C) yyyy name of author + +This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this when it starts in an interactive mode: + +Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: + +Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker. + +signature of Ty Coon, 1 April 1989 Ty Coon, President of Vice diff --git a/firmware/Makefile b/firmware/Makefile new file mode 100644 index 0000000..0e1f472 --- /dev/null +++ b/firmware/Makefile @@ -0,0 +1,102 @@ +################################Shimatta Makefile#################################### +#CPU: STM32L052 +#Compiler: arm-none-eabi +##################################################################################### + +ifneq ($(VERBOSE),true) +QUIET=@ +else +QUIET= +endif + + +#Add Files and Folders below######################################################### +CFILES = main.c syscalls/syscalls.c setup/system_init.c startup/startup_stm32l052x8xx.c usb.c unique-id.c eeprom.c +ASFILES = +INCLUDEPATH = -Iinclude -Iinclude/cmsis + +OBJDIR=obj +target = project +LIBRARYPATH = -Lstartup +LIBRARIES = + +DEFINES = -DSTM32L052xx -DSTM32L0 +mapfile = memmap + +##Custom Files### + +#TODO + + +################################################################################### +CC=arm-none-eabi-gcc +OBJCOPY=arm-none-eabi-objcopy +OBJDUMP=arm-none-eabi-objdump +SIZE=arm-none-eabi-size + +LFLAGS = -mlittle-endian -mthumb -mcpu=cortex-m0plus -mthumb-interwork +LFLAGS += -mfloat-abi=soft --disable-newlib-supplied-syscalls -nostartfiles +LFLAGS += -Tstartup/stm32l052x8xx.ld -Wl,-Map=$(mapfile).map -Wl,--gc-sections -g -Wl,--print-memory-usage + +CFLAGS = -c -fmessage-length=0 -mlittle-endian -mthumb -mcpu=cortex-m0plus -mthumb-interwork +CFLAGS += -mfloat-abi=soft -nostartfiles -Wall -g -O0 + +#################################################################################### + +OBJ = $(CFILES:%.c=$(OBJDIR)/%.c.o) +ASOBJ = $(ASFILES:%.S=$(OBJDIR)/%.S.o) + +default: $(target).elf + +binary: $(target).bin $(target).hex + +%.bin: %.elf + $(OBJCOPY) -O binary $^ $@ +%.hex: %.elf + $(OBJCOPY) -O ihex $^ $@ + +#Linking +$(target).elf: $(OBJ) $(ASOBJ) + @echo Linking $@ + $(QUIET)$(CC) $(LFLAGS) $(LIBRARYPATH) -o $@ $^ $(LIBRARIES) + $(QUIET)$(SIZE) $@ + +#Compiling +$(OBJ): + @echo Compiling $@ + $(eval OUTPATH=$(dir $@)) + @mkdir -p $(OUTPATH) + $(QUIET)$(CC) $(CFLAGS) -MMD -MT $@ $(INCLUDEPATH) $(DEFINES) -o $@ $(@:$(OBJDIR)/%.c.o=%.c) + +$(ASOBJ): + @echo Compiling $@ + $(eval OUTPATH=$(dir $@)) + @mkdir -p $(OUTPATH) + $(QUIET)$(CC) $(CFLAGS) -MMD -MT $@ $(INCLUDEPATH) $(DEFINES) -o $@ $(@:$(OBJDIR)/%.S.o=%.S) + +.PHONY: qtproject clean mrproper objcopy disassemble + +disassemble: $(target).elf + $(OBJDUMP) -D -s $< > $(target).lss + +objcopy: $(target).bin $(target).hex + +mrproper: + rm -f $(target).pro + +clean: + rm -f $(target).elf $(target).bin $(target).hex $(OBJ) $(ASOBJ) $(mapfile).map $(target).lss + rm -rfv $(OBJDIR) + +qtproject: + echo -e "TEMPLATE = app\nCONFIG -= console app_bundle qt" > $(target).pro + echo -e "SOURCES += $(CFILES) $(ASFILES)" >> $(target).pro + echo -ne "INCLUDEPATH += " >> $(target).pro + echo "$(INCLUDEPATH)" | sed "s!-I!./!g" >> $(target).pro + echo -ne "HEADERS += " >> $(target).pro + find -name "*.h" | tr "\\n" " " >> $(target).pro + echo -ne "\nDEFINES += " >> $(target).pro + echo "$(DEFINES)" | sed "s/-D//g" >> $(target).pro + +-include $(CFILES:%.c=$(OBJDIR)/%.c.d) $(ASFILES:%.S=$(OBJDIR)/%.S.d) + diff --git a/firmware/README.md b/firmware/README.md new file mode 100644 index 0000000..4bf020c --- /dev/null +++ b/firmware/README.md @@ -0,0 +1,2 @@ +# stm32l052x8xx-template + diff --git a/firmware/eeprom.c b/firmware/eeprom.c new file mode 100644 index 0000000..299edac --- /dev/null +++ b/firmware/eeprom.c @@ -0,0 +1,86 @@ +#include "eeprom.h" +#include + +/** + * @brief Defined in Linkerscript as the start of the EEPROM + */ +extern uint32_t __ld_seeprom; + +int data_eeprom_write_word(uint32_t word_addr_offset, uint32_t word) +{ + uint32_t *eeprom_base_addr = &__ld_seeprom; + + /* Unlock the NVM interface */ + FLASH->PEKEYR = 0x89ABCDEFUL; + FLASH->PEKEYR = 0x02030405UL; + + __DSB(); + + /* Check if we are unlocked */ + if (FLASH->PECR & FLASH_PECR_PELOCK) + return -1; + + FLASH->PECR &= ~(FLASH_PECR_PELOCK | FLASH_PECR_ERASE); + + eeprom_base_addr += word_addr_offset; + *eeprom_base_addr = word; + + /* Lock the flash interface again */ + FLASH->PECR |= FLASH_PECR_PELOCK; + + return 0; +} + +int data_eeprom_write(uint32_t byte_offset, const uint8_t *data, uint32_t len) +{ + char *eeprom_base_addr = (char *)&__ld_seeprom; + char *dest_ptr; + uint32_t *word_dest_ptr; + uint32_t full_words; + uint32_t remain_bytes; + + /* Unlock the NVM interface */ + FLASH->PEKEYR = 0x89ABCDEFUL; + FLASH->PEKEYR = 0x02030405UL; + + __DSB(); + + /* Check if we are unlocked */ + if (FLASH->PECR & FLASH_PECR_PELOCK) + return -1; + + FLASH->PECR &= ~(FLASH_PECR_PELOCK | FLASH_PECR_ERASE); + + dest_ptr = eeprom_base_addr + byte_offset; + + /* Do the first bytes */ + while ((uint32_t)dest_ptr & 0x3) { + *(dest_ptr++) = *(data++); + len -= 1; + } + + /* Do the remianing words */ + full_words = len / 4; + remain_bytes = len % 4; + + while (full_words) { + word_dest_ptr = (uint32_t *)dest_ptr; + *word_dest_ptr = (((uint32_t)data[3]) << 24) | (((uint32_t)data[2]) << 16) | (((uint32_t)data[1]) << 8) | + (((uint32_t)data[0]) << 0); + dest_ptr += 4; + data += 4; + full_words--; + } + + while (remain_bytes) { + *dest_ptr = *data; + dest_ptr++; + data++; + remain_bytes--; + } + + /* Lock the flash interface again */ + FLASH->PECR |= FLASH_PECR_PELOCK; + + return 0; +} diff --git a/firmware/eeprom.h b/firmware/eeprom.h new file mode 100644 index 0000000..2c50135 --- /dev/null +++ b/firmware/eeprom.h @@ -0,0 +1,10 @@ +#ifndef _EEPROM_H_ +#define _EEPROM_H_ + +#include + +int data_eeprom_write_word(uint32_t word_addr_offset, uint32_t word); + +int data_eeprom_write(uint32_t byte_offset, const uint8_t *data, uint32_t len); + +#endif /* _EEPROM_H_ */ diff --git a/firmware/include/cmsis/cmsis_gcc.h b/firmware/include/cmsis/cmsis_gcc.h new file mode 100644 index 0000000..d868f2e --- /dev/null +++ b/firmware/include/cmsis/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/firmware/include/cmsis/core_cm0plus.h b/firmware/include/cmsis/core_cm0plus.h new file mode 100644 index 0000000..7614450 --- /dev/null +++ b/firmware/include/cmsis/core_cm0plus.h @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/include/cmsis/core_cmFunc.h b/firmware/include/cmsis/core_cmFunc.h new file mode 100644 index 0000000..ca319a5 --- /dev/null +++ b/firmware/include/cmsis/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/firmware/include/cmsis/core_cmInstr.h b/firmware/include/cmsis/core_cmInstr.h new file mode 100644 index 0000000..a0a5064 --- /dev/null +++ b/firmware/include/cmsis/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/firmware/include/stm32l052xx.h b/firmware/include/stm32l052xx.h new file mode 100644 index 0000000..d5bbc26 --- /dev/null +++ b/firmware/include/stm32l052xx.h @@ -0,0 +1,7342 @@ +/** + ****************************************************************************** + * @file stm32l052xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32l052xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l052xx + * @{ + */ + +#ifndef __STM32L052xx_H +#define __STM32L052xx_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32l052xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ + +/****** STM32L-0 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ + TIM21_IRQn = 20, /*!< TIM21 Interrupt */ + TIM22_IRQn = 22, /*!< TIM22 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ + USB_IRQn = 31, /*!< USB global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include +//#include "system_stm32l0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ + __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ + __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ + uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + + +/** +* @brief CRC calculation unit +*/ + +typedef struct +{ +__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ +__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ +uint8_t RESERVED0; /*!< Reserved, 0x05 */ +uint16_t RESERVED1; /*!< Reserved, 0x06 */ +__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +uint32_t RESERVED2; /*!< Reserved, 0x0C */ +__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ +__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ + +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + uint32_t RESERVED0[6]; /*!< 0x14-0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + uint32_t RESERVED1; /*!< 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ +} DMA_Request_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l0xx + * @{ + */ + +#ifndef __STM32L0xx_H +#define __STM32L0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32L0) +#define STM32L0 +#endif /* STM32L0 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && \ + !defined (STM32L011xx) && !defined (STM32L021xx) && \ + !defined (STM32L031xx) && !defined (STM32L041xx) && \ + !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \ + !defined (STM32L062xx) && !defined (STM32L063xx) && \ + !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \ + !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) + /* #define STM32L010x4 */ /*!< STM32L010K4, STM32L010F4 Devices */ + /* #define STM32L010x6 */ /*!< STM32L010C6 Devices */ + /* #define STM32L010x8 */ /*!< STM32L010K8, STM32L010R8 Devices */ + /* #define STM32L010xB */ /*!< STM32L010RB Devices */ + /* #define STM32L011xx */ /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */ + /* #define STM32L021xx */ /*!< STM32L021D4, STM32L021F4, STM32L021G4, STM32L021K4 Devices */ + /* #define STM32L031xx */ /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */ + /* #define STM32L041xx */ /*!< STM32L041C6, STM32L041K6, STM32L041G6, STM32L041F6, STM32L041E6 Devices */ + /* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8, STM32L051K6, STM32L051T6, STM32L051T8 Devices */ + /* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8, STM32L052T6, STM32L052T8 Devices */ + /* #define STM32L053xx */ /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */ + /* #define STM32L062xx */ /*!< STM32L062K8 Devices */ + /* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 Devices */ + /* #define STM32L071xx */ /*!< STM32L071V8, STM32L071K8, STM32L071VB, STM32L071RB, STM32L071CB, STM32L071KB, STM32L071VZ, STM32L071RZ, STM32L071CZ, STM32L071KZ, STM32L071C8 Devices */ + /* #define STM32L072xx */ /*!< STM32L072V8, STM32L072VB, STM32L072RB, STM32L072CB, STM32L072VZ, STM32L072RZ, STM32L072CZ, STM32L072KB, STM32L072KZ Devices */ + /* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ, STM32L073CB, STM32L073CZ Devices */ + /* #define STM32L081xx */ /*!< STM32L081CB, STM32L081CZ, STM32L081KZ Devices */ + /* #define STM32L082xx */ /*!< STM32L082KB, STM32L082KZ, STM32L082CZ Devices */ + /* #define STM32L083xx */ /*!< STM32L083V8, STM32L083VB, STM32L083RB, STM32L083VZ, STM32L083RZ, STM32L083CB, STM32L083CZ Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number + */ +#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x09) /*!< [23:16] sub1 version */ +#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\ + |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32L0xx_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ +#if defined(STM32L010xB) + #include "stm32l010xb.h" +#elif defined(STM32L010x8) + #include "stm32l010x8.h" +#elif defined(STM32L010x6) + #include "stm32l010x6.h" +#elif defined(STM32L010x4) + #include "stm32l010x4.h" +#elif defined(STM32L011xx) + #include "stm32l011xx.h" +#elif defined(STM32L021xx) + #include "stm32l021xx.h" +#elif defined(STM32L031xx) + #include "stm32l031xx.h" +#elif defined(STM32L041xx) + #include "stm32l041xx.h" +#elif defined(STM32L051xx) + #include "stm32l051xx.h" +#elif defined(STM32L052xx) + #include "stm32l052xx.h" +#elif defined(STM32L053xx) + #include "stm32l053xx.h" +#elif defined(STM32L062xx) + #include "stm32l062xx.h" +#elif defined(STM32L063xx) + #include "stm32l063xx.h" +#elif defined(STM32L071xx) + #include "stm32l071xx.h" +#elif defined(STM32L072xx) + #include "stm32l072xx.h" +#elif defined(STM32L073xx) + #include "stm32l073xx.h" +#elif defined(STM32L082xx) + #include "stm32l082xx.h" +#elif defined(STM32L083xx) + #include "stm32l083xx.h" +#elif defined(STM32L081xx) + #include "stm32l081xx.h" +#else + #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32l0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32L0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/firmware/macro_helpers.h b/firmware/macro_helpers.h new file mode 100644 index 0000000..9878931 --- /dev/null +++ b/firmware/macro_helpers.h @@ -0,0 +1,13 @@ +/** + * General Macro Helpers + * + * Kevin Cuzner + */ + +#ifndef _MACRO_HELPERS_H_ +#define _MACRO_HELPERS_H_ + +#define NUMARGS(...) (sizeof((int[]){__VA_ARGS__})/sizeof(int)) + +#endif //_MACRO_HELPERS_H_ + diff --git a/firmware/main.c b/firmware/main.c new file mode 100644 index 0000000..bdbe457 --- /dev/null +++ b/firmware/main.c @@ -0,0 +1,506 @@ +#include +#include +#include +#include "usb.h" +#include "unique-id.h" +#include "eeprom.h" +#include + +volatile unsigned int i = 0x12345678; +unsigned char c = 2; +unsigned int my_static_var; + +volatile uint32_t tick = 0; + +uint8_t ep0_buff[64]; + +uint8_t dev_descriptor[] = { + 18, // bLength + 1, // bDescriptorType + 0x00, 0x02, // bcdUSB + 0x00, // bDeviceClass = Use info in interface descriptor + 0x00, // bDeviceSubClass = Use info in interface + 0x00, // bDeviceProtocol = Use info in interface + 64, // bMaxPacketSize0 + 0xAD, 0xDE, // idVendor + 0xEF, 0xBE, // idProduct + 0x00, 0x01, // bcdDevice + 1, // iManufacturer + 2, // iProduct + 3, // iSerialNumber + 1 // bNumConfigurations +}; + + +/* See: https://github.com/anszom/avr-vusb-keyboard/blob/master/sw/hid_descriptor.h */ +const uint8_t hid_report_descriptor[] = { + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x06, // USAGE (Keyboard) + 0xa1, 0x01, // COLLECTION (Application) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + 0x19, 0xe0, // USAGE_MINIMUM (Keyboard LeftControl) + 0x29, 0xe7, // USAGE_MAXIMUM (Keyboard Right GUI) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x75, 0x01, // REPORT_SIZE (1) + 0x95, 0x08, // REPORT_COUNT (8) + 0x81, 0x02, // INPUT (Data,Var,Abs) //1 byte + + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0x81, 0x03, // INPUT (Cnst,Var,Abs) //1 byte + + 0x95, 0x06, // REPORT_COUNT (6) + 0x75, 0x08, // REPORT_SIZE (8) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x65, // LOGICAL_MAXIMUM (101) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated)) + 0x29, 0x65, // USAGE_MAXIMUM (Keyboard Application) + 0x81, 0x00, // INPUT (Data,Ary,Abs) //6 bytes + + 0xc0 // END_COLLECTION +}; + +struct hid_report { + uint8_t modifier; + uint8_t reserved; + uint8_t keycodes[6]; +}; + +const uint8_t config_desc[34] = { + 9, /* bLenght */ + 2, /* bDescriptorType */ + 34, 0, /* wTotalLength */ + 1, /* bNumInterfaces */ + 1, /* bConfigurationValue */ + 0, /* iConfiguration */ + 0x80, /* bmAttributes */ + 50, /* bMaxPower */ + /* Interface Descriptor */ + 0x09, /* Length = 9 */ + 0x04, /* Type = Interface Descriptor */ + 0x00, /* Interface Number */ + 0x00, /* bAlternateSetting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass (3 = HID) */ + 0x00, /* bInterfaceSubClass */ + 0x00, /* bInterfaceProtocol */ + 0x00, /* iInterface */ + /* Endpoint Descriptor: EP1 Interrupt IN */ + 0x07, /* bLength */ + 0x05, /* bDescriptorType (5 = endpoint) */ + 0x81, /* bEndpointAddress */ + 0x03, /* bmAttributes (3 = Interrupt transfer */ + 64, 0x00, /* MaxPacketSize */ + 10, /* bInterval */ + + /* HID Descriptor */ + 9, /* bLength */ + 0x21, /* Descriptor Type: 0x21 = HID */ + 0x11, 0x01, /* BCD HID */ + 0x00, /* bCountryCode */ + 1, /* bNumDescriptors */ + 0x22, /* bDescriptorType 0x22=report */ + sizeof(hid_report_descriptor), 0x00 +}; + +const uint8_t lang_zero_desc[4] = { + 4, /* bLength */ + 3, /* Descriptor Type = string */ + 0x09, 0x04 /* Language ID = English (US) */ +}; + +const uint8_t manufacturer_string_desc[] = +{ + 2 + 8 * 2, /* Length */ + 3, /* Type = String descriptor */ + 'S', 0x00, + 'h', 0x00, + 'i', 0x00, + 'm', 0x00, + 'a', 0x00, + 't', 0x00, + 't', 0x00, + 'a', 0x00, +}; + +const uint8_t product_string_desc[] = +{ + 2 + 22 * 2, /* Length */ + 3, /* Type = String descriptor */ + 'S', 0x00, + 'u', 0x00, + 's', 0x00, + 't', 0x00, + 'a', 0x00, + 'i', 0x00, + 'n', 0x00, + ' ', 0x00, + 'P', 0x00, + 'e', 0x00, + 'd', 0x00, + 'a', 0x00, + 'l', 0x00, + ' ', 0x00, + 'K', 0x00, + 'e', 0x00, + 'y', 0x00, + 'b', 0x00, + 'o', 0x00, + 'a', 0x00, + 'r', 0x00, + 'd', 0x00, +}; + +uint8_t serial_string_desc[25 * 2 + 10]; + +struct usb_descriptor_entry desc_table[] = { +{0x0000, 0x0100, dev_descriptor, sizeof(dev_descriptor)}, +{0x0000, 0x0200, config_desc, sizeof(config_desc)}, +{0x0000, 0x0300, lang_zero_desc, sizeof(lang_zero_desc)}, +{0x0409, 0x0301, manufacturer_string_desc, sizeof(manufacturer_string_desc)}, +{0x0409, 0x0302, product_string_desc, sizeof(product_string_desc)}, +{0x0409, 0x0303, serial_string_desc, sizeof(serial_string_desc)}, +{0x0000, 0x2200, hid_report_descriptor, sizeof(hid_report_descriptor)}, +{0x0001, 0x2200, hid_report_descriptor, sizeof(hid_report_descriptor)}, +/* sentinel */ +{0x00, 0x0, NULL, 0}, +}; + +static void wait_for_ticks(uint32_t ticks) +{ + tick = 0; + while (tick < ticks); +} + +static void uint_to_hex(uint64_t num, uint8_t hex_digits, char *out) +{ + int pos; + int string_idx; + uint64_t mask; + + if (!out || !hex_digits) + return; + + if (hex_digits > 16) + return; + + for (pos = hex_digits - 1, string_idx = 0; pos >= 0; pos--, string_idx++) { + mask = num & ((uint64_t)0xFULL << (pos * 4)); + mask >>= pos * 4; + + if (mask <= 0x9) { + out[string_idx] = 0x30 + (char)mask; + } else if (mask > 0x9) { + out[string_idx] = 0x37 + mask; + } + } + +} + +static void create_sn_from_unique_id(void) +{ + uint64_t lot; + uint32_t uid; + char id_string[25]; + int i; + int j; + + struct usb_descriptor_entry *desc_entry; + + unique_id_get(&lot, &uid); + uint_to_hex(lot, 16, id_string); + id_string[16] = ':'; + uint_to_hex(uid, 8, &id_string[17]); + + for (i = 0; desc_table[i].descriptor; i++) { + desc_entry = &desc_table[i]; + if (desc_entry->descriptor == serial_string_desc) { + for (j = 0; j < 25; j++) { + serial_string_desc[2 * j + 2] = id_string[j]; + serial_string_desc[2 * j + 1 + 2] = 0x00; + } + desc_entry->size = 25 * 2 + 2; + serial_string_desc[0] = 25 * 2 + 2; + serial_string_desc[1] = 3; + break; + } + } +} + +bool expect_report; +bool expect_eeprom_data; +uint16_t eep_offset; +uint16_t eep_len; + +static void ep_rx_data_callback(uint8_t endpoint, const uint8_t *buffer, uint32_t len) +{ + if (endpoint == 0) { + if (expect_report) { + usb_endpoint_send_status_stage(0); + } else if (expect_eeprom_data) { + if (len > eep_len) { + usb_endpoint_stall(0, true, true); + } else { + data_eeprom_write(eep_offset, buffer, len); + eep_len -= len; + eep_offset += len; + if (eep_len == 0) { + usb_endpoint_send_status_stage(0); + } + } + + } + } + return; +} + + +static void append_pedal_keycodes_to_report(struct hid_report *r, uint32_t word) +{ + int i, j; + uint8_t keycode; + + if (word & 0xFF) { + r->modifier |= word & 0xFF; + } + + for (i = 0; i < 3; i++) { + word >>= 8; + keycode = word & 0xFF; + if (!keycode) + continue; + for (j = 0; j < 6; j++) { + if (r->keycodes[j] == 0) { + r->keycodes[j] = keycode; + break; + } + } + } +} + +static void build_report(struct hid_report *r) +{ + uint32_t idr; + const uint32_t *pedal1_word = (const uint32_t *)0x08080000UL; + const uint32_t *pedal2_word = (const uint32_t *)0x08080004UL; + + idr = GPIOB->IDR; + + memset(r, 0, sizeof(struct hid_report)); + + if (!(idr & (1<<7))) { + append_pedal_keycodes_to_report(r, *pedal1_word); + } + + if (!(idr & (1<<6))) { + append_pedal_keycodes_to_report(r, *pedal2_word); + } +} + +static uint16_t idle; + +static enum control_state ep_rx_setup_received_callback(uint8_t endpoint, const struct setup_packet *setup_pkg) +{ + enum control_state ret_state = CONTROL_NOT_HANDLED; + static struct hid_report r; + + expect_report = false; + expect_eeprom_data = false; + eep_len = 0; + eep_offset = 0; + + if (endpoint != 0) { + return ret_state; + } + + + if (setup_pkg->bm_req_type & 0x80) { + /* Device to host transfer */ + if ((setup_pkg->bm_req_type & 0xE0) == 0x20) { + /* Class transfer */ + switch (setup_pkg->b_request) { + case 0x01: + /* Get report */ + build_report(&r); + usb_endpoint_send(0, (uint8_t *)&r, sizeof(r)); + ret_state = CONTROL_DATA_TX; + break; + case 0x02: + /* Get idle */ + usb_endpoint_send(0, (uint8_t *)&idle, 2); + break; + } + } else if (setup_pkg->bm_req_type & (1<<6)) { + switch (setup_pkg->b_request) { + case 0x2: + usb_endpoint_send(0, (uint8_t *)0x08080000, setup_pkg->w_length); + ret_state = CONTROL_DATA_TX; + break; + } + } + } else { + /* Host to device transfer */ + if ((setup_pkg->bm_req_type & 0xE0) == 0x20) { + /* Class transfer */ + switch (setup_pkg->b_request) { + case 0xA: + /* Set idle */ + idle = setup_pkg->w_value; + ret_state = CONTROL_STATUS_TX; + break; + case 0x09: + /* Set report */ + expect_report = true; + usb_endpoint_prepare_receive(0, ep0_buff, sizeof(ep0_buff)); + ret_state = CONTROL_DATA_RX; + break; + default: + break; + } + } else if (setup_pkg->bm_req_type == 0x1 && setup_pkg->b_request == 11) { + /* Set interface */ + /* Nothing to do. Just ack it */ + ret_state = CONTROL_STATUS_TX; + } else if (setup_pkg->bm_req_type == (1<<6)) { + /* Vendor Access */ + switch (setup_pkg->b_request) { + case 0x1: + if (setup_pkg->w_value) + GPIOA->ODR |= (1<w_index); + else + GPIOA->ODR &= ~(1<w_index); + ret_state = CONTROL_STATUS_TX; + break; + case 0x2: + expect_eeprom_data = true; + eep_len = setup_pkg->w_length; + eep_offset = setup_pkg->w_index; + usb_endpoint_prepare_receive(0, ep0_buff, sizeof(ep0_buff)); + ret_state = CONTROL_DATA_RX; + break; + default: + break; + } + } + } + + return ret_state; +} + +static volatile bool ep1_tx_pending; + +static void ep_tx_complete_callback(uint8_t endpoint) +{ + if (endpoint == 1) { + ep1_tx_pending = false; + } else if (endpoint == 0) { + + } +} + +static void usb_sof_callback(void) +{ + +} + +static volatile bool configured = false; + +static void usb_reset_callback(void) +{ + configured = false; +} + + + +static void usb_configured_callback(uint16_t config_idx) +{ + GPIOA->ODR &= ~0xF; + usb_endpoint_config(EP_INTERRUPT, 1, false, true); + configured = true; +} + + +const struct usb_callbacks my_callbacks = { + .ep_rx_data_callback = ep_rx_data_callback, + .ep_rx_setup_received_callback = ep_rx_setup_received_callback, + .ep_tx_complete_callback = ep_tx_complete_callback, + .usb_configured_callback = usb_configured_callback, + .usb_reset_callback = usb_reset_callback, + .usb_sof_callback = usb_sof_callback, +}; + +static void patch_vid_pid() +{ + const uint32_t * const vid_pid_ptr = (const uint32_t *)0x08080008; + const uint32_t vid_pid_word = *vid_pid_ptr; + uint16_t vid; + uint16_t pid; + + vid = (vid_pid_word >> 16) & 0xFFFFU; + pid = vid_pid_word & 0xFFFF; + + if (vid != 0U && pid != 0U) { + dev_descriptor[8] = (uint8_t)(vid & 0xFF); + dev_descriptor[9] = (uint8_t)((vid >> 8) & 0xFF); + dev_descriptor[10] = (uint8_t)(pid & 0xFF); + dev_descriptor[11] = (uint8_t)((pid >> 8) & 0xFF); + } +} + +int main(void) +{ + bool status_changed = false; + struct hid_report report; + struct hid_report report_send_buff; + + RCC->IOPENR |= RCC_IOPENR_IOPAEN; + GPIOA->MODER &= ~(3<<(0*2)) & ~(3<<(1*2)) & ~(3<<(2*2)) & ~(3<<(3*2)); + GPIOA->MODER |= (1<<(0*2)) | (1<<(1*2)) | (1<<(2*2)) | (1<<(3*2)); + GPIOA->ODR |= (1<<0); + SysTick_Config(3200000); + //setup_usb_clock(); + __enable_irq(); + + create_sn_from_unique_id(); + patch_vid_pid(); + + usb_init(&my_callbacks); + wait_for_ticks(2); + usb_enable(desc_table); + + NVIC_SetPriority(SysTick_IRQn, 0); + NVIC_SetPriority(USB_IRQn, 1); + + + RCC->IOPENR |= RCC_IOPENR_GPIOBEN; + GPIOB->MODER &= ~((0x3<<(6*2)) | (0x3<<(7*2))); + GPIOB->PUPDR |= (1<<(6*2)) | (1<<(7*2)); + + + while (1) { + + while (!configured) { + ep1_tx_pending = false; + } + + build_report(&report); + + if (memcmp(&report, &report_send_buff, sizeof(struct hid_report))) + status_changed = true; + + if (status_changed && !ep1_tx_pending) { + memcpy(&report_send_buff, &report, sizeof(struct hid_report)); + ep1_tx_pending = true; + status_changed = false; + usb_endpoint_send(1, (uint8_t *)&report_send_buff, sizeof(struct hid_report)); + } + + } +} + +void SysTick_Handler(void) +{ + tick++; +} diff --git a/firmware/setup/system_init.c b/firmware/setup/system_init.c new file mode 100644 index 0000000..690888b --- /dev/null +++ b/firmware/setup/system_init.c @@ -0,0 +1,74 @@ +/* +* STM32L052x8 System Setup Code +* +* This file is part of 'STM32L052' code template'. +* +* It is free software: you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation, version 2 of the License. +* +* This code is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this template. If not, see . +* ------------------------------------------------------------------------ +*/ + +#include +#include + +/** + * @brief Init for 32 MHz clock + */ +static void __init_default_clocks(void) +{ + uint32_t tmp; + + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Set Flash Waitstate */ + FLASH->ACR |= FLASH_ACR_LATENCY; + + /* Configure interal voltage regualtor to range 1 (1.8V) */ + PWR->CR = PWR_CR_VOS_0; + + /* Enable MSI osc as main source for now to ensure we're running stable */ + tmp = RCC->CFGR; + tmp &= ~0x3; + RCC->CFGR = tmp; + + /* Enable HSI */ + RCC->CR |= RCC_CR_HSION; + + /* Wait for HSI to be ready */ + while (!(RCC->CR & RCC_CR_HSIRDY)); + + /* Disable PLL */ + RCC->CR &= ~RCC_CR_PLLON; + while (RCC->CR & RCC_CR_PLLRDY); + + /* Reset PLL and clock div config etc. */ + RCC->CFGR = 0; + + /* Configure PLL for HSI input and 32 MHz output + * PLLDIV = 2 + * PLLMUL = x4 + */ + RCC->CFGR |= RCC_CFGR_PLLDIV_0 | RCC_CFGR_PLLMUL_0; + + /* Startup PLL */ + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)); + + /* Switch over to PLL clock. Prescalers for buses are finde with div by 1 for 32 MHz */ + RCC->CFGR |= RCC_CFGR_SW_0 | RCC_CFGR_SW_1; +} + + +void __system_init(void) +{ + __init_default_clocks(); +} diff --git a/firmware/startup/startup_stm32l052x8xx.c b/firmware/startup/startup_stm32l052x8xx.c new file mode 100644 index 0000000..76df9eb --- /dev/null +++ b/firmware/startup/startup_stm32l052x8xx.c @@ -0,0 +1,199 @@ +/* +* STM32L052x8 Startup code +* +* This file is part of 'STM32L052' code template'. +* +* It is free software: you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation, version 2 of the License. +* +* This code is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this template. If not, see . +* ------------------------------------------------------------------------ +*/ + +/* C++ library init */ +# if defined(__cplusplus) +extern "C" { + extern void __libc_init_array(void); +} +#endif + +/* Defines for weak default handlers */ +#define WEAK __attribute__((weak)) +#define ALIAS(func) __attribute__ ((weak, alias (#func))) + +/* Define for section mapping */ +#define SECTION(sec) __attribute__((section(sec))) + +/* Handler prototypes */ +#if defined(_cplusplus) +extern "C" { +#endif + + +/* Interrupt Default handler */ +WEAK void __int_default_handler(void); + +/* Core Interrupts */ +void Reset_Handler(void); +void NMI_Handler(void) ALIAS(__int_default_handler); +void HardFault_Handler(void) ALIAS(__int_default_handler); +void SVCall_Handler(void) ALIAS(__int_default_handler); +void PendSV_Handler(void) ALIAS(__int_default_handler); +void SysTick_Handler(void) ALIAS(__int_default_handler); + +/* Peripheral Interrupts (by default mapped onto Default Handler) */ +void WWDG_IRQHandler(void) ALIAS(__int_default_handler); +void PVD_IRQHandler(void) ALIAS(__int_default_handler); +void RTC_IRQHandler(void) ALIAS(__int_default_handler); +void FLASH_IRQHandler(void) ALIAS(__int_default_handler); +void RCC_CRS_IRQHandler(void) ALIAS(__int_default_handler); +void EXTI0_1_IRQHandler(void) ALIAS(__int_default_handler); +void EXTI2_3_IRQHandler(void) ALIAS(__int_default_handler); +void EXTI4_15_IRQHandler(void) ALIAS(__int_default_handler); +void TSC_IRQHandler(void) ALIAS(__int_default_handler); +void DMA1_CH1_IRQHandler(void) ALIAS(__int_default_handler); +void DMA1_CH2_3_IRQHandler(void) ALIAS(__int_default_handler); +void DMA1_CH4_5_6_7_IRQHandler(void) ALIAS(__int_default_handler); +void ADC_COMP_IRQHandler(void) ALIAS(__int_default_handler); +void LPTIM1_IRQHandler(void) ALIAS(__int_default_handler); +void USART4_5_IRQHandler(void) ALIAS(__int_default_handler); +void TIM2_IRQHandler(void) ALIAS(__int_default_handler); +void TIM3_IRQHandler(void) ALIAS(__int_default_handler); +void TIM6_DAC_IRQHandler(void) ALIAS(__int_default_handler); +void TIM7_IRQHandler(void) ALIAS(__int_default_handler); +void TIM21_IRQHandler(void) ALIAS(__int_default_handler); +void I2C3_IRQHandler(void) ALIAS(__int_default_handler); +void TIM22_IRQHandler(void) ALIAS(__int_default_handler); +void I2C1_IRQHandler(void) ALIAS(__int_default_handler); +void I2C2_IRQHandler(void) ALIAS(__int_default_handler); +void SPI1_IRQHandler(void) ALIAS(__int_default_handler); +void SPI2_IRQHandler(void) ALIAS(__int_default_handler); +void USART1_IRQHandler(void) ALIAS(__int_default_handler); +void USART2_IRQHandler(void) ALIAS(__int_default_handler); +void LPUART1_AES_RNG_IRQHandler(void) ALIAS(__int_default_handler); +void USB_IRQHandler(void) ALIAS(__int_default_handler); + +extern int main(void); +extern void __system_init(void); + +extern void __ld_top_of_stack(void); +#if defined(_cplusplus) +extern "C" } +#endif + +void (* const vector_table[])(void) SECTION(".vectors") = { + &__ld_top_of_stack, + /* Core Interrupts */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SVCall_Handler, + 0, + 0, + PendSV_Handler, + SysTick_Handler, + /* Peripheral Interrupts */ + WWDG_IRQHandler, + PVD_IRQHandler, + RTC_IRQHandler, + FLASH_IRQHandler, + RCC_CRS_IRQHandler, + EXTI0_1_IRQHandler, + EXTI2_3_IRQHandler, + EXTI4_15_IRQHandler, + TSC_IRQHandler, + DMA1_CH1_IRQHandler, + DMA1_CH2_3_IRQHandler, + DMA1_CH4_5_6_7_IRQHandler, + ADC_COMP_IRQHandler, + LPTIM1_IRQHandler, + USART4_5_IRQHandler, + TIM2_IRQHandler, + TIM3_IRQHandler, + TIM6_DAC_IRQHandler, + TIM7_IRQHandler, + 0, + TIM21_IRQHandler, + I2C3_IRQHandler, + TIM22_IRQHandler, + I2C1_IRQHandler, + I2C2_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + USART1_IRQHandler, + USART2_IRQHandler, + LPUART1_AES_RNG_IRQHandler, + 0, + USB_IRQHandler, +}; + +static void __init_section(unsigned int *src_start, unsigned int *dest_start, unsigned int *dest_end) { + unsigned int *get, *put; + + put = dest_start; + get = src_start; + + while ((unsigned int)put < (unsigned int)dest_end) { + *(put++) = *(get++); + } +} + +static void __fill_zero(unsigned int *start, unsigned int *end) { + while ((unsigned int) start < (unsigned int)end) { + *(start++) = 0x00000000; + } +} + +extern unsigned int __ld_load_data; +extern unsigned int __ld_sitcm; +extern unsigned int __ld_eitcm; +extern unsigned int __ld_sdtcm; +extern unsigned int __ld_edtcm; +extern unsigned int __ld_sdata; +extern unsigned int __ld_edata; +extern unsigned int __ld_sbss; +extern unsigned int __ld_ebss; +extern unsigned int __ld_sheap; +extern unsigned int __ld_eheap; + +void Reset_Handler(void) { + /* Stack is already initilized by hardware */ + + /* Copy .data section */ + __init_section(&__ld_load_data, &__ld_sdata, &__ld_edata); + /* Fill bss with zero */ + __fill_zero(&__ld_sbss, &__ld_ebss); + /* Fill Heap with zero */ + __fill_zero(&__ld_sheap, &__ld_eheap); + /* Set clocks, waitstates, ART operation etc. */ + __system_init(); + + /* C++ init function */ +#if defined(__cplusplus) + __libc_init_array(); +#endif + /* Call main */ + main(); + + /* Catch return from main() */ + while(1); +} + +WEAK void __int_default_handler(void) +{ + while(1); +} diff --git a/firmware/startup/stm32l052x8xx.ld b/firmware/startup/stm32l052x8xx.ld new file mode 100644 index 0000000..a5fac68 --- /dev/null +++ b/firmware/startup/stm32l052x8xx.ld @@ -0,0 +1,142 @@ +/* +* STM32L052x8 Linkerscript +* +* This file is part of 'STM32L052' code template'. +* +* It is free software: you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation, version 2 of the License. +* +* This code is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this template. If not, see . +* ------------------------------------------------------------------------ +* +* Flash Size: 64kB +* RAM Size: 8kB +*/ + +/* USER PARAMETERS */ +__ld_stack_size = 0x0400; +__ld_heap_size = 0x0200; + +/* END OF USER PARAMETERS */ +ENTRY(Reset_Handler) +__ld_top_of_stack = 0x20001000; /* One byte above the end of the SRAM. Stack is pre-decrewmenting, so this is okay */ + + +/* Available memory areas */ +MEMORY +{ + FLASH (xr) : ORIGIN = 0x08000000, LENGTH = 64K + EEPROM (r) : ORIGIN = 0x08080000, LENGTH = 2K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K +} + +SECTIONS +{ + .vectors : ALIGN(4) + { + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .text : ALIGN(4) + { + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP(*(.init)) /* Constructors */ + KEEP(*(.fini)) /* Destructors */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : ALIGN(4) + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + /* Constructor/Destructor tables */ + .preinit_array : ALIGN(4) + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : ALIGN(4) + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : ALIGN(4) + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + .eeprom (NOLOAD) : ALIGN(4) + { + __ld_seeprom = .; + *(.eepdata) + *(.eepdata*) + + } >EEPROM + + /* Initialized Data */ + __ld_load_data = LOADADDR(.data); + .data : ALIGN(4) + { + __ld_sdata = .; + *(.data) + *(.data*) + . = ALIGN(4); + __ld_edata = .; + } >RAM AT> FLASH + + /* Uninitialized static data */ + .bss : ALIGN(4) + { + __ld_sbss = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __ld_ebss = .; + } >RAM + + .heap_stack (NOLOAD) : ALIGN(4) + { + __ld_sheap = .; + . = . + __ld_heap_size; + __ld_eheap = .; + . = . + __ld_stack_size; + . = ALIGN(4); + } >RAM +} + diff --git a/firmware/svd/STM32L0x1.svd b/firmware/svd/STM32L0x1.svd new file mode 100644 index 0000000..360fdb2 --- /dev/null +++ b/firmware/svd/STM32L0x1.svd @@ -0,0 +1,16671 @@ + + + STM32L0x1 + 1.3 + STM32L0x1 + + + CM0+ + r0p0 + little + false + false + 3 + false + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + AES + Advanced encryption standard hardware + accelerator + AES + 0x40026000 + + 0x0 + 0x400 + registers + + + AES_RNG_LPUART1 + AES global interrupt RNG global interrupt and + LPUART1 global interrupt through + 29 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAOUTEN + Enable DMA management of data output + phase + 12 + 1 + + + DMAINEN + Enable DMA management of data input + phase + 11 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + CCFIE + CCF flag interrupt enable + 9 + 1 + + + ERRC + Error clear + 8 + 1 + + + CCFC + Computation Complete Flag + Clear + 7 + 1 + + + CHMOD + AES chaining mode + 5 + 2 + + + MODE + AES operating mode + 3 + 2 + + + DATATYPE + Data type selection (for data in and + data out to/from the cryptographic + block) + 1 + 2 + + + EN + AES enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + WRERR + Write error flag + 2 + 1 + + + RDERR + Read error flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + DINR + DINR + data input register + 0x8 + 0x20 + read-write + 0x00000000 + + + AES_DINR + Data Input Register. + 0 + 32 + + + + + DOUTR + DOUTR + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + AES_DOUTR + Data output register + 0 + 32 + + + + + KEYR0 + KEYR0 + key register 0 + 0x10 + 0x20 + read-write + 0x00000000 + + + AES_KEYR0 + Data Output Register (LSB key + [31:0]) + 0 + 32 + + + + + KEYR1 + KEYR1 + key register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + AES_KEYR1 + AES key register (key + [63:32]) + 0 + 32 + + + + + KEYR2 + KEYR2 + key register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + AES_KEYR2 + AES key register (key + [95:64]) + 0 + 32 + + + + + KEYR3 + KEYR3 + key register 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + AES_KEYR3 + AES key register (MSB key + [127:96]) + 0 + 32 + + + + + IVR0 + IVR0 + initialization vector register + 0 + 0x20 + 0x20 + read-write + 0x00000000 + + + AES_IVR0 + initialization vector register (LSB IVR + [31:0]) + 0 + 32 + + + + + IVR1 + IVR1 + initialization vector register + 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + AES_IVR1 + Initialization Vector Register (IVR + [63:32]) + 0 + 32 + + + + + IVR2 + IVR2 + initialization vector register + 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + AES_IVR2 + Initialization Vector Register (IVR + [95:64]) + 0 + 32 + + + + + IVR3 + IVR3 + initialization vector register + 3 + 0x2C + 0x20 + read-write + 0x00000000 + + + AES_IVR3 + Initialization Vector Register (MSB IVR + [127:96]) + 0 + 32 + + + + + + + DMA1 + Direct memory access controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 9 + + + DMA1_Channel2_3 + DMA1 Channel2 and 3 interrupts + 10 + + + DMA1_Channel4_7 + DMA1 Channel4 to 7 interrupts + 11 + + + + ISR + ISR + interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF7 + Channel x transfer error flag (x = 1 + ..7) + 27 + 1 + + + HTIF7 + Channel x half transfer flag (x = 1 + ..7) + 26 + 1 + + + TCIF7 + Channel x transfer complete flag (x = 1 + ..7) + 25 + 1 + + + GIF7 + Channel x global interrupt flag (x = 1 + ..7) + 24 + 1 + + + TEIF6 + Channel x transfer error flag (x = 1 + ..7) + 23 + 1 + + + HTIF6 + Channel x half transfer flag (x = 1 + ..7) + 22 + 1 + + + TCIF6 + Channel x transfer complete flag (x = 1 + ..7) + 21 + 1 + + + GIF6 + Channel x global interrupt flag (x = 1 + ..7) + 20 + 1 + + + TEIF5 + Channel x transfer error flag (x = 1 + ..7) + 19 + 1 + + + HTIF5 + Channel x half transfer flag (x = 1 + ..7) + 18 + 1 + + + TCIF5 + Channel x transfer complete flag (x = 1 + ..7) + 17 + 1 + + + GIF5 + Channel x global interrupt flag (x = 1 + ..7) + 16 + 1 + + + TEIF4 + Channel x transfer error flag (x = 1 + ..7) + 15 + 1 + + + HTIF4 + Channel x half transfer flag (x = 1 + ..7) + 14 + 1 + + + TCIF4 + Channel x transfer complete flag (x = 1 + ..7) + 13 + 1 + + + GIF4 + Channel x global interrupt flag (x = 1 + ..7) + 12 + 1 + + + TEIF3 + Channel x transfer error flag (x = 1 + ..7) + 11 + 1 + + + HTIF3 + Channel x half transfer flag (x = 1 + ..7) + 10 + 1 + + + TCIF3 + Channel x transfer complete flag (x = 1 + ..7) + 9 + 1 + + + GIF3 + Channel x global interrupt flag (x = 1 + ..7) + 8 + 1 + + + TEIF2 + Channel x transfer error flag (x = 1 + ..7) + 7 + 1 + + + HTIF2 + Channel x half transfer flag (x = 1 + ..7) + 6 + 1 + + + TCIF2 + Channel x transfer complete flag (x = 1 + ..7) + 5 + 1 + + + GIF2 + Channel x global interrupt flag (x = 1 + ..7) + 4 + 1 + + + TEIF1 + Channel x transfer error flag (x = 1 + ..7) + 3 + 1 + + + HTIF1 + Channel x half transfer flag (x = 1 + ..7) + 2 + 1 + + + TCIF1 + Channel x transfer complete flag (x = 1 + ..7) + 1 + 1 + + + GIF1 + Channel x global interrupt flag (x = 1 + ..7) + 0 + 1 + + + + + IFCR + IFCR + interrupt flag clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + CTEIF7 + Channel x transfer error clear (x = 1 + ..7) + 27 + 1 + + + CHTIF7 + Channel x half transfer clear (x = 1 + ..7) + 26 + 1 + + + CTCIF7 + Channel x transfer complete clear (x = 1 + ..7) + 25 + 1 + + + CGIF7 + Channel x global interrupt clear (x = 1 + ..7) + 24 + 1 + + + CTEIF6 + Channel x transfer error clear (x = 1 + ..7) + 23 + 1 + + + CHTIF6 + Channel x half transfer clear (x = 1 + ..7) + 22 + 1 + + + CTCIF6 + Channel x transfer complete clear (x = 1 + ..7) + 21 + 1 + + + CGIF6 + Channel x global interrupt clear (x = 1 + ..7) + 20 + 1 + + + CTEIF5 + Channel x transfer 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= + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x reset bit y (y = + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL7 + Alternate function selection for port x + pin y (y = 0..7) + 28 + 4 + + + AFSEL6 + Alternate function selection for port x + pin y (y = 0..7) + 24 + 4 + + + AFSEL5 + Alternate function selection for port x + pin y (y = 0..7) + 20 + 4 + + + AFSEL4 + Alternate function selection for port x + pin y (y = 0..7) + 16 + 4 + + + AFSEL3 + Alternate function selection for port x + pin y (y = 0..7) + 12 + 4 + + + AFSEL2 + Alternate function selection for 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GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x Reset bit y (y= 0 .. + 15) + 15 + 1 + + + BR14 + Port x Reset bit y (y= 0 .. + 15) + 14 + 1 + + + BR13 + Port x Reset bit y (y= 0 .. + 15) + 13 + 1 + + + BR12 + Port x Reset bit y (y= 0 .. + 15) + 12 + 1 + + + BR11 + Port x Reset bit y (y= 0 .. + 15) + 11 + 1 + + + BR10 + Port x Reset bit y (y= 0 .. + 15) + 10 + 1 + + + BR9 + Port x Reset bit y (y= 0 .. + 15) + 9 + 1 + + + BR8 + Port x Reset bit y (y= 0 .. + 15) + 8 + 1 + + + BR7 + Port x Reset bit y (y= 0 .. + 15) + 7 + 1 + + + BR6 + Port x Reset bit y (y= 0 .. + 15) + 6 + 1 + + + BR5 + Port x Reset bit y (y= 0 .. + 15) + 5 + 1 + + + BR4 + Port x Reset bit y (y= 0 .. + 15) + 4 + 1 + + + BR3 + Port x Reset bit y (y= 0 .. + 15) + 3 + 1 + + + BR2 + Port x Reset bit y (y= 0 .. + 15) + 2 + 1 + + + BR1 + Port x Reset bit y (y= 0 .. + 15) + 1 + 1 + + + BR0 + Port x Reset bit y (y= 0 .. + 15) + 0 + 1 + + + + + + + GPIOB + General-purpose I/Os + GPIO + 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0..15) + 4 + 2 + + + MODE1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODE0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEED15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEED14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEED13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEED12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEED11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEED10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEED9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEED8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEED7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEED6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEED5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEED4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEED3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEED2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEED1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEED0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID15 + Port input data bit (y = + 0..15) + 15 + 1 + + + ID14 + Port input data bit (y = + 0..15) + 14 + 1 + + + ID13 + Port input data bit (y = + 0..15) + 13 + 1 + + + ID12 + Port input data bit (y = + 0..15) + 12 + 1 + + + ID11 + Port input data bit (y = + 0..15) + 11 + 1 + + + ID10 + Port input data bit (y = + 0..15) + 10 + 1 + + + ID9 + Port input data bit (y = + 0..15) + 9 + 1 + + + ID8 + Port input data bit (y = + 0..15) + 8 + 1 + + + ID7 + Port input data bit (y = + 0..15) + 7 + 1 + + + ID6 + Port input data bit (y = + 0..15) + 6 + 1 + + + ID5 + Port input data bit (y = + 0..15) + 5 + 1 + + + ID4 + Port input data bit (y = + 0..15) + 4 + 1 + + + ID3 + Port input data bit (y = + 0..15) + 3 + 1 + + + ID2 + Port input data bit (y = + 0..15) + 2 + 1 + + + ID1 + Port input data bit (y = + 0..15) + 1 + 1 + + + ID0 + Port input data bit (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD15 + Port output data bit (y = + 0..15) + 15 + 1 + + + OD14 + Port output data bit (y = + 0..15) + 14 + 1 + + + OD13 + Port output data bit (y = + 0..15) + 13 + 1 + + + OD12 + Port output data bit (y = + 0..15) + 12 + 1 + + + OD11 + Port output data bit (y = + 0..15) + 11 + 1 + + + OD10 + Port output data bit (y = + 0..15) + 10 + 1 + + + OD9 + Port output data bit (y = + 0..15) + 9 + 1 + + + OD8 + Port output data bit (y = + 0..15) + 8 + 1 + + + OD7 + Port output data bit (y = + 0..15) + 7 + 1 + + + OD6 + Port output data bit (y = + 0..15) + 6 + 1 + + + OD5 + Port output data bit (y = + 0..15) + 5 + 1 + + + OD4 + Port output data bit (y = + 0..15) + 4 + 1 + + + OD3 + Port output data bit (y = + 0..15) + 3 + 1 + + + OD2 + Port output data bit (y = + 0..15) + 2 + 1 + + + OD1 + Port output data bit (y = + 0..15) + 1 + 1 + + + OD0 + Port output data bit (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x reset bit y (y = + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL7 + Alternate function selection for port x + pin y (y = 0..7) + 28 + 4 + + + AFSEL6 + Alternate function selection for port x + pin y (y = 0..7) + 24 + 4 + + + AFSEL5 + Alternate function selection for port x + pin y (y = 0..7) + 20 + 4 + + + AFSEL4 + Alternate function selection for port x + pin y (y = 0..7) + 16 + 4 + + + AFSEL3 + Alternate function selection for port x + pin y (y = 0..7) + 12 + 4 + + + AFSEL2 + Alternate function selection for port x + pin y (y = 0..7) + 8 + 4 + + + AFSEL1 + Alternate function selection for port x + pin y (y = 0..7) + 4 + 4 + + + AFSEL0 + Alternate function selection for port x + pin y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + Alternate function selection for port x + pin y (y = 8..15) + 28 + 4 + + + AFSEL14 + Alternate function selection for port x + pin y (y = 8..15) + 24 + 4 + + + AFSEL13 + Alternate function selection for port x + pin y (y = 8..15) + 20 + 4 + + + AFSEL12 + Alternate function selection for port x + pin y (y = 8..15) + 16 + 4 + + + AFSEL11 + Alternate function selection for port x + pin y (y = 8..15) + 12 + 4 + + + AFSEL10 + Alternate function selection for port x + pin y (y = 8..15) + 8 + 4 + + + AFSEL9 + Alternate function selection for port x + pin y (y = 8..15) + 4 + 4 + + + AFSEL8 + Alternate function selection for port x + pin y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x Reset bit y (y= 0 .. + 15) + 15 + 1 + + + BR14 + Port x Reset bit y (y= 0 .. + 15) + 14 + 1 + + + BR13 + Port x Reset bit y (y= 0 .. + 15) + 13 + 1 + + + BR12 + Port x Reset bit y (y= 0 .. + 15) + 12 + 1 + + + BR11 + Port x Reset bit y (y= 0 .. + 15) + 11 + 1 + + + BR10 + Port x Reset bit y (y= 0 .. + 15) + 10 + 1 + + + BR9 + Port x Reset bit y (y= 0 .. + 15) + 9 + 1 + + + BR8 + Port x Reset bit y (y= 0 .. + 15) + 8 + 1 + + + BR7 + Port x Reset bit y (y= 0 .. + 15) + 7 + 1 + + + BR6 + Port x Reset bit y (y= 0 .. + 15) + 6 + 1 + + + BR5 + Port x Reset bit y (y= 0 .. + 15) + 5 + 1 + + + BR4 + Port x Reset bit y (y= 0 .. + 15) + 4 + 1 + + + BR3 + Port x Reset bit y (y= 0 .. + 15) + 3 + 1 + + + BR2 + Port x Reset bit y (y= 0 .. + 15) + 2 + 1 + + + BR1 + Port x Reset bit y (y= 0 .. + 15) + 1 + 1 + + + BR0 + Port x Reset bit y (y= 0 .. + 15) + 0 + 1 + + + + + + + GPIOC + 0x50000800 + + + GPIOD + 0x50000C00 + + + GPIOH + 0x50001C00 + + + GPIOE + 0x50001000 + + + LPTIM + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + LPTIM1 + LPTIMER1 interrupt through + EXTI29 + 13 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt + Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value. + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value. + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value. + 0 + 16 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC global interrupt + 2 + + + + TR + TR + RTC time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + RTC date register + 0x4 + 0x20 + read-write + 0x00000000 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + CR + CR + RTC control register + 0x8 + 0x20 + 0x00000000 + + + COE + Calibration output enable + 23 + 1 + read-write + + + OSEL + Output selection + 21 + 2 + read-write + + + POL + Output polarity + 20 + 1 + read-write + + + COSEL + Calibration output + selection + 19 + 1 + read-write + + + BKP + Backup + 18 + 1 + read-write + + + SUB1H + Subtract 1 hour (winter time + change) + 17 + 1 + write-only + + + ADD1H + Add 1 hour (summer time + change) + 16 + 1 + write-only + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + read-write + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + read-write + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + TSE + timestamp enable + 11 + 1 + read-write + + + WUTE + Wakeup timer enable + 10 + 1 + read-write + + + ALRBE + Alarm B enable + 9 + 1 + read-write + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + FMT + Hour format + 6 + 1 + read-write + + + BYPSHAD + Bypass the shadow + registers + 5 + 1 + read-write + + + REFCKON + RTC_REFIN reference clock detection + enable (50 or 60 Hz) + 4 + 1 + read-write + + + TSEDGE + Time-stamp event active + edge + 3 + 1 + read-write + + + WUCKSEL + Wakeup clock selection + 0 + 3 + read-write + + + + + ISR + ISR + RTC initialization and status + register + 0xC + 0x20 + 0x00000000 + + + TAMP2F + RTC_TAMP2 detection flag + 14 + 1 + read-write + + + TAMP1F + RTC_TAMP1 detection flag + 13 + 1 + read-write + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + + + ALRBF + Alarm B flag + 9 + 1 + read-write + + + ALRAF + Alarm A flag + 8 + 1 + read-write + + + INIT + Initialization mode + 7 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + RSF + Registers synchronization + flag + 5 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + + + PRER + PRER + RTC prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler + factor + 0 + 16 + + + + + WUTR + WUTR + RTC wakeup timer register + 0x14 + 0x20 + read-write + 0x00000000 + + + WUT + Wakeup auto-reload value + bits + 0 + 16 + + + + + ALRMAR + ALRMAR + RTC alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format. + 28 + 2 + + + DU + Date units or day in BCD + format. + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format. + 20 + 2 + + + HU + Hour units in BCD format. + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format. + 4 + 3 + + + SU + Second units in BCD + format. + 0 + 4 + + + + + ALRMBR + ALRMBR + RTC alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + SSR + SSR + RTC sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + RTC shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + + + TSTR + TSTR + RTC timestamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format. + 20 + 2 + + + HU + Hour units in BCD format. + 16 + 4 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + ST + Second tens in BCD format. + 4 + 3 + + + SU + Second units in BCD + format. + 0 + 4 + + + + + TSDR + TSDR + RTC timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + RTC time-stamp sub second + register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + RTC calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 + ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle + period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle + period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAMPCR + TAMPCR + RTC tamper configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP2MF + Tamper 2 mask flag + 21 + 1 + + + TAMP2NOERASE + Tamper 2 no erase + 20 + 1 + + + TAMP2IE + Tamper 2 interrupt enable + 19 + 1 + + + TAMP1MF + Tamper 1 mask flag + 18 + 1 + + + TAMP1NOERASE + Tamper 1 no erase + 17 + 1 + + + TAMP1IE + Tamper 1 interrupt enable + 16 + 1 + + + TAMPPUDIS + RTC_TAMPx pull-up disable + 15 + 1 + + + TAMPPRCH + RTC_TAMPx precharge + duration + 13 + 2 + + + TAMPFLT + RTC_TAMPx filter count + 11 + 2 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TAMP2_TRG + Active level for RTC_TAMP2 + input + 4 + 1 + + + TAMP2E + RTC_TAMP2 input detection + enable + 3 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for RTC_TAMP1 + input + 1 + 1 + + + TAMP1E + RTC_TAMP1 input detection + enable + 0 + 1 + + + + + ALRMASSR + ALRMASSR + RTC alarm A sub second + register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBSSR + ALRMBSSR + RTC alarm B sub second + register + 0x48 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + OR + OR + option register + 0x4C + 0x20 + read-write + 0x00000000 + + + RTC_OUT_RMP + RTC_ALARM on PC13 output + type + 1 + 1 + + + RTC_ALARM_TYPE + RTC_ALARM on PC13 output + type + 0 + 1 + + + + + BKP0R + BKP0R + RTC backup registers + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + RTC backup registers + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + RTC backup registers + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + RTC backup registers + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + RTC backup registers + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 27 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt + enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt + enable + 26 + 1 + + + DEAT4 + Driver Enable assertion + time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion + time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush + request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x00C0 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear + flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear + flag + 8 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + + + USART2 + 0x40004400 + + + USART4 + 0x40004C00 + + USART4_USART5 + USART4/USART5 global interrupt + 14 + + + + USART5 + 0x40005000 + + USART2 + USART2 global interrupt + 28 + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read + 0x0000) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value + update + 2 + 1 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window + value + 0 + 12 + + + + + + + WWDG + System window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early wakeup interrupt + 9 + 1 + + + WDGTB1 + Timer base + 8 + 1 + + + WDGTB0 + WDGTB0 + 7 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + Firewall + Firewall + Firewall + 0x40011C00 + + 0x0 + 0x400 + registers + + + + FIREWALL_CSSA + FIREWALL_CSSA + Code segment start address + 0x0 + 0x20 + read-write + 0x00000000 + + + ADD + code segment start address + 8 + 16 + + + + + FIREWALL_CSL + FIREWALL_CSL + Code segment length + 0x4 + 0x20 + read-write + 0x00000000 + + + LENG + code segment length + 8 + 14 + + + + + FIREWALL_NVDSSA + FIREWALL_NVDSSA + Non-volatile data segment start + address + 0x8 + 0x20 + read-write + 0x00000000 + + + ADD + Non-volatile data segment start + address + 8 + 16 + + + + + FIREWALL_NVDSL + FIREWALL_NVDSL + Non-volatile data segment + length + 0xC + 0x20 + read-write + 0x00000000 + + + LENG + Non-volatile data segment + length + 8 + 14 + + + + + FIREWALL_VDSSA + FIREWALL_VDSSA + Volatile data segment start + address + 0x10 + 0x20 + read-write + 0x00000000 + + + ADD + Volatile data segment start + address + 6 + 10 + + + + + FIREWALL_VDSL + FIREWALL_VDSL + Volatile data segment length + 0x14 + 0x20 + read-write + 0x00000000 + + + LENG + Non-volatile data segment + length + 6 + 10 + + + + + FIREWALL_CR + FIREWALL_CR + Configuration register + 0x20 + 0x20 + read-write + 0x00000000 + + + VDE + Volatile data execution + 2 + 1 + + + VDS + Volatile data shared + 1 + 1 + + + FPA + Firewall pre alarm + 0 + 1 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 4 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000300 + + + PLLRDY + PLL clock ready flag + 25 + 1 + read-only + + + PLLON + PLL enable bit + 24 + 1 + read-write + + + RTCPRE + TC/LCD prescaler + 20 + 2 + read-write + + + CSSLSEON + Clock security system on HSE enable + bit + 19 + 1 + read-write + + + HSEBYP + HSE clock bypass bit + 18 + 1 + read-write + + + HSERDY + HSE clock ready flag + 17 + 1 + read-only + + + HSEON + HSE clock enable bit + 16 + 1 + read-write + + + MSIRDY + MSI clock ready flag + 9 + 1 + read-only + + + MSION + MSI clock enable bit + 8 + 1 + read-write + + + HSI16DIVF + HSI16DIVF + 4 + 1 + read-only + + + HSI16DIVEN + HSI16DIVEN + 3 + 1 + read-write + + + HSI16RDYF + Internal high-speed clock ready + flag + 2 + 1 + read-write + + + HSI16KERON + High-speed internal clock enable bit for + some IP kernels + 1 + 1 + read-only + + + HSI16ON + 16 MHz high-speed internal clock + enable + 0 + 1 + read-write + + + HSI16OUTEN + 16 MHz high-speed internal clock output + enable + 5 + 1 + read-write + + + + + ICSCR + ICSCR + Internal clock sources calibration + register + 0x4 + 0x20 + 0x0000B000 + + + MSITRIM + MSI clock trimming + 24 + 8 + read-write + + + MSICAL + MSI clock calibration + 16 + 8 + read-only + + + MSIRANGE + MSI clock ranges + 13 + 3 + read-write + + + HSI16TRIM + High speed internal clock + trimming + 8 + 5 + read-write + + + HSI16CAL + nternal high speed clock + calibration + 0 + 8 + read-only + + + + + CFGR + CFGR + Clock configuration register + 0xC + 0x20 + 0x00000000 + + + MCOPRE + Microcontroller clock output + prescaler + 28 + 3 + read-write + + + MCOSEL + Microcontroller clock output + selection + 24 + 3 + read-write + + + PLLDIV + PLL output division + 22 + 2 + read-write + + + PLLMUL + PLL multiplication factor + 18 + 4 + read-write + + + PLLSRC + PLL entry clock source + 16 + 1 + read-write + + + STOPWUCK + Wake-up from stop clock + selection + 15 + 1 + read-write + + + PPRE2 + APB high-speed prescaler + (APB2) + 11 + 3 + read-write + + + PPRE1 + APB low-speed prescaler + (APB1) + 8 + 3 + read-write + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + SWS + System clock switch status + 2 + 2 + read-only + + + SW + System clock switch + 0 + 2 + read-write + + + + + CIER + CIER + Clock interrupt enable + register + 0x10 + 0x20 + read-only + 0x00000000 + + + CSSLSE + LSE CSS interrupt flag + 7 + 1 + + + MSIRDYIE + MSI ready interrupt flag + 5 + 1 + + + PLLRDYIE + PLL ready interrupt flag + 4 + 1 + + + HSERDYIE + HSE ready interrupt flag + 3 + 1 + + + HSI16RDYIE + HSI16 ready interrupt flag + 2 + 1 + + + LSERDYIE + LSE ready interrupt flag + 1 + 1 + + + LSIRDYIE + LSI ready interrupt flag + 0 + 1 + + + + + CIFR + CIFR + Clock interrupt flag register + 0x14 + 0x20 + read-only + 0x00000000 + + + CSSHSEF + Clock Security System Interrupt + flag + 8 + 1 + + + CSSLSEF + LSE Clock Security System Interrupt + flag + 7 + 1 + + + MSIRDYF + MSI ready interrupt flag + 5 + 1 + + + PLLRDYF + PLL ready interrupt flag + 4 + 1 + + + HSERDYF + HSE ready interrupt flag + 3 + 1 + + + HSI16RDYF + HSI16 ready interrupt flag + 2 + 1 + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x18 + 0x20 + read-only + 0x00000000 + + + CSSHSEC + Clock Security System Interrupt + clear + 8 + 1 + + + CSSLSEC + LSE Clock Security System Interrupt + clear + 7 + 1 + + + MSIRDYC + MSI ready Interrupt clear + 5 + 1 + + + PLLRDYC + PLL ready Interrupt clear + 4 + 1 + + + HSERDYC + HSE ready Interrupt clear + 3 + 1 + + + HSI16RDYC + HSI16 ready Interrupt + clear + 2 + 1 + + + LSERDYC + LSE ready Interrupt clear + 1 + 1 + + + LSIRDYC + LSI ready Interrupt clear + 0 + 1 + + + + + IOPRSTR + IOPRSTR + GPIO reset register + 0x1C + 0x20 + read-write + 0x00000000 + + + IOPHRST + I/O port H reset + 7 + 1 + + + IOPDRST + I/O port D reset + 3 + 1 + + + IOPCRST + I/O port A reset + 2 + 1 + + + IOPBRST + I/O port B reset + 1 + 1 + + + IOPARST + I/O port A reset + 0 + 1 + + + IOPERST + I/O port E reset + 4 + 1 + + + + + AHBRSTR + AHBRSTR + AHB peripheral reset register + 0x20 + 0x20 + read-write + 0x00000000 + + + CRYPRST + Crypto module reset + 24 + 1 + + + CRCRST + Test integration module + reset + 12 + 1 + + + MIFRST + Memory interface reset + 8 + 1 + + + DMARST + DMA reset + 0 + 1 + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x24 + 0x20 + read-write + 0x000000000 + + + DBGRST + DBG reset + 22 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + ADCRST + ADC interface reset + 9 + 1 + + + TIM22RST + TIM22 timer reset + 5 + 1 + + + TIM21RST + TIM21 timer reset + 2 + 1 + + + SYSCFGRST + System configuration controller + reset + 0 + 1 + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + LPTIM1RST + Low power timer reset + 31 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + LPUART1RST + LPUART1 reset + 18 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + TIM6RST + Timer 6 reset + 4 + 1 + + + TIM2RST + Timer 2 reset + 0 + 1 + + + TIM3RST + Timer 3 reset + 1 + 1 + + + TIM7RST + Timer 7 reset + 5 + 1 + + + USART4RST + USART4 reset + 19 + 1 + + + USART5RST + USART5 reset + 20 + 1 + + + CRCRST + CRC reset + 27 + 1 + + + I2C3 + I2C3 reset + 30 + 1 + + + + + IOPENR + IOPENR + GPIO clock enable register + 0x2C + 0x20 + read-write + 0x00000000 + + + IOPHEN + I/O port H clock enable + bit + 7 + 1 + + + IOPDEN + I/O port D clock enable + bit + 3 + 1 + + + IOPCEN + IO port A clock enable bit + 2 + 1 + + + IOPBEN + IO port B clock enable bit + 1 + 1 + + + IOPAEN + IO port A clock enable bit + 0 + 1 + + + IOPEEN + IO port E clock enable bit + 4 + 1 + + + + + AHBENR + AHBENR + AHB peripheral clock enable + register + 0x30 + 0x20 + read-write + 0x00000100 + + + CRYPEN + Crypto clock enable bit + 24 + 1 + + + CRCEN + CRC clock enable bit + 12 + 1 + + + MIFEN + NVM interface clock enable + bit + 8 + 1 + + + DMAEN + DMA clock enable bit + 0 + 1 + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable + register + 0x34 + 0x20 + read-write + 0x00000000 + + + DBGEN + DBG clock enable bit + 22 + 1 + + + USART1EN + USART1 clock enable bit + 14 + 1 + + + SPI1EN + SPI1 clock enable bit + 12 + 1 + + + ADCEN + ADC clock enable bit + 9 + 1 + + + FWEN + Firewall clock enable bit + 7 + 1 + + + TIM22EN + TIM22 timer clock enable + bit + 5 + 1 + + + TIM21EN + TIM21 timer clock enable + bit + 2 + 1 + + + SYSCFGEN + System configuration controller clock + enable bit + 0 + 1 + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + LPTIM1EN + Low power timer clock enable + bit + 31 + 1 + + + PWREN + Power interface clock enable + bit + 28 + 1 + + + I2C2EN + I2C2 clock enable bit + 22 + 1 + + + I2C1EN + I2C1 clock enable bit + 21 + 1 + + + LPUART1EN + LPUART1 clock enable bit + 18 + 1 + + + USART2EN + UART2 clock enable bit + 17 + 1 + + + SPI2EN + SPI2 clock enable bit + 14 + 1 + + + WWDGEN + Window watchdog clock enable + bit + 11 + 1 + + + TIM6EN + Timer 6 clock enable bit + 4 + 1 + + + TIM2EN + Timer2 clock enable bit + 0 + 1 + + + TIM3EN + Timer 3 clock enbale bit + 2 + 1 + + + TIM7EN + Timer 7 clock enable bit + 5 + 1 + + + USART4EN + USART4 clock enable bit + 19 + 1 + + + USART5EN + USART5 clock enable bit + 20 + 1 + + + I2C3EN + I2C3 clock enable bit + 30 + 1 + + + + + IOPSMEN + IOPSMEN + GPIO clock enable in sleep mode + register + 0x3C + 0x20 + read-write + 0x0000008F + + + IOPHSMEN + Port H clock enable during Sleep mode + bit + 7 + 1 + + + IOPDSMEN + Port D clock enable during Sleep mode + bit + 3 + 1 + + + IOPCSMEN + Port C clock enable during Sleep mode + bit + 2 + 1 + + + IOPBSMEN + Port B clock enable during Sleep mode + bit + 1 + 1 + + + IOPASMEN + Port A clock enable during Sleep mode + bit + 0 + 1 + + + IOPESMEN + Port E clock enable during Sleep mode + bit + 4 + 1 + + + + + AHBSMENR + AHBSMENR + AHB peripheral clock enable in sleep mode + register + 0x40 + 0x20 + read-write + 0x01111301 + + + CRYPTSMEN + Crypto clock enable during sleep mode + bit + 24 + 1 + + + CRCSMEN + CRC clock enable during sleep mode + bit + 12 + 1 + + + SRAMSMEN + SRAM interface clock enable during sleep + mode bit + 9 + 1 + + + MIFSMEN + NVM interface clock enable during sleep + mode bit + 8 + 1 + + + DMASMEN + DMA clock enable during sleep mode + bit + 0 + 1 + + + + + APB2SMENR + APB2SMENR + APB2 peripheral clock enable in sleep mode + register + 0x44 + 0x20 + read-write + 0x00405225 + + + DBGSMEN + DBG clock enable during sleep mode + bit + 22 + 1 + + + USART1SMEN + USART1 clock enable during sleep mode + bit + 14 + 1 + + + SPI1SMEN + SPI1 clock enable during sleep mode + bit + 12 + 1 + + + ADCSMEN + ADC clock enable during sleep mode + bit + 9 + 1 + + + TIM22SMEN + TIM22 timer clock enable during sleep + mode bit + 5 + 1 + + + TIM21SMEN + TIM21 timer clock enable during sleep + mode bit + 2 + 1 + + + SYSCFGSMEN + System configuration controller clock + enable during sleep mode bit + 0 + 1 + + + + + APB1SMENR + APB1SMENR + APB1 peripheral clock enable in sleep mode + register + 0x48 + 0x20 + read-write + 0xB8E64A11 + + + LPTIM1SMEN + Low power timer clock enable during + sleep mode bit + 31 + 1 + + + PWRSMEN + Power interface clock enable during + sleep mode bit + 28 + 1 + + + CRSSMEN + Clock recovery system clock enable + during sleep mode bit + 27 + 1 + + + I2C2SMEN + I2C2 clock enable during sleep mode + bit + 22 + 1 + + + I2C1SMEN + I2C1 clock enable during sleep mode + bit + 21 + 1 + + + LPUART1SMEN + LPUART1 clock enable during sleep mode + bit + 18 + 1 + + + USART2SMEN + UART2 clock enable during sleep mode + bit + 17 + 1 + + + SPI2SMEN + SPI2 clock enable during sleep mode + bit + 14 + 1 + + + WWDGSMEN + Window watchdog clock enable during + sleep mode bit + 11 + 1 + + + TIM6SMEN + Timer 6 clock enable during sleep mode + bit + 4 + 1 + + + TIM2SMEN + Timer2 clock enable during sleep mode + bit + 0 + 1 + + + TIM3SMEN + Timer 3 clock enable during sleep mode + bit + 1 + 1 + + + TIM7SMEN + Timer 7 clock enable during sleep mode + bit + 5 + 1 + + + USART4SMEN + USART4 clock enabe during sleep mode + bit + 19 + 1 + + + USART5SMEN + USART5 clock enable during sleep mode + bit + 20 + 1 + + + I2C3SMEN + I2C3 clock enable during sleep mode + bit + 30 + 1 + + + + + CCIPR + CCIPR + Clock configuration register + 0x4C + 0x20 + read-write + 0x00000000 + + + LPTIM1SEL1 + Low Power Timer clock source selection + bits + 19 + 1 + + + LPTIM1SEL0 + LPTIM1SEL0 + 18 + 1 + + + I2C1SEL1 + I2C1 clock source selection + bits + 13 + 1 + + + I2C1SEL0 + I2C1SEL0 + 12 + 1 + + + LPUART1SEL1 + LPUART1 clock source selection + bits + 11 + 1 + + + LPUART1SEL0 + LPUART1SEL0 + 10 + 1 + + + USART2SEL1 + USART2 clock source selection + bits + 3 + 1 + + + USART2SEL0 + USART2SEL0 + 2 + 1 + + + USART1SEL1 + USART1 clock source selection + bits + 1 + 1 + + + USART1SEL0 + USART1SEL0 + 0 + 1 + + + I2C3SEL0 + I2C3 clock source selection + bits + 16 + 1 + + + I2C3SEL1 + I2C3 clock source selection + bits + 17 + 1 + + + + + CSR + CSR + Control and status register + 0x50 + 0x20 + 0x0C000000 + + + LPWRSTF + Low-power reset flag + 31 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + IWDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + PINRSTF + PIN reset flag + 26 + 1 + read-write + + + OBLRSTF + OBLRSTF + 25 + 1 + read-write + + + FWRSTF + Firewall reset flag + 24 + 1 + read-write + + + RTCRST + RTC software reset bit + 19 + 1 + read-write + + + RTCEN + RTC clock enable bit + 18 + 1 + read-write + + + RTCSEL + RTC and LCD clock source selection + bits + 16 + 2 + read-write + + + CSSLSED + CSS on LSE failure detection + flag + 14 + 1 + read-write + + + CSSLSEON + CSSLSEON + 13 + 1 + read-write + + + LSEDRV + LSEDRV + 11 + 2 + read-write + + + LSEBYP + External low-speed oscillator bypass + bit + 10 + 1 + read-write + + + LSERDY + External low-speed oscillator ready + bit + 9 + 1 + read-only + + + LSEON + External low-speed oscillator enable + bit + 8 + 1 + read-write + + + LSIRDY + Internal low-speed oscillator ready + bit + 1 + 1 + read-only + + + LSION + Internal low-speed oscillator + enable + 0 + 1 + read-write + + + LSIIWDGLP + LSI clock input to IWDG in + Ultra-low-power mode (Stop and Standby) enable + bit + 2 + 1 + read-write + + + RMVF + Remove reset flag + 23 + 1 + read-write + + + + + + + SYSCFG_COMP + System configuration controller and COMP + register + SYSCFG + 0x40010000 + + 0x0 + 0x400 + registers + + + + CFGR1 + CFGR1 + SYSCFG configuration register + 1 + 0x0 + 0x20 + 0x00000000 + + + BOOT_MODE + Boot mode selected by the boot pins + status bits + 8 + 2 + read-only + + + MEM_MODE + Memory mapping selection + bits + 0 + 2 + read-write + + + + + CFGR2 + CFGR2 + SYSCFG configuration register + 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + I2C2_FMP + I2C2 Fm+ drive capability enable + bit + 13 + 1 + + + I2C1_FMP + I2C1 Fm+ drive capability enable + bit + 12 + 1 + + + I2C_PB9_FMP + Fm+ drive capability on PB9 enable + bit + 11 + 1 + + + I2C_PB8_FMP + Fm+ drive capability on PB8 enable + bit + 10 + 1 + + + I2C_PB7_FMP + Fm+ drive capability on PB7 enable + bit + 9 + 1 + + + I2C_PB6_FMP + Fm+ drive capability on PB6 enable + bit + 8 + 1 + + + CAPA + Configuration of internal VLCD rail + connection to optional external + capacitor + 1 + 3 + + + FWDISEN + Firewall disable bit + 0 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to + 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to + 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to + 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to + 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to + 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to + 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to + 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to + 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to + 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to + 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to + 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to + 15) + 12 + 4 + + + EXTI14 + EXTI14 + 8 + 4 + + + EXTI13 + EXTI13 + 4 + 4 + + + EXTI12 + EXTI12 + 0 + 4 + + + + + CFGR3 + CFGR3 + SYSCFG configuration register + 3 + 0x20 + 0x20 + 0x00000000 + + + REF_LOCK + REF_CTRL lock bit + 31 + 1 + write-only + + + VREFINT_RDYF + VREFINT ready flag + 30 + 1 + read-only + + + VREFINT_COMP_RDYF + VREFINT for comparator ready + flag + 29 + 1 + read-only + + + VREFINT_ADC_RDYF + VREFINT for ADC ready flag + 28 + 1 + read-only + + + SENSOR_ADC_RDYF + Sensor for ADC ready flag + 27 + 1 + read-only + + + REF_RC48MHz_RDYF + VREFINT for 48 MHz RC oscillator ready + flag + 26 + 1 + read-only + + + ENREF_RC48MHz + VREFINT reference for 48 MHz RC + oscillator enable bit + 13 + 1 + read-write + + + ENBUF_VREFINT_COMP + VREFINT reference for comparator 2 + enable bit + 12 + 1 + read-write + + + ENBUF_SENSOR_ADC + Sensor reference for ADC enable + bit + 9 + 1 + read-write + + + ENBUF_BGAP_ADC + VREFINT reference for ADC enable + bit + 8 + 1 + read-write + + + SEL_VREF_OUT + BGAP_ADC connection bit + 4 + 2 + read-write + + + EN_BGAP + Vref Enable bit + 0 + 1 + read-write + + + + + COMP1_CTRL + COMP1_CTRL + Comparator 1 control and status + register + 0x18 + 0x20 + read-write + 0x00000000 + + + COMP1EN + Comparator 1 enable bit + 0 + 1 + + + COMP1INNSEL + Comparator 1 Input Minus connection + configuration bit + 4 + 2 + + + COMP1WM + Comparator 1 window mode selection + bit + 8 + 1 + + + COMP1LPTIMIN1 + Comparator 1 LPTIM input propagation + bit + 12 + 1 + + + COMP1POLARITY + Comparator 1 polarity selection + bit + 15 + 1 + + + COMP1VALUE + Comparator 1 output status + bit + 30 + 1 + + + COMP1LOCK + COMP1_CSR register lock + bit + 31 + 1 + + + + + COMP2_CTRL + COMP2_CTRL + Comparator 2 control and status + register + 0x1C + 0x20 + read-write + 0x00000000 + + + COMP2EN + Comparator 2 enable bit + 0 + 1 + + + COMP2SPEED + Comparator 2 power mode selection + bit + 3 + 1 + + + COMP2INNSEL + Comparator 2 Input Minus connection + configuration bit + 4 + 3 + + + COMP2INPSEL + Comparator 2 Input Plus connection + configuration bit + 8 + 3 + + + COMP2LPTIMIN2 + Comparator 2 LPTIM input 2 propagation + bit + 12 + 1 + + + COMP2LPTIMIN1 + Comparator 2 LPTIM input 1 propagation + bit + 13 + 1 + + + COMP2POLARITY + Comparator 2 polarity selection + bit + 15 + 1 + + + COMP2VALUE + Comparator 2 output status + bit + 30 + 1 + + + COMP2LOCK + COMP2_CSR register lock + bit + 31 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1_global_interrupt + 25 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + SSOE + SS output enable + 2 + 1 + + + FRF + Frame format + 4 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + CHSIDE + Channel side + 2 + 1 + read-only + + + UDR + Underrun flag + 3 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + MODF + Mode fault + 5 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMOD + I2S mode selection + 11 + 1 + + + I2SE + I2S Enable + 10 + 1 + + + I2SCFG + I2S configuration mode + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPOL + Steady state clock + polarity + 3 + 1 + + + DATLEN + Data length to be + transferred + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 0x00000010 + + + MCKOE + Master clock output enable + 9 + 1 + + + ODD + Odd factor for the + prescaler + 8 + 1 + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 26 + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 global interrupt + 23 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match interrupt enable (slave + only) + 3 + 1 + + + NACKIE + Not acknowledge received interrupt + enable + 4 + 1 + + + STOPIE + STOP detection Interrupt + enable + 5 + 1 + + + TCIE + Transfer Complete interrupt + enable + 6 + 1 + + + ERRIE + Error interrupts enable + 7 + 1 + + + DNF + Digital noise filter + 8 + 4 + + + ANFOFF + Analog noise filter OFF + 12 + 1 + + + TXDMAEN + DMA transmission requests + enable + 14 + 1 + + + RXDMAEN + DMA reception requests + enable + 15 + 1 + + + SBC + Slave byte control + 16 + 1 + + + NOSTRETCH + Clock stretching disable + 17 + 1 + + + WUPEN + Wakeup from STOP enable + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable + 20 + 1 + + + SMBDEN + SMBus Device Default address + enable + 21 + 1 + + + ALERTEN + SMBUS alert enable + 22 + 1 + + + PECEN + PEC enable + 23 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master + mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave + mode) + 15 + 1 + + + STOP + Stop generation (master + mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read + direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master + mode) + 11 + 1 + + + RD_WRN + Transfer direction (master + mode) + 10 + 1 + + + SADD + Slave address bit (master + mode) + 0 + 10 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master + mode) + 0 + 8 + + + SCLH + SCL high period (master + mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout + detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout + enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave + mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave + mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection + flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave + mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master + mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received + flag + 4 + 1 + read-only + + + ADDR + Address matched (slave + mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty + (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status + (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty + (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag + clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag + clear + 10 + 1 + + + ARLOCF + Arbitration lost flag + clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking + register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2 + I2C2 global interrupt + 24 + + + + I2C3 + 0x40007800 + + I2C3 + I2C3 global interrupt + 21 + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + CR + CR + power control register + 0x0 + 0x20 + read-write + 0x00001000 + + + LPDS + Low-power deep sleep + 0 + 1 + + + PDDS + Power down deepsleep + 1 + 1 + + + CWUF + Clear wakeup flag + 2 + 1 + + + CSBF + Clear standby flag + 3 + 1 + + + PVDE + Power voltage detector + enable + 4 + 1 + + + PLS + PVD level selection + 5 + 3 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + ULP + Ultra-low-power mode + 9 + 1 + + + FWU + Fast wakeup + 10 + 1 + + + VOS + Voltage scaling range + selection + 11 + 2 + + + DS_EE_KOFF + Deep sleep mode with Flash memory kept + off + 13 + 1 + + + LPRUN + Low power run mode + 14 + 1 + + + + + CSR + CSR + power control/status register + 0x4 + 0x20 + 0x00000000 + + + BRE + Backup regulator enable + 9 + 1 + read-write + + + EWUP + Enable WKUP pin + 8 + 1 + read-write + + + BRR + Backup regulator ready + 3 + 1 + read-only + + + PVDO + PVD output + 2 + 1 + read-only + + + SBF + Standby flag + 1 + 1 + read-only + + + WUF + Wakeup flag + 0 + 1 + read-only + + + VOSF + Voltage Scaling select + flag + 4 + 1 + read-only + + + REGLPF + Regulator LP flag + 5 + 1 + read-only + + + + + + + Flash + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 3 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LATENCY + Latency + 0 + 1 + + + PRFTEN + Prefetch enable + 1 + 1 + + + SLEEP_PD + Flash mode during Sleep + 3 + 1 + + + RUN_PD + Flash mode during Run + 4 + 1 + + + DESAB_BUF + Disable Buffer + 5 + 1 + + + PRE_READ + Pre-read data address + 6 + 1 + + + + + PECR + PECR + Program/erase control register + 0x4 + 0x20 + read-write + 0x00000007 + + + PELOCK + FLASH_PECR and data EEPROM + lock + 0 + 1 + + + PRGLOCK + Program memory lock + 1 + 1 + + + OPTLOCK + Option bytes block lock + 2 + 1 + + + PROG + Program memory selection + 3 + 1 + + + DATA + Data EEPROM selection + 4 + 1 + + + FTDW + Fixed time data write for Byte, Half + Word and Word programming + 8 + 1 + + + ERASE + Page or Double Word erase + mode + 9 + 1 + + + FPRG + Half Page/Double Word programming + mode + 10 + 1 + + + PARALLELBANK + Parallel bank mode + 15 + 1 + + + EOPIE + End of programming interrupt + enable + 16 + 1 + + + ERRIE + Error interrupt enable + 17 + 1 + + + OBL_LAUNCH + Launch the option byte + loading + 18 + 1 + + + + + PDKEYR + PDKEYR + Power down key register + 0x8 + 0x20 + write-only + 0x00000000 + + + PDKEYR + RUN_PD in FLASH_ACR key + 0 + 32 + + + + + PEKEYR + PEKEYR + Program/erase key register + 0xC + 0x20 + write-only + 0x00000000 + + + PEKEYR + FLASH_PEC and data EEPROM + key + 0 + 32 + + + + + PRGKEYR + PRGKEYR + Program memory key register + 0x10 + 0x20 + write-only + 0x00000000 + + + PRGKEYR + Program memory key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0x14 + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x18 + 0x20 + 0x00000004 + + + BSY + Write/erase operations in + progress + 0 + 1 + read-only + + + EOP + End of operation + 1 + 1 + read-only + + + ENDHV + End of high voltage + 2 + 1 + read-only + + + READY + Flash memory module ready after low + power mode + 3 + 1 + read-only + + + WRPERR + Write protected error + 8 + 1 + read-write + + + PGAERR + Programming alignment + error + 9 + 1 + read-write + + + SIZERR + Size error + 10 + 1 + read-write + + + OPTVERR + Option validity error + 11 + 1 + read-write + + + RDERR + RDERR + 14 + 1 + read-write + + + NOTZEROERR + NOTZEROERR + 16 + 1 + read-write + + + FWWERR + FWWERR + 17 + 1 + read-write + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0x00F80000 + + + RDPRT + Read protection + 0 + 8 + + + BOR_LEV + BOR_LEV + 16 + 4 + + + SPRMOD + Selection of protection mode of WPR + bits + 8 + 1 + + + + + WRPR + WRPR + Write protection register + 0x20 + 0x20 + read-write + 0x00000000 + + + WRP + Write protection + 0 + 16 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + 1 + + + EXTI0_1 + EXTI Line[1:0] interrupts + 5 + + + EXTI2_3 + EXTI Line[3:2] interrupts + 6 + + + EXTI4_15 + EXTI Line15 and EXTI4 interrupts + 7 + + + + IMR + IMR + Interrupt mask register + (EXTI_IMR) + 0x0 + 0x20 + read-write + 0xFF840000 + + + IM0 + Interrupt Mask on line 0 + 0 + 1 + + + IM1 + Interrupt Mask on line 1 + 1 + 1 + + + IM2 + Interrupt Mask on line 2 + 2 + 1 + + + IM3 + Interrupt Mask on line 3 + 3 + 1 + + + IM4 + Interrupt Mask on line 4 + 4 + 1 + + + IM5 + Interrupt Mask on line 5 + 5 + 1 + + + IM6 + Interrupt Mask on line 6 + 6 + 1 + + + IM7 + Interrupt Mask on line 7 + 7 + 1 + + + IM8 + Interrupt Mask on line 8 + 8 + 1 + + + IM9 + Interrupt Mask on line 9 + 9 + 1 + + + IM10 + Interrupt Mask on line 10 + 10 + 1 + + + IM11 + Interrupt Mask on line 11 + 11 + 1 + + + IM12 + Interrupt Mask on line 12 + 12 + 1 + + + IM13 + Interrupt Mask on line 13 + 13 + 1 + + + IM14 + Interrupt Mask on line 14 + 14 + 1 + + + IM15 + Interrupt Mask on line 15 + 15 + 1 + + + IM16 + Interrupt Mask on line 16 + 16 + 1 + + + IM17 + Interrupt Mask on line 17 + 17 + 1 + + + IM18 + Interrupt Mask on line 18 + 18 + 1 + + + IM19 + Interrupt Mask on line 19 + 19 + 1 + + + IM20 + Interrupt Mask on line 20 + 20 + 1 + + + IM21 + Interrupt Mask on line 21 + 21 + 1 + + + IM22 + Interrupt Mask on line 22 + 22 + 1 + + + IM23 + Interrupt Mask on line 23 + 23 + 1 + + + IM24 + Interrupt Mask on line 24 + 24 + 1 + + + IM25 + Interrupt Mask on line 25 + 25 + 1 + + + IM26 + Interrupt Mask on line 27 + 26 + 1 + + + IM28 + Interrupt Mask on line 27 + 28 + 1 + + + IM29 + Interrupt Mask on line 27 + 29 + 1 + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + EM0 + Event Mask on line 0 + 0 + 1 + + + EM1 + Event Mask on line 1 + 1 + 1 + + + EM2 + Event Mask on line 2 + 2 + 1 + + + EM3 + Event Mask on line 3 + 3 + 1 + + + EM4 + Event Mask on line 4 + 4 + 1 + + + EM5 + Event Mask on line 5 + 5 + 1 + + + EM6 + Event Mask on line 6 + 6 + 1 + + + EM7 + Event Mask on line 7 + 7 + 1 + + + EM8 + Event Mask on line 8 + 8 + 1 + + + EM9 + Event Mask on line 9 + 9 + 1 + + + EM10 + Event Mask on line 10 + 10 + 1 + + + EM11 + Event Mask on line 11 + 11 + 1 + + + EM12 + Event Mask on line 12 + 12 + 1 + + + EM13 + Event Mask on line 13 + 13 + 1 + + + EM14 + Event Mask on line 14 + 14 + 1 + + + EM15 + Event Mask on line 15 + 15 + 1 + + + EM16 + Event Mask on line 16 + 16 + 1 + + + EM17 + Event Mask on line 17 + 17 + 1 + + + EM18 + Event Mask on line 18 + 18 + 1 + + + EM19 + Event Mask on line 19 + 19 + 1 + + + EM20 + Event Mask on line 20 + 20 + 1 + + + EM21 + Event Mask on line 21 + 21 + 1 + + + EM22 + Event Mask on line 22 + 22 + 1 + + + EM23 + Event Mask on line 23 + 23 + 1 + + + EM24 + Event Mask on line 24 + 24 + 1 + + + EM25 + Event Mask on line 25 + 25 + 1 + + + EM26 + Event Mask on line 26 + 26 + 1 + + + EM28 + Event Mask on line 28 + 28 + 1 + + + EM29 + Event Mask on line 29 + 29 + 1 + + + + + RTSR + RTSR + Rising Trigger selection register + (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + RT0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + RT1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + RT2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + RT3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + RT4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + RT5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + RT6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + RT7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + RT8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + RT9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + RT10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + RT11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + RT12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + RT13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + RT14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + RT15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + RT16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + RT17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + RT19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + RT20 + Rising trigger event configuration of + line 20 + 20 + 1 + + + RT21 + Rising trigger event configuration of + line 21 + 21 + 1 + + + RT22 + Rising trigger event configuration of + line 22 + 22 + 1 + + + + + FTSR + FTSR + Falling Trigger selection register + (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + FT0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + FT1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + FT2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + FT3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + FT4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + FT5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + FT6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + FT7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + FT8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + FT9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + FT10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + FT11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + FT12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + FT13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + FT14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + FT15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + FT16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + FT17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + FT19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + FT20 + Falling trigger event configuration of + line 20 + 20 + 1 + + + FT21 + Falling trigger event configuration of + line 21 + 21 + 1 + + + FT22 + Falling trigger event configuration of + line 22 + 22 + 1 + + + + + SWIER + SWIER + Software interrupt event register + (EXTI_SWIER) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWI0 + Software Interrupt on line + 0 + 0 + 1 + + + SWI1 + Software Interrupt on line + 1 + 1 + 1 + + + SWI2 + Software Interrupt on line + 2 + 2 + 1 + + + SWI3 + Software Interrupt on line + 3 + 3 + 1 + + + SWI4 + Software Interrupt on line + 4 + 4 + 1 + + + SWI5 + Software Interrupt on line + 5 + 5 + 1 + + + SWI6 + Software Interrupt on line + 6 + 6 + 1 + + + SWI7 + Software Interrupt on line + 7 + 7 + 1 + + + SWI8 + Software Interrupt on line + 8 + 8 + 1 + + + SWI9 + Software Interrupt on line + 9 + 9 + 1 + + + SWI10 + Software Interrupt on line + 10 + 10 + 1 + + + SWI11 + Software Interrupt on line + 11 + 11 + 1 + + + SWI12 + Software Interrupt on line + 12 + 12 + 1 + + + SWI13 + Software Interrupt on line + 13 + 13 + 1 + + + SWI14 + Software Interrupt on line + 14 + 14 + 1 + + + SWI15 + Software Interrupt on line + 15 + 15 + 1 + + + SWI16 + Software Interrupt on line + 16 + 16 + 1 + + + SWI17 + Software Interrupt on line + 17 + 17 + 1 + + + SWI19 + Software Interrupt on line + 19 + 19 + 1 + + + SWI20 + Software Interrupt on line + 20 + 20 + 1 + + + SWI21 + Software Interrupt on line + 21 + 21 + 1 + + + SWI22 + Software Interrupt on line + 22 + 22 + 1 + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PIF0 + Pending bit 0 + 0 + 1 + + + PIF1 + Pending bit 1 + 1 + 1 + + + PIF2 + Pending bit 2 + 2 + 1 + + + PIF3 + Pending bit 3 + 3 + 1 + + + PIF4 + Pending bit 4 + 4 + 1 + + + PIF5 + Pending bit 5 + 5 + 1 + + + PIF6 + Pending bit 6 + 6 + 1 + + + PIF7 + Pending bit 7 + 7 + 1 + + + PIF8 + Pending bit 8 + 8 + 1 + + + PIF9 + Pending bit 9 + 9 + 1 + + + PIF10 + Pending bit 10 + 10 + 1 + + + PIF11 + Pending bit 11 + 11 + 1 + + + PIF12 + Pending bit 12 + 12 + 1 + + + PIF13 + Pending bit 13 + 13 + 1 + + + PIF14 + Pending bit 14 + 14 + 1 + + + PIF15 + Pending bit 15 + 15 + 1 + + + PIF16 + Pending bit 16 + 16 + 1 + + + PIF17 + Pending bit 17 + 17 + 1 + + + PIF19 + Pending bit 19 + 19 + 1 + + + PIF20 + Pending bit 20 + 20 + 1 + + + PIF21 + Pending bit 21 + 21 + 1 + + + PIF22 + Pending bit 22 + 22 + 1 + + + + + + + ADC + Analog-to-digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC_COMP + ADC and comparator 1 and 2 + 12 + + + + ISR + ISR + interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + ADRDY + ADC ready + 0 + 1 + + + EOSMP + End of sampling flag + 1 + 1 + + + EOC + End of conversion flag + 2 + 1 + + + EOS + End of sequence flag + 3 + 1 + + + OVR + ADC overrun + 4 + 1 + + + AWD + Analog watchdog flag + 7 + 1 + + + EOCAL + End Of Calibration flag + 11 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADRDYIE + ADC ready interrupt enable + 0 + 1 + + + EOSMPIE + End of sampling flag interrupt + enable + 1 + 1 + + + EOCIE + End of conversion interrupt + enable + 2 + 1 + + + EOSIE + End of conversion sequence interrupt + enable + 3 + 1 + + + OVRIE + Overrun interrupt enable + 4 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 7 + 1 + + + EOCALIE + End of calibration interrupt + enable + 11 + 1 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADEN + ADC enable command + 0 + 1 + + + ADDIS + ADC disable command + 1 + 1 + + + ADSTART + ADC start conversion + command + 2 + 1 + + + ADSTP + ADC stop conversion + command + 4 + 1 + + + ADVREGEN + ADC Voltage Regulator + Enable + 28 + 1 + + + ADCAL + ADC calibration + 31 + 1 + + + + + CFGR1 + CFGR1 + configuration register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 26 + 5 + + + AWDEN + Analog watchdog enable + 23 + 1 + + + AWDSGL + Enable the watchdog on a single channel + or on all channels + 22 + 1 + + + DISCEN + Discontinuous mode + 16 + 1 + + + AUTOFF + Auto-off mode + 15 + 1 + + + AUTDLY + Auto-delayed conversion + mode + 14 + 1 + + + CONT + Single / continuous conversion + mode + 13 + 1 + + + OVRMOD + Overrun management mode + 12 + 1 + + + EXTEN + External trigger enable and polarity + selection + 10 + 2 + + + EXTSEL + External trigger selection + 6 + 3 + + + ALIGN + Data alignment + 5 + 1 + + + RES + Data resolution + 3 + 2 + + + SCANDIR + Scan sequence direction + 2 + 1 + + + DMACFG + Direct memery access + configuration + 1 + 1 + + + DMAEN + Direct memory access + enable + 0 + 1 + + + + + CFGR2 + CFGR2 + configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + OVSE + Oversampler Enable + 0 + 1 + + + OVSR + Oversampling ratio + 2 + 3 + + + OVSS + Oversampling shift + 5 + 4 + + + TOVS + Triggered Oversampling + 9 + 1 + + + CKMODE + ADC clock mode + 30 + 2 + + + + + SMPR + SMPR + sampling time register + 0x14 + 0x20 + read-write + 0x00000000 + + + SMPR + Sampling time selection + 0 + 3 + + + + + TR + TR + watchdog threshold register + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT + Analog watchdog higher + threshold + 16 + 12 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + + + CHSELR + CHSELR + channel selection register + 0x28 + 0x20 + read-write + 0x00000000 + + + CHSEL18 + Channel-x selection + 18 + 1 + + + CHSEL17 + Channel-x selection + 17 + 1 + + + CHSEL16 + Channel-x selection + 16 + 1 + + + CHSEL15 + Channel-x selection + 15 + 1 + + + CHSEL14 + Channel-x selection + 14 + 1 + + + CHSEL13 + Channel-x selection + 13 + 1 + + + CHSEL12 + Channel-x selection + 12 + 1 + + + CHSEL11 + Channel-x selection + 11 + 1 + + + CHSEL10 + Channel-x selection + 10 + 1 + + + CHSEL9 + Channel-x selection + 9 + 1 + + + CHSEL8 + Channel-x selection + 8 + 1 + + + CHSEL7 + Channel-x selection + 7 + 1 + + + CHSEL6 + Channel-x selection + 6 + 1 + + + CHSEL5 + Channel-x selection + 5 + 1 + + + CHSEL4 + Channel-x selection + 4 + 1 + + + CHSEL3 + Channel-x selection + 3 + 1 + + + CHSEL2 + Channel-x selection + 2 + 1 + + + CHSEL1 + Channel-x selection + 1 + 1 + + + CHSEL0 + Channel-x selection + 0 + 1 + + + + + DR + DR + data register + 0x40 + 0x20 + read-only + 0x00000000 + + + DATA + Converted data + 0 + 16 + + + + + CALFACT + CALFACT + ADC Calibration factor + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT + Calibration factor + 0 + 7 + + + + + CCR + CCR + ADC common configuration + register + 0x308 + 0x20 + read-write + 0x00000000 + + + PRESC + ADC prescaler + 18 + 4 + + + VREFEN + VREFINT enable + 22 + 1 + + + TSEN + Temperature sensor enable + 23 + 1 + + + VLCDEN + VLCD enable + 24 + 1 + + + LFMEN + Low Frequency Mode enable + 25 + 1 + + + + + + + DBG + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 12 + + + REV_ID + Revision Identifier + 16 + 16 + + + + + CR + CR + Debug MCU Configuration + Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + DBG_SLEEP + Debug Sleep Mode + 0 + 1 + + + + + APB1_FZ + APB1_FZ + APB Low Freeze Register + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER2_STOP + Debug Timer 2 stopped when Core is + halted + 0 + 1 + + + DBG_TIMER6_STOP + Debug Timer 6 stopped when Core is + halted + 4 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is + halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core + is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when + Core is halted + 12 + 1 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout mode stopped when + core is halted + 21 + 1 + + + DBG_I2C2_STOP + I2C2 SMBUS timeout mode stopped when + core is halted + 22 + 1 + + + DBG_LPTIMER_STOP + LPTIM1 counter stopped when core is + halted + 31 + 1 + + + + + APB2_FZ + APB2_FZ + APB High Freeze Register + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIMER21_STOP + Debug Timer 21 stopped when Core is + halted + 2 + 1 + + + DBG_TIMER22_STO + Debug Timer 22 stopped when Core is + halted + 6 + 1 + + + + + + + TIM2 + General-purpose-timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 15 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output compare 2 clear + enable + 15 + 1 + + + OC2M + Output compare 2 mode + 12 + 3 + + + OC2PE + Output compare 2 preload + enable + 11 + 1 + + + OC2FE + Output compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output compare 1 clear + enable + 7 + 1 + + + OC1M + Output compare 1 mode + 4 + 3 + + + OC1PE + Output compare 1 preload + enable + 3 + 1 + + + OC1FE + Output compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + 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Capture/Compare 2 value + 0 + 16 + + + + + OR + OR + TIM21 option register + 0x50 + 0x20 + read-write + 0x00000000 + + + ETR_RMP + Timer21 ETR remap + 0 + 2 + + + TI1_RMP + Timer21 TI1 + 2 + 3 + + + TI2_RMP + Timer21 TI2 + 5 + 1 + + + + + + + TIM22 + General-purpose-timers + TIM + 0x40011400 + + 0x0 + 0x400 + registers + + + TIM22 + TIMER22 global interrupt + 22 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + DIR + Direction + 4 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS + Slave mode selection + 0 + 3 + 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Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 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read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register 0 + 0x300 + 0x20 + read-write + 0x00000000 + + + PRI_0 + priority for interrupt 0 + 0 + 8 + + + PRI_1 + priority for interrupt 1 + 8 + 8 + + + PRI_2 + priority for interrupt 2 + 16 + 8 + + + PRI_3 + priority for interrupt 3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register 1 + 0x304 + 0x20 + read-write + 0x00000000 + + + PRI_4 + priority for interrupt n + 0 + 8 + + + PRI_5 + priority for interrupt n + 8 + 8 + + + PRI_6 + priority for interrupt n + 16 + 8 + + + PRI_7 + priority for interrupt n + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register 2 + 0x308 + 0x20 + read-write + 0x00000000 + + + PRI_8 + priority for interrupt n + 0 + 8 + + + PRI_9 + priority for interrupt n + 8 + 8 + + + PRI_10 + priority for interrupt n + 16 + 8 + + + PRI_11 + priority for interrupt n + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register 3 + 0x30C + 0x20 + read-write + 0x00000000 + + + PRI_12 + priority for interrupt n + 0 + 8 + + + PRI_13 + priority for interrupt n + 8 + 8 + + + PRI_14 + priority for interrupt n + 16 + 8 + + + PRI_15 + priority for interrupt n + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register 4 + 0x310 + 0x20 + read-write + 0x00000000 + + + PRI_16 + priority for interrupt n + 0 + 8 + + + PRI_17 + priority for interrupt n + 8 + 8 + + + PRI_18 + priority for interrupt n + 16 + 8 + + + PRI_19 + priority for interrupt n + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register 5 + 0x314 + 0x20 + read-write + 0x00000000 + + + PRI_20 + priority for interrupt n + 0 + 8 + + + PRI_21 + priority for interrupt n + 8 + 8 + + + PRI_22 + priority for interrupt n + 16 + 8 + + + PRI_23 + priority for interrupt n + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register 6 + 0x318 + 0x20 + read-write + 0x00000000 + + + PRI_24 + priority for interrupt n + 0 + 8 + + + PRI_25 + priority for interrupt n + 8 + 8 + + + PRI_26 + priority for interrupt n + 16 + 8 + + + PRI_27 + priority for interrupt n + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register 7 + 0x31C + 0x20 + read-write + 0x00000000 + + + PRI_28 + priority for interrupt n + 0 + 8 + + + PRI_29 + priority for interrupt n + 8 + 8 + + + PRI_30 + priority for interrupt n + 16 + 8 + + + PRI_31 + priority for interrupt n + 24 + 8 + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + MPU_TYPER + MPU_TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction + regions + 16 + 8 + + + + + MPU_CTRL + MPU_CTRL + MPU control register + 0x4 + 0x20 + read-only + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard + fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to + default memory map + 2 + 1 + + + + + MPU_RNR + MPU_RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + MPU_RBAR + MPU_RBAR + MPU region base address + register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + MPU_RASR + MPU_RASR + MPU region attribute and size + register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection + region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable + bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CSR + CSR + SysTick control and status + register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request + enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + RVR + RVR + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + CVR + CVR + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value + register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS + value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Architecture + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 7 + 25 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + + + diff --git a/firmware/svd/STM32L0x2.svd b/firmware/svd/STM32L0x2.svd new file mode 100644 index 0000000..bc19e6f --- /dev/null +++ b/firmware/svd/STM32L0x2.svd @@ -0,0 +1,20698 @@ + + + STM32L0x2 + 1.3 + STM32L0x2 + + + CM0+ + r0p0 + little + false + false + 3 + false + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + AES + Advanced encryption standard hardware + accelerator + AES + 0x40026000 + + 0x0 + 0x400 + registers + + + AES_RNG_LPUART1 + AES global interrupt RNG global interrupt and + LPUART1 global interrupt through + 29 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAOUTEN + Enable DMA management of data output + phase + 12 + 1 + + + DMAINEN + Enable DMA management of data input + phase + 11 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + CCFIE + CCF flag interrupt enable + 9 + 1 + + + ERRC + Error clear + 8 + 1 + + + CCFC + Computation Complete Flag + Clear + 7 + 1 + + + CHMOD + AES chaining mode + 5 + 2 + + + MODE + AES operating mode + 3 + 2 + + + DATATYPE + Data type selection (for data in and + data out to/from the cryptographic + block) + 1 + 2 + + + EN + AES enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + WRERR + Write error flag + 2 + 1 + + + RDERR + Read error flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + DINR + DINR + data input register + 0x8 + 0x20 + read-write + 0x00000000 + + + AES_DINR + Data Input Register. + 0 + 32 + + + + + DOUTR + DOUTR + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + AES_DOUTR + Data output register + 0 + 32 + + + + + KEYR0 + KEYR0 + key register 0 + 0x10 + 0x20 + read-write + 0x00000000 + + + AES_KEYR0 + Data Output Register (LSB key + [31:0]) + 0 + 32 + + + + + KEYR1 + KEYR1 + key register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + AES_KEYR1 + AES key register (key + [63:32]) + 0 + 32 + + + + + KEYR2 + KEYR2 + key register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + AES_KEYR2 + AES key register (key + [95:64]) + 0 + 32 + + + + + KEYR3 + KEYR3 + key register 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + AES_KEYR3 + AES key register (MSB key + [127:96]) + 0 + 32 + + + + + IVR0 + IVR0 + initialization vector register + 0 + 0x20 + 0x20 + read-write + 0x00000000 + + + AES_IVR0 + initialization vector register (LSB IVR + [31:0]) + 0 + 32 + + + + + IVR1 + IVR1 + initialization vector register + 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + AES_IVR1 + Initialization Vector Register (IVR + [63:32]) + 0 + 32 + + + + + IVR2 + IVR2 + initialization vector register + 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + AES_IVR2 + Initialization Vector Register (IVR + [95:64]) + 0 + 32 + + + + + IVR3 + IVR3 + initialization vector register + 3 + 0x2C + 0x20 + read-write + 0x00000000 + + + AES_IVR3 + Initialization Vector Register (MSB IVR + [127:96]) + 0 + 32 + + + + + + + DAC + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable + 13 + 1 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + + BOFF1 + DAC channel1 output buffer + disable + 1 + 1 + + + EN1 + DAC channel1 enable + 0 + 1 + + + + + SWTRIGR + SWTRIGR + software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + + + DHR12R1 + DHR12R1 + channel1 12-bit right-aligned data holding + register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L1 + DHR12L1 + channel1 12-bit left-aligned data holding + register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R1 + DHR8R1 + channel1 8-bit right-aligned data holding + register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR1 + DAC channel1 DMA underrun + flag + 13 + 1 + + + + + DHR12R2 + DHR12R2 + channel2 12-bit right-aligned data holding + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L2 + DHR12L2 + channel2 12-bit left-aligned data holding + register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R2 + DHR8R2 + channel2 8-bit right-aligned data holding + register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + + + DHR12LD + DHR12LD + Dual DAC 12-bit left-aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 20 + 12 + + + + + DHR8RD + DHR8RD + Dual DAC 8-bit right-aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + + + DOR2 + DOR2 + channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + + + DMA1 + Direct memory access controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 9 + + + DMA1_Channel2_3 + DMA1 Channel2 and 3 interrupts + 10 + + + DMA1_Channel4_7 + DMA1 Channel4 to 7 interrupts + 11 + + + + ISR + ISR + interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF7 + Channel x transfer error flag (x = 1 + ..7) + 27 + 1 + + + HTIF7 + Channel x half transfer flag (x = 1 + ..7) + 26 + 1 + + + TCIF7 + Channel x transfer complete flag (x = 1 + ..7) + 25 + 1 + + + GIF7 + Channel x global interrupt flag (x = 1 + ..7) + 24 + 1 + + + TEIF6 + Channel x transfer error flag (x = 1 + ..7) + 23 + 1 + + + HTIF6 + Channel x half transfer flag (x = 1 + ..7) + 22 + 1 + + + TCIF6 + Channel x transfer complete flag (x = 1 + ..7) + 21 + 1 + + + GIF6 + Channel x global interrupt flag (x = 1 + ..7) + 20 + 1 + + + TEIF5 + Channel x transfer error flag (x = 1 + ..7) + 19 + 1 + + + HTIF5 + Channel x half transfer flag (x = 1 + ..7) + 18 + 1 + + + TCIF5 + Channel x transfer complete flag (x = 1 + ..7) + 17 + 1 + + + GIF5 + Channel x global interrupt flag (x = 1 + ..7) + 16 + 1 + + + TEIF4 + Channel x transfer error flag (x = 1 + ..7) + 15 + 1 + + + HTIF4 + Channel x half transfer flag (x = 1 + ..7) + 14 + 1 + + + TCIF4 + Channel x transfer complete flag (x = 1 + ..7) + 13 + 1 + + + GIF4 + Channel x global interrupt flag (x = 1 + ..7) + 12 + 1 + + + TEIF3 + Channel x transfer error flag (x = 1 + ..7) + 11 + 1 + + + HTIF3 + Channel x half transfer flag (x = 1 + ..7) + 10 + 1 + + + TCIF3 + Channel x transfer complete flag (x = 1 + ..7) + 9 + 1 + + + GIF3 + Channel x global interrupt flag (x = 1 + ..7) + 8 + 1 + + + TEIF2 + Channel x transfer error flag (x = 1 + ..7) + 7 + 1 + + + HTIF2 + Channel x half transfer flag (x = 1 + ..7) + 6 + 1 + + + TCIF2 + Channel x transfer complete flag (x = 1 + ..7) + 5 + 1 + + + GIF2 + Channel x global interrupt flag (x = 1 + ..7) + 4 + 1 + + + TEIF1 + Channel x transfer error flag (x = 1 + ..7) + 3 + 1 + + + HTIF1 + Channel x half transfer flag (x = 1 + ..7) + 2 + 1 + + + TCIF1 + Channel x transfer complete flag (x = 1 + ..7) + 1 + 1 + + + GIF1 + Channel x global interrupt flag (x = 1 + ..7) + 0 + 1 + + + + + IFCR + IFCR + interrupt flag clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + CTEIF7 + Channel x transfer error clear (x = 1 + ..7) + 27 + 1 + + + CHTIF7 + Channel x half transfer clear (x = 1 + ..7) + 26 + 1 + + + CTCIF7 + Channel x transfer complete clear (x = 1 + ..7) + 25 + 1 + + + CGIF7 + Channel x global interrupt clear (x = 1 + ..7) + 24 + 1 + + + CTEIF6 + Channel x transfer error clear (x = 1 + ..7) + 23 + 1 + + + CHTIF6 + Channel x half transfer clear (x = 1 + ..7) + 22 + 1 + + + CTCIF6 + Channel x transfer complete clear (x = 1 + ..7) + 21 + 1 + + + CGIF6 + Channel x global interrupt clear (x = 1 + ..7) + 20 + 1 + + + CTEIF5 + Channel x transfer error clear (x = 1 + ..7) + 19 + 1 + + + CHTIF5 + Channel x half transfer clear (x = 1 + ..7) + 18 + 1 + + + CTCIF5 + Channel x transfer complete clear (x = 1 + ..7) + 17 + 1 + + + CGIF5 + Channel x global interrupt clear (x = 1 + ..7) + 16 + 1 + + + CTEIF4 + Channel x transfer error clear (x = 1 + ..7) + 15 + 1 + + + CHTIF4 + Channel x half transfer clear (x = 1 + ..7) + 14 + 1 + + + CTCIF4 + Channel x transfer complete clear (x = 1 + ..7) + 13 + 1 + + + CGIF4 + Channel x global interrupt clear (x = 1 + ..7) + 12 + 1 + + + CTEIF3 + Channel x transfer error clear (x = 1 + ..7) + 11 + 1 + + + CHTIF3 + Channel x half transfer clear (x = 1 + ..7) + 10 + 1 + + + CTCIF3 + Channel x transfer complete clear (x = 1 + ..7) + 9 + 1 + + + CGIF3 + Channel x global interrupt clear (x = 1 + ..7) + 8 + 1 + + + CTEIF2 + Channel x transfer error clear (x = 1 + ..7) + 7 + 1 + + + CHTIF2 + Channel x half transfer clear (x = 1 + ..7) + 6 + 1 + + + CTCIF2 + Channel x transfer complete clear (x = 1 + ..7) + 5 + 1 + + + CGIF2 + Channel x global interrupt clear (x = 1 + ..7) + 4 + 1 + + + CTEIF1 + Channel x transfer error clear (x = 1 + ..7) + 3 + 1 + + + CHTIF1 + Channel x half transfer clear (x = 1 + ..7) + 2 + 1 + + + CTCIF1 + Channel x transfer complete clear (x = 1 + ..7) + 1 + 1 + + + CGIF1 + Channel x global interrupt clear (x = 1 + ..7) + 0 + 1 + + + + + CCR1 + CCR1 + channel x configuration + register + 0x8 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR1 + CNDTR1 + channel x number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + channel x peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + channel x memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + channel x configuration + register + 0x1C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR2 + CNDTR2 + channel x number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + channel x peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + channel x memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + channel x configuration + register + 0x30 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR3 + CNDTR3 + channel x number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + channel x peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + channel x memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR4 + CCR4 + channel x configuration + register + 0x44 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR4 + CNDTR4 + channel x number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR4 + CPAR4 + channel x peripheral address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR4 + CMAR4 + channel x memory address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR5 + CCR5 + channel x configuration + register + 0x58 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR5 + CNDTR5 + channel x number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR5 + CPAR5 + channel x peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR5 + CMAR5 + channel x memory address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR6 + CCR6 + channel x configuration + register + 0x6C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR6 + CNDTR6 + channel x number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR6 + CPAR6 + channel x peripheral address + register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR6 + CMAR6 + channel x memory address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR7 + CCR7 + channel x configuration + register + 0x80 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR7 + CNDTR7 + channel x number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR7 + CPAR7 + channel x peripheral address + register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 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Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODE5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODE4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODE3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODE2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODE1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODE0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 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+ + PUPD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID15 + Port input data bit (y = + 0..15) + 15 + 1 + + + ID14 + Port input data bit (y = + 0..15) + 14 + 1 + + + ID13 + Port input data bit (y = + 0..15) + 13 + 1 + + + ID12 + Port input data bit (y = + 0..15) + 12 + 1 + + + ID11 + Port input data bit (y = + 0..15) + 11 + 1 + + + ID10 + Port input data bit (y = + 0..15) + 10 + 1 + + + ID9 + Port input data bit (y = + 0..15) + 9 + 1 + + + ID8 + Port input data bit (y = + 0..15) + 8 + 1 + + + ID7 + Port input data bit (y = + 0..15) + 7 + 1 + + + ID6 + Port input data bit (y = + 0..15) + 6 + 1 + + + ID5 + Port input data bit (y = + 0..15) + 5 + 1 + + + ID4 + Port input data bit (y = + 0..15) + 4 + 1 + + + ID3 + Port input data bit (y = + 0..15) + 3 + 1 + + + ID2 + Port input data bit (y = + 0..15) + 2 + 1 + + + ID1 + Port input data bit (y = + 0..15) + 1 + 1 + + + ID0 + Port input data bit (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD15 + Port output data bit (y = + 0..15) + 15 + 1 + + + OD14 + Port output data bit (y = + 0..15) + 14 + 1 + + + OD13 + Port output data bit (y = + 0..15) + 13 + 1 + + + OD12 + Port output data bit (y = + 0..15) + 12 + 1 + + + OD11 + Port output data bit (y = + 0..15) + 11 + 1 + + + OD10 + Port output data bit (y = + 0..15) + 10 + 1 + + + OD9 + Port output data bit (y = + 0..15) + 9 + 1 + + + OD8 + Port output data bit (y = + 0..15) + 8 + 1 + + + OD7 + Port output data bit (y = + 0..15) + 7 + 1 + + + OD6 + Port output data bit (y = + 0..15) + 6 + 1 + + + OD5 + Port output data bit (y = + 0..15) + 5 + 1 + + + OD4 + Port output data bit (y = + 0..15) + 4 + 1 + + + OD3 + Port output data bit (y = + 0..15) + 3 + 1 + + + OD2 + Port output data bit (y = + 0..15) + 2 + 1 + + + OD1 + Port output data bit (y = + 0..15) + 1 + 1 + + + OD0 + Port output data bit (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x reset bit y (y = + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL7 + Alternate function selection for port x + pin y (y = 0..7) + 28 + 4 + + + AFSEL6 + Alternate function selection for port x + pin y (y = 0..7) + 24 + 4 + + + AFSEL5 + Alternate function selection for port x + pin y (y = 0..7) + 20 + 4 + + + AFSEL4 + Alternate function selection for port x + pin y (y = 0..7) + 16 + 4 + + + AFSEL3 + Alternate function selection for port x + pin y (y = 0..7) + 12 + 4 + + + AFSEL2 + Alternate function selection for port x + pin y (y = 0..7) + 8 + 4 + + + AFSEL1 + Alternate function selection for port x + pin y (y = 0..7) + 4 + 4 + + + AFSEL0 + Alternate function selection for port x + pin y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + Alternate function selection for port x + pin y (y = 8..15) + 28 + 4 + + + AFSEL14 + Alternate function selection for port x + pin y (y = 8..15) + 24 + 4 + + + AFSEL13 + Alternate function selection for port x + pin y (y = 8..15) + 20 + 4 + + + AFSEL12 + Alternate function selection for port x + pin y (y = 8..15) + 16 + 4 + + + AFSEL11 + Alternate function selection for port x + pin y (y = 8..15) + 12 + 4 + + + AFSEL10 + Alternate function selection for port x + pin y (y = 8..15) + 8 + 4 + + + AFSEL9 + Alternate function selection for port x + pin y (y = 8..15) + 4 + 4 + + + AFSEL8 + Alternate function selection for port x + pin y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x Reset bit y (y= 0 .. + 15) + 15 + 1 + + + BR14 + Port x Reset bit y (y= 0 .. + 15) + 14 + 1 + + + BR13 + Port x Reset bit y (y= 0 .. + 15) + 13 + 1 + + + BR12 + Port x Reset bit y (y= 0 .. + 15) + 12 + 1 + + + BR11 + Port x Reset bit y (y= 0 .. + 15) + 11 + 1 + + + BR10 + Port x Reset bit y (y= 0 .. + 15) + 10 + 1 + + + BR9 + Port x Reset bit y (y= 0 .. + 15) + 9 + 1 + + + BR8 + Port x Reset bit y (y= 0 .. + 15) + 8 + 1 + + + BR7 + Port x Reset bit y (y= 0 .. + 15) + 7 + 1 + + + BR6 + Port x Reset bit y (y= 0 .. + 15) + 6 + 1 + + + BR5 + Port x Reset bit y (y= 0 .. + 15) + 5 + 1 + + + BR4 + Port x Reset bit y (y= 0 .. + 15) + 4 + 1 + + + BR3 + Port x Reset bit y (y= 0 .. + 15) + 3 + 1 + + + BR2 + Port x Reset bit y (y= 0 .. + 15) + 2 + 1 + + + BR1 + Port x Reset bit y (y= 0 .. + 15) + 1 + 1 + + + BR0 + Port x Reset bit y (y= 0 .. + 15) + 0 + 1 + + + + + + + GPIOC + 0x50000800 + + + GPIOD + 0x50000C00 + + + GPIOH + 0x50001C00 + + + GPIOE + 0x50001000 + + + LPTIM + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + LPTIM1 + LPTIMER1 interrupt through + EXTI29 + 13 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt + Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value. + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value. + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value. + 0 + 16 + + + + + + + RNG + Random number generator + RNG + 0x40025000 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator + enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt + status + 6 + 1 + read-write + + + CEIS + Clock error interrupt + status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC global interrupt + 2 + + + + TR + TR + RTC time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + RTC date register + 0x4 + 0x20 + read-write + 0x00000000 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + CR + CR + RTC control register + 0x8 + 0x20 + 0x00000000 + + + COE + Calibration output enable + 23 + 1 + read-write + + + OSEL + Output selection + 21 + 2 + read-write + + + POL + Output polarity + 20 + 1 + read-write + + + COSEL + Calibration output + selection + 19 + 1 + read-write + + + BKP + Backup + 18 + 1 + read-write + + + SUB1H + Subtract 1 hour (winter time + change) + 17 + 1 + write-only + + + ADD1H + Add 1 hour (summer time + change) + 16 + 1 + write-only + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + read-write + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + read-write + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + TSE + timestamp enable + 11 + 1 + read-write + + + WUTE + Wakeup timer enable + 10 + 1 + read-write + + + ALRBE + Alarm B enable + 9 + 1 + read-write + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + FMT + Hour format + 6 + 1 + read-write + + + BYPSHAD + Bypass the shadow + registers + 5 + 1 + read-write + + + REFCKON + RTC_REFIN reference clock detection + enable (50 or 60 Hz) + 4 + 1 + read-write + + + TSEDGE + Time-stamp event active + edge + 3 + 1 + read-write + + + WUCKSEL + Wakeup clock selection + 0 + 3 + read-write + + + + + ISR + ISR + RTC initialization and status + register + 0xC + 0x20 + 0x00000000 + + + TAMP2F + RTC_TAMP2 detection flag + 14 + 1 + read-write + + + TAMP1F + RTC_TAMP1 detection flag + 13 + 1 + read-write + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + + + ALRBF + Alarm B flag + 9 + 1 + read-write + + + ALRAF + Alarm A flag + 8 + 1 + read-write + + + INIT + Initialization mode + 7 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + RSF + Registers synchronization + flag + 5 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + + + PRER + PRER + RTC prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler + factor + 0 + 16 + + + + + WUTR + WUTR + RTC wakeup timer register + 0x14 + 0x20 + read-write + 0x00000000 + + + WUT + Wakeup auto-reload value + bits + 0 + 16 + + + + + ALRMAR + ALRMAR + RTC alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format. + 28 + 2 + + + DU + Date units or day in BCD + format. + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format. + 20 + 2 + + + HU + Hour units in BCD format. + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format. + 4 + 3 + + + SU + Second units in BCD + format. + 0 + 4 + + + + + ALRMBR + ALRMBR + RTC alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + SSR + SSR + RTC sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + RTC shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + + + TSTR + TSTR + RTC timestamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format. + 20 + 2 + + + HU + Hour units in BCD format. + 16 + 4 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + ST + Second tens in BCD format. + 4 + 3 + + + SU + Second units in BCD + format. + 0 + 4 + + + + + TSDR + TSDR + RTC timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + RTC time-stamp sub second + register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + RTC calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 + ppm + 15 + 1 + + + CALW8 + Use a 8-second calibration cycle + period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle + period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAMPCR + TAMPCR + RTC tamper configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP2MF + Tamper 2 mask flag + 21 + 1 + + + TAMP2NOERASE + Tamper 2 no erase + 20 + 1 + + + TAMP2IE + Tamper 2 interrupt enable + 19 + 1 + + + TAMP1MF + Tamper 1 mask flag + 18 + 1 + + + TAMP1NOERASE + Tamper 1 no erase + 17 + 1 + + + TAMP1IE + Tamper 1 interrupt enable + 16 + 1 + + + TAMPPUDIS + RTC_TAMPx pull-up disable + 15 + 1 + + + TAMPPRCH + RTC_TAMPx precharge + duration + 13 + 2 + + + TAMPFLT + RTC_TAMPx filter count + 11 + 2 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TAMP2_TRG + Active level for RTC_TAMP2 + input + 4 + 1 + + + TAMP2E + RTC_TAMP2 input detection + enable + 3 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for RTC_TAMP1 + input + 1 + 1 + + + TAMP1E + RTC_TAMP1 input detection + enable + 0 + 1 + + + + + ALRMASSR + ALRMASSR + RTC alarm A sub second + register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBSSR + ALRMBSSR + RTC alarm B sub second + register + 0x48 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + OR + OR + option register + 0x4C + 0x20 + read-write + 0x00000000 + + + RTC_OUT_RMP + RTC_ALARM on PC13 output + type + 1 + 1 + + + RTC_ALARM_TYPE + RTC_ALARM on PC13 output + type + 0 + 1 + + + + + BKP0R + BKP0R + RTC backup registers + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + RTC backup registers + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + RTC backup registers + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + RTC backup registers + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + RTC backup registers + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt + enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt + enable + 26 + 1 + + + DEAT4 + Driver Enable assertion + time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion + time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush + request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x00C0 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear + flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear + flag + 8 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + + + USART2 + 0x40004400 + + + USART4 + 0x40004C00 + + USART4_USART5 + USART4/USART5 global interrupt + 14 + + + USART1 + USART1 global interrupt + 27 + + + + USART5 + 0x40005000 + + USART2 + USART2 global interrupt + 28 + + + + TSC + Touch sensing controller + TSC + 0x40024000 + + 0x0 + 0x400 + registers + + + TSC + Touch sensing interrupt + 8 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CTPH + Charge transfer pulse high + 28 + 4 + + + CTPL + Charge transfer pulse low + 24 + 4 + + + SSD + Spread spectrum deviation + 17 + 7 + + + SSE + Spread spectrum enable + 16 + 1 + + + SSPSC + Spread spectrum prescaler + 15 + 1 + + + PGPSC + pulse generator prescaler + 12 + 3 + + + MCV + Max count value + 5 + 3 + + + IODEF + I/O Default mode + 4 + 1 + + + SYNCPOL + Synchronization pin + polarity + 3 + 1 + + + AM + Acquisition mode + 2 + 1 + + + START + Start a new acquisition + 1 + 1 + + + TSCE + Touch sensing controller + enable + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + MCEIE + Max count error interrupt + enable + 1 + 1 + + + EOAIE + End of acquisition interrupt + enable + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x8 + 0x20 + read-write + 0x00000000 + + + MCEIC + Max count error interrupt + clear + 1 + 1 + + + EOAIC + End of acquisition interrupt + clear + 0 + 1 + + + + + ISR + ISR + interrupt status register + 0xC + 0x20 + read-write + 0x00000000 + + + MCEF + Max count error flag + 1 + 1 + + + EOAF + End of acquisition flag + 0 + 1 + + + + + IOHCR + IOHCR + I/O hysteresis control + register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOASCR + IOASCR + I/O analog switch control + register + 0x18 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOSCR + IOSCR + I/O sampling control register + 0x20 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOCCR + IOCCR + I/O channel control register + 0x28 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOGCSR + IOGCSR + I/O group control status + register + 0x30 + 0x20 + 0x00000000 + + + G8S + Analog I/O group x status + 23 + 1 + read-only + + + G7S + Analog I/O group x status + 22 + 1 + read-only + + + G6S + Analog I/O group x status + 21 + 1 + read-only + + + G5S + Analog I/O group x status + 20 + 1 + read-only + + + G4S + Analog I/O group x status + 19 + 1 + read-only + + + G3S + Analog I/O group x status + 18 + 1 + read-only + + + G2S + Analog I/O group x status + 17 + 1 + read-only + + + G1S + Analog I/O group x status + 16 + 1 + read-only + + + G8E + Analog I/O group x enable + 7 + 1 + read-write + + + G7E + Analog I/O group x enable + 6 + 1 + read-write + + + G6E + Analog I/O group x enable + 5 + 1 + read-write + + + G5E + Analog I/O group x enable + 4 + 1 + read-write + + + G4E + Analog I/O group x enable + 3 + 1 + read-write + + + G3E + Analog I/O group x enable + 2 + 1 + read-write + + + G2E + Analog I/O group x enable + 1 + 1 + read-write + + + G1E + Analog I/O group x enable + 0 + 1 + read-write + + + + + IOG1CR + IOG1CR + I/O group x counter register + 0x34 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG2CR + IOG2CR + I/O group x counter register + 0x38 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG3CR + IOG3CR + I/O group x counter register + 0x3C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG4CR + IOG4CR + I/O group x counter register + 0x40 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG5CR + IOG5CR + I/O group x counter register + 0x44 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG6CR + IOG6CR + I/O group x counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG7CR + IOG7CR + I/O group x counter register + 0x4C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG8CR + IOG8CR + I/O group x counter register + 0x50 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read + 0x0000) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value + update + 2 + 1 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window + value + 0 + 12 + + + + + + + WWDG + System window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early wakeup interrupt + 9 + 1 + + + WDGTB1 + Timer base + 8 + 1 + + + WDGTB0 + WDGTB0 + 7 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + USB_FS + Universal serial bus full-speed device + interface + USB + 0x40005C00 + + 0x0 + 0x400 + registers + + + USB + USB event interrupt through + EXTI18 + 31 + + + + EP0R + EP0R + endpoint register + 0x0 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP1R + EP1R + endpoint register + 0x4 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP2R + EP2R + endpoint register + 0x8 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP3R + EP3R + endpoint register + 0xC + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP4R + EP4R + endpoint register + 0x10 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP5R + EP5R + endpoint register + 0x14 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP6R + EP6R + endpoint register + 0x18 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP7R + EP7R + endpoint register + 0x1C + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + CNTR + CNTR + control register + 0x40 + 0x20 + read-write + 0x0 + + + CTRM + CTRM + 15 + 1 + + + PMAOVRM + PMAOVRM + 14 + 1 + + + ERRM + ERRM + 13 + 1 + + + WKUPM + WKUPM + 12 + 1 + + + SUSPM + SUSPM + 11 + 1 + + + RESETM + RESETM + 10 + 1 + + + SOFM + SOFM + 9 + 1 + + + ESOFM + ESOFM + 8 + 1 + + + L1REQM + L1REQM + 7 + 1 + + + L1RESUME + L1RESUME + 5 + 1 + + + RESUME + RESUME + 4 + 1 + + + FSUSP + FSUSP + 3 + 1 + + + LPMODE + LPMODE + 2 + 1 + + + PDWN + PDWN + 1 + 1 + + + FRES + FRES + 0 + 1 + + + + + ISTR + ISTR + interrupt status register + 0x44 + 0x20 + read-write + 0x0 + + + CTR + CTR + 15 + 1 + + + PMAOVR + PMAOVR + 14 + 1 + + + ERR + ERR + 13 + 1 + + + WKUP + WKUP + 12 + 1 + + + SUSP + SUSP + 11 + 1 + + + RESET + RESET + 10 + 1 + + + SOF + SOF + 9 + 1 + + + ESOF + ESOF + 8 + 1 + + + L1REQ + L1REQ + 7 + 1 + + + DIR + DIR + 4 + 1 + + + EP_ID + EP_ID + 0 + 4 + + + + + FNR + FNR + frame number register + 0x48 + 0x20 + read-only + 0x0 + + + RXDP + RXDP + 15 + 1 + + + RXDM + RXDM + 14 + 1 + + + LCK + LCK + 13 + 1 + + + LSOF + LSOF + 11 + 2 + + + FN + FN + 0 + 11 + + + + + DADDR + DADDR + device address + 0x4C + 0x20 + read-write + 0x0 + + + EF + EF + 7 + 1 + + + ADD + ADD + 0 + 7 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x0 + + + BTABLE + BTABLE + 3 + 13 + + + + + LPMCSR + LPMCSR + LPM control and status + register + 0x54 + 0x20 + 0x0 + + + BESL + BESL + 4 + 4 + read-only + + + REMWAKE + REMWAKE + 3 + 1 + read-only + + + LPMACK + LPMACK + 1 + 1 + read-write + + + LPMEN + LPMEN + 0 + 1 + read-write + + + + + BCDR + BCDR + Battery charging detector + 0x58 + 0x20 + 0x0 + + + DPPU + DPPU + 15 + 1 + read-write + + + PS2DET + PS2DET + 7 + 1 + read-only + + + SDET + SDET + 6 + 1 + read-only + + + PDET + PDET + 5 + 1 + read-only + + + DCDET + DCDET + 4 + 1 + read-only + + + SDEN + SDEN + 3 + 1 + read-write + + + PDEN + PDEN + 2 + 1 + read-write + + + DCDEN + DCDEN + 1 + 1 + read-write + + + BCDEN + BCDEN + 0 + 1 + read-write + + + + + + + CRS + Clock recovery system + CRS + 0x40006C00 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00002000 + + + TRIM + HSI48 oscillator smooth + trimming + 8 + 6 + + + SWSYNC + Generate software SYNC + event + 7 + 1 + + + AUTOTRIMEN + Automatic trimming enable + 6 + 1 + + + CEN + Frequency error counter + enable + 5 + 1 + + + ESYNCIE + Expected SYNC interrupt + enable + 3 + 1 + + + ERRIE + Synchronization or trimming error + interrupt enable + 2 + 1 + + + SYNCWARNIE + SYNC warning interrupt + enable + 1 + 1 + + + SYNCOKIE + SYNC event OK interrupt + enable + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0x4 + 0x20 + read-write + 0x2022BB7F + + + SYNCPOL + SYNC polarity selection + 31 + 1 + + + SYNCSRC + SYNC signal source + selection + 28 + 2 + + + SYNCDIV + SYNC divider + 24 + 3 + + + FELIM + Frequency error limit + 16 + 8 + + + RELOAD + Counter reload value + 0 + 16 + + + + + ISR + ISR + interrupt and status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FECAP + Frequency error capture + 16 + 16 + + + FEDIR + Frequency error direction + 15 + 1 + + + TRIMOVF + Trimming overflow or + underflow + 10 + 1 + + + SYNCMISS + SYNC missed + 9 + 1 + + + SYNCERR + SYNC error + 8 + 1 + + + ESYNCF + Expected SYNC flag + 3 + 1 + + + ERRF + Error flag + 2 + 1 + + + SYNCWARNF + SYNC warning flag + 1 + 1 + + + SYNCOKF + SYNC event OK flag + 0 + 1 + + + + + ICR + ICR + interrupt flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + ESYNCC + Expected SYNC clear flag + 3 + 1 + + + ERRC + Error clear flag + 2 + 1 + + + SYNCWARNC + SYNC warning clear flag + 1 + 1 + + + SYNCOKC + SYNC event OK clear flag + 0 + 1 + + + + + + + Firewall + Firewall + Firewall + 0x40011C00 + + 0x0 + 0x400 + registers + + + + FIREWALL_CSSA + FIREWALL_CSSA + Code segment start address + 0x0 + 0x20 + read-write + 0x00000000 + + + ADD + code segment start address + 8 + 16 + + + + + FIREWALL_CSL + FIREWALL_CSL + Code segment length + 0x4 + 0x20 + read-write + 0x00000000 + + + LENG + code segment length + 8 + 14 + + + + + FIREWALL_NVDSSA + FIREWALL_NVDSSA + Non-volatile data segment start + address + 0x8 + 0x20 + read-write + 0x00000000 + + + ADD + Non-volatile data segment start + address + 8 + 16 + + + + + FIREWALL_NVDSL + FIREWALL_NVDSL + Non-volatile data segment + length + 0xC + 0x20 + read-write + 0x00000000 + + + LENG + Non-volatile data segment + length + 8 + 14 + + + + + FIREWALL_VDSSA + FIREWALL_VDSSA + Volatile data segment start + address + 0x10 + 0x20 + read-write + 0x00000000 + + + ADD + Volatile data segment start + address + 6 + 10 + + + + + FIREWALL_VDSL + FIREWALL_VDSL + Volatile data segment length + 0x14 + 0x20 + read-write + 0x00000000 + + + LENG + Non-volatile data segment + length + 6 + 10 + + + + + FIREWALL_CR + FIREWALL_CR + Configuration register + 0x20 + 0x20 + read-write + 0x00000000 + + + VDE + Volatile data execution + 2 + 1 + + + VDS + Volatile data shared + 1 + 1 + + + FPA + Firewall pre alarm + 0 + 1 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 4 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000300 + + + PLLRDY + PLL clock ready flag + 25 + 1 + read-only + + + PLLON + PLL enable bit + 24 + 1 + read-write + + + RTCPRE + TC/LCD prescaler + 20 + 2 + read-write + + + CSSLSEON + Clock security system on HSE enable + bit + 19 + 1 + read-write + + + HSEBYP + HSE clock bypass bit + 18 + 1 + read-write + + + HSERDY + HSE clock ready flag + 17 + 1 + read-only + + + HSEON + HSE clock enable bit + 16 + 1 + read-write + + + MSIRDY + MSI clock ready flag + 9 + 1 + read-only + + + MSION + MSI clock enable bit + 8 + 1 + read-write + + + HSI16DIVF + HSI16DIVF + 4 + 1 + read-only + + + HSI16DIVEN + HSI16DIVEN + 3 + 1 + read-write + + + HSI16RDYF + Internal high-speed clock ready + flag + 2 + 1 + read-write + + + HSI16KERON + High-speed internal clock enable bit for + some IP kernels + 1 + 1 + read-only + + + HSI16ON + 16 MHz high-speed internal clock + enable + 0 + 1 + read-write + + + HSI16OUTEN + 16 MHz high-speed internal clock output + enable + 5 + 1 + read-write + + + + + ICSCR + ICSCR + Internal clock sources calibration + register + 0x4 + 0x20 + 0x0000B000 + + + MSITRIM + MSI clock trimming + 24 + 8 + read-write + + + MSICAL + MSI clock calibration + 16 + 8 + read-only + + + MSIRANGE + MSI clock ranges + 13 + 3 + read-write + + + HSI16TRIM + High speed internal clock + trimming + 8 + 5 + read-write + + + HSI16CAL + nternal high speed clock + calibration + 0 + 8 + read-only + + + + + CRRCR + CRRCR + Clock recovery RC register + 0x8 + 0x20 + 0x00000000 + + + HSI48CAL + 48 MHz HSI clock + calibration + 8 + 8 + read-only + + + HSI48RDY + 48MHz HSI clock ready flag + 1 + 1 + read-only + + + HSI48ON + 48MHz HSI clock enable bit + 0 + 1 + read-write + + + HSI48DIV6EN + 48 MHz HSI clock divided by 6 output + enable + 2 + 1 + read-write + + + + + CFGR + CFGR + Clock configuration register + 0xC + 0x20 + 0x00000000 + + + MCOPRE + Microcontroller clock output + prescaler + 28 + 3 + read-write + + + MCOSEL + Microcontroller clock output + selection + 24 + 4 + read-write + + + PLLDIV + PLL output division + 22 + 2 + read-write + + + PLLMUL + PLL multiplication factor + 18 + 4 + read-write + + + PLLSRC + PLL entry clock source + 16 + 1 + read-write + + + STOPWUCK + Wake-up from stop clock + selection + 15 + 1 + read-write + + + PPRE2 + APB high-speed prescaler + (APB2) + 11 + 3 + read-write + + + PPRE1 + APB low-speed prescaler + (APB1) + 8 + 3 + read-write + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + SWS + System clock switch status + 2 + 2 + read-only + + + SW + System clock switch + 0 + 2 + read-write + + + + + CIER + CIER + Clock interrupt enable + register + 0x10 + 0x20 + read-only + 0x00000000 + + + CSSLSE + LSE CSS interrupt flag + 7 + 1 + + + HSI48RDYIE + HSI48 ready interrupt flag + 6 + 1 + + + MSIRDYIE + MSI ready interrupt flag + 5 + 1 + + + PLLRDYIE + PLL ready interrupt flag + 4 + 1 + + + HSERDYIE + HSE ready interrupt flag + 3 + 1 + + + HSI16RDYIE + HSI16 ready interrupt flag + 2 + 1 + + + LSERDYIE + LSE ready interrupt flag + 1 + 1 + + + LSIRDYIE + LSI ready interrupt flag + 0 + 1 + + + + + CIFR + CIFR + Clock interrupt flag register + 0x14 + 0x20 + read-only + 0x00000000 + + + CSSHSEF + Clock Security System Interrupt + flag + 8 + 1 + + + CSSLSEF + LSE Clock Security System Interrupt + flag + 7 + 1 + + + HSI48RDYF + HSI48 ready interrupt flag + 6 + 1 + + + MSIRDYF + MSI ready interrupt flag + 5 + 1 + + + PLLRDYF + PLL ready interrupt flag + 4 + 1 + + + HSERDYF + HSE ready interrupt flag + 3 + 1 + + + HSI16RDYF + HSI16 ready interrupt flag + 2 + 1 + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x18 + 0x20 + read-only + 0x00000000 + + + CSSHSEC + Clock Security System Interrupt + clear + 8 + 1 + + + CSSLSEC + LSE Clock Security System Interrupt + clear + 7 + 1 + + + HSI48RDYC + HSI48 ready Interrupt + clear + 6 + 1 + + + MSIRDYC + MSI ready Interrupt clear + 5 + 1 + + + PLLRDYC + PLL ready Interrupt clear + 4 + 1 + + + HSERDYC + HSE ready Interrupt clear + 3 + 1 + + + HSI16RDYC + HSI16 ready Interrupt + clear + 2 + 1 + + + LSERDYC + LSE ready Interrupt clear + 1 + 1 + + + LSIRDYC + LSI ready Interrupt clear + 0 + 1 + + + + + IOPRSTR + IOPRSTR + GPIO reset register + 0x1C + 0x20 + read-write + 0x00000000 + + + IOPHRST + I/O port H reset + 7 + 1 + + + IOPDRST + I/O port D reset + 3 + 1 + + + IOPCRST + I/O port A reset + 2 + 1 + + + IOPBRST + I/O port B reset + 1 + 1 + + + IOPARST + I/O port A reset + 0 + 1 + + + IOPERST + I/O port E reset + 4 + 1 + + + + + AHBRSTR + AHBRSTR + AHB peripheral reset register + 0x20 + 0x20 + read-write + 0x00000000 + + + CRYPRST + Crypto module reset + 24 + 1 + + + RNGRST + Random Number Generator module + reset + 20 + 1 + + + TOUCHRST + Touch Sensing reset + 16 + 1 + + + CRCRST + Test integration module + reset + 12 + 1 + + + MIFRST + Memory interface reset + 8 + 1 + + + DMARST + DMA reset + 0 + 1 + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x24 + 0x20 + read-write + 0x000000000 + + + DBGRST + DBG reset + 22 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + ADCRST + ADC interface reset + 9 + 1 + + + TM12RST + TIM22 timer reset + 5 + 1 + + + TIM21RST + TIM21 timer reset + 2 + 1 + + + SYSCFGRST + System configuration controller + reset + 0 + 1 + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + LPTIM1RST + Low power timer reset + 31 + 1 + + + DACRST + DAC interface reset + 29 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + CRSRST + Clock recovery system + reset + 27 + 1 + + + USBRST + USB reset + 23 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + LPUART1RST + LPUART1 reset + 18 + 1 + + + LPUART12RST + UART2 reset + 17 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + WWDRST + Window watchdog reset + 11 + 1 + + + TIM6RST + Timer 6 reset + 4 + 1 + + + TIM2RST + Timer2 reset + 0 + 1 + + + TIM3RST + Timer3 reset + 1 + 1 + + + TIM7RST + Timer 7 reset + 5 + 1 + + + USART4RST + USART4 reset + 19 + 1 + + + USART5RST + USART5 reset + 20 + 1 + + + I2C3RST + I2C3 reset + 30 + 1 + + + + + IOPENR + IOPENR + GPIO clock enable register + 0x2C + 0x20 + read-write + 0x00000000 + + + IOPHEN + I/O port H clock enable + bit + 7 + 1 + + + IOPDEN + I/O port D clock enable + bit + 3 + 1 + + + IOPCEN + IO port A clock enable bit + 2 + 1 + + + IOPBEN + IO port B clock enable bit + 1 + 1 + + + IOPAEN + IO port A clock enable bit + 0 + 1 + + + IOPEEN + I/O port E clock enable + bit + 4 + 1 + + + + + AHBENR + AHBENR + AHB peripheral clock enable + register + 0x30 + 0x20 + read-write + 0x00000100 + + + CRYPEN + Crypto clock enable bit + 24 + 1 + + + RNGEN + Random Number Generator clock enable + bit + 20 + 1 + + + TOUCHEN + Touch Sensing clock enable + bit + 16 + 1 + + + CRCEN + CRC clock enable bit + 12 + 1 + + + MIFEN + NVM interface clock enable + bit + 8 + 1 + + + DMAEN + DMA clock enable bit + 0 + 1 + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable + register + 0x34 + 0x20 + read-write + 0x00000000 + + + DBGEN + DBG clock enable bit + 22 + 1 + + + USART1EN + USART1 clock enable bit + 14 + 1 + + + SPI1EN + SPI1 clock enable bit + 12 + 1 + + + ADCEN + ADC clock enable bit + 9 + 1 + + + MIFIEN + MiFaRe Firewall clock enable + bit + 7 + 1 + + + TIM22EN + TIM22 timer clock enable + bit + 5 + 1 + + + TIM21EN + TIM21 timer clock enable + bit + 2 + 1 + + + SYSCFGEN + System configuration controller clock + enable bit + 0 + 1 + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + LPTIM1EN + Low power timer clock enable + bit + 31 + 1 + + + DACEN + DAC interface clock enable + bit + 29 + 1 + + + PWREN + Power interface clock enable + bit + 28 + 1 + + + CRSEN + Clock recovery system clock enable + bit + 27 + 1 + + + USBEN + USB clock enable bit + 23 + 1 + + + I2C2EN + I2C2 clock enable bit + 22 + 1 + + + I2C1EN + I2C1 clock enable bit + 21 + 1 + + + LPUART1EN + LPUART1 clock enable bit + 18 + 1 + + + USART2EN + UART2 clock enable bit + 17 + 1 + + + SPI2EN + SPI2 clock enable bit + 14 + 1 + + + WWDGEN + Window watchdog clock enable + bit + 11 + 1 + + + TIM6EN + Timer 6 clock enable bit + 4 + 1 + + + TIM2EN + Timer2 clock enable bit + 0 + 1 + + + TIM3EN + Timer3 clock enable bit + 1 + 1 + + + TIM7EN + Timer 7 clock enable bit + 5 + 1 + + + USART4EN + USART4 clock enable bit + 19 + 1 + + + USART5EN + USART5 clock enable bit + 20 + 1 + + + I2C3EN + I2C3 clock enable bit + 30 + 1 + + + + + IOPSMEN + IOPSMEN + GPIO clock enable in sleep mode + register + 0x3C + 0x20 + read-write + 0x0000008F + + + IOPHSMEN + IOPHSMEN + 7 + 1 + + + IOPDSMEN + IOPDSMEN + 3 + 1 + + + IOPCSMEN + IOPCSMEN + 2 + 1 + + + IOPBSMEN + IOPBSMEN + 1 + 1 + + + IOPASMEN + IOPASMEN + 0 + 1 + + + IOPESMEN + Port E clock enable during Sleep mode + bit + 4 + 1 + + + + + AHBSMENR + AHBSMENR + AHB peripheral clock enable in sleep mode + register + 0x40 + 0x20 + read-write + 0x01111301 + + + CRYPSMEN + Crypto clock enable during sleep mode + bit + 24 + 1 + + + RNGSMEN + Random Number Generator clock enable + during sleep mode bit + 20 + 1 + + + TOUCHSMEN + Touch Sensing clock enable during sleep + mode bit + 16 + 1 + + + CRCSMEN + CRC clock enable during sleep mode + bit + 12 + 1 + + + SRAMSMEN + SRAM interface clock enable during sleep + mode bit + 9 + 1 + + + MIFSMEN + NVM interface clock enable during sleep + mode bit + 8 + 1 + + + DMASMEN + DMA clock enable during sleep mode + bit + 0 + 1 + + + + + APB2SMENR + APB2SMENR + APB2 peripheral clock enable in sleep mode + register + 0x44 + 0x20 + read-write + 0x00405225 + + + DBGSMEN + DBG clock enable during sleep mode + bit + 22 + 1 + + + USART1SMEN + USART1 clock enable during sleep mode + bit + 14 + 1 + + + SPI1SMEN + SPI1 clock enable during sleep mode + bit + 12 + 1 + + + ADCSMEN + ADC clock enable during sleep mode + bit + 9 + 1 + + + TIM22SMEN + TIM22 timer clock enable during sleep + mode bit + 5 + 1 + + + TIM21SMEN + TIM21 timer clock enable during sleep + mode bit + 2 + 1 + + + SYSCFGSMEN + System configuration controller clock + enable during sleep mode bit + 0 + 1 + + + + + APB1SMENR + APB1SMENR + APB1 peripheral clock enable in sleep mode + register + 0x48 + 0x20 + read-write + 0xB8E64A11 + + + LPTIM1SMEN + Low power timer clock enable during + sleep mode bit + 31 + 1 + + + DACSMEN + DAC interface clock enable during sleep + mode bit + 29 + 1 + + + PWRSMEN + Power interface clock enable during + sleep mode bit + 28 + 1 + + + CRSSMEN + Clock recovery system clock enable + during sleep mode bit + 27 + 1 + + + USBSMEN + USB clock enable during sleep mode + bit + 23 + 1 + + + I2C2SMEN + I2C2 clock enable during sleep mode + bit + 22 + 1 + + + I2C1SMEN + I2C1 clock enable during sleep mode + bit + 21 + 1 + + + LPUART1SMEN + LPUART1 clock enable during sleep mode + bit + 18 + 1 + + + USART2SMEN + UART2 clock enable during sleep mode + bit + 17 + 1 + + + SPI2SMEN + SPI2 clock enable during sleep mode + bit + 14 + 1 + + + WWDGSMEN + Window watchdog clock enable during + sleep mode bit + 11 + 1 + + + TIM6SMEN + Timer 6 clock enable during sleep mode + bit + 4 + 1 + + + TIM2SMEN + Timer2 clock enable during sleep mode + bit + 0 + 1 + + + TIM3SMEN + Timer3 clock enable during Sleep mode + bit + 1 + 1 + + + TIM7SMEN + Timer 7 clock enable during Sleep mode + bit + 5 + 1 + + + USART4SMEN + USART4 clock enable during Sleep mode + bit + 19 + 1 + + + USART5SMEN + USART5 clock enable during Sleep mode + bit + 20 + 1 + + + I2C3SMEN + 2C3 clock enable during Sleep mode + bit + 30 + 1 + + + + + CCIPR + CCIPR + Clock configuration register + 0x4C + 0x20 + read-write + 0x00000000 + + + HSI48MSEL + 48 MHz HSI48 clock source selection + bit + 26 + 1 + + + LPTIM1SEL1 + Low Power Timer clock source selection + bits + 19 + 1 + + + LPTIM1SEL0 + LPTIM1SEL0 + 18 + 1 + + + I2C1SEL1 + I2C1 clock source selection + bits + 13 + 1 + + + I2C1SEL0 + I2C1SEL0 + 12 + 1 + + + LPUART1SEL1 + LPUART1 clock source selection + bits + 11 + 1 + + + LPUART1SEL0 + LPUART1SEL0 + 10 + 1 + + + USART2SEL1 + USART2 clock source selection + bits + 3 + 1 + + + USART2SEL0 + USART2SEL0 + 2 + 1 + + + USART1SEL1 + USART1 clock source selection + bits + 1 + 1 + + + USART1SEL0 + USART1SEL0 + 0 + 1 + + + I2C3SEL + I2C3 clock source selection + bits + 16 + 2 + + + + + CSR + CSR + Control and status register + 0x50 + 0x20 + 0x0C000000 + + + LPWRSTF + Low-power reset flag + 31 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + IWDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + PINRSTF + PIN reset flag + 26 + 1 + read-write + + + OBLRSTF + OBLRSTF + 25 + 1 + read-write + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + RTCRST + RTC software reset bit + 19 + 1 + read-write + + + RTCEN + RTC clock enable bit + 18 + 1 + read-write + + + RTCSEL + RTC and LCD clock source selection + bits + 16 + 2 + read-write + + + CSSLSED + CSS on LSE failure detection + flag + 14 + 1 + read-write + + + CSSLSEON + CSSLSEON + 13 + 1 + read-write + + + LSEDRV + LSEDRV + 11 + 2 + read-write + + + LSEBYP + External low-speed oscillator bypass + bit + 10 + 1 + read-write + + + LSERDY + External low-speed oscillator ready + bit + 9 + 1 + read-only + + + LSEON + External low-speed oscillator enable + bit + 8 + 1 + read-write + + + LSIRDY + Internal low-speed oscillator ready + bit + 1 + 1 + read-write + + + LSION + Internal low-speed oscillator + enable + 0 + 1 + read-write + + + + + + + SYSCFG_COMP + System configuration controller and + Comparator + SYSCFG + 0x40010000 + + 0x0 + 0x400 + registers + + + + CFGR1 + CFGR1 + SYSCFG configuration register + 1 + 0x0 + 0x20 + 0x00000000 + + + BOOT_MODE + Boot mode selected by the boot pins + status bits + 8 + 2 + read-only + + + MEM_MODE + Memory mapping selection + bits + 0 + 2 + read-write + + + + + CFGR2 + CFGR2 + SYSCFG configuration register + 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + I2C2_FMP + I2C2 Fm+ drive capability enable + bit + 13 + 1 + + + I2C1_FMP + I2C1 Fm+ drive capability enable + bit + 12 + 1 + + + I2C_PB9_FMP + Fm+ drive capability on PB9 enable + bit + 11 + 1 + + + I2C_PB8_FMP + Fm+ drive capability on PB8 enable + bit + 10 + 1 + + + I2C_PB7_FMP + Fm+ drive capability on PB7 enable + bit + 9 + 1 + + + I2C_PB6_FMP + Fm+ drive capability on PB6 enable + bit + 8 + 1 + + + FWDISEN + Firewall disable bit + 0 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to + 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to + 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to + 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to + 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to + 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to + 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to + 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to + 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to + 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to + 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to + 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to + 15) + 12 + 4 + + + EXTI14 + EXTI14 + 8 + 4 + + + EXTI13 + EXTI13 + 4 + 4 + + + EXTI12 + EXTI12 + 0 + 4 + + + + + CFGR3 + CFGR3 + SYSCFG configuration register + 3 + 0x20 + 0x20 + 0x00000000 + + + REF_LOCK + REF_CTRL lock bit + 31 + 1 + write-only + + + VREFINT_RDYF + VREFINT ready flag + 30 + 1 + read-only + + + VREFINT_COMP_RDYF + VREFINT for comparator ready + flag + 29 + 1 + read-only + + + VREFINT_ADC_RDYF + VREFINT for ADC ready flag + 28 + 1 + read-only + + + SENSOR_ADC_RDYF + Sensor for ADC ready flag + 27 + 1 + read-only + + + REF_RC48MHz_RDYF + VREFINT for 48 MHz RC oscillator ready + flag + 26 + 1 + read-only + + + ENREF_RC48MHz + VREFINT reference for 48 MHz RC + oscillator enable bit + 13 + 1 + read-write + + + ENBUF_VREFINT_COMP + VREFINT reference for comparator 2 + enable bit + 12 + 1 + read-write + + + ENBUF_SENSOR_ADC + Sensor reference for ADC enable + bit + 9 + 1 + read-write + + + ENBUF_BGAP_ADC + VREFINT reference for ADC enable + bit + 8 + 1 + read-write + + + SEL_VREF_OUT + BGAP_ADC connection bit + 4 + 2 + read-write + + + EN_BGAP + Vref Enable bit + 0 + 1 + read-write + + + + + COMP1_CSR + COMP1_CSR + Comparator 1 control and status + register + 0x18 + 0x20 + 0x00000000 + + + COMP1LOCK + COMP1_CSR register lock + bit + 31 + 1 + read-only + + + COMP1VALUE + Comparator 1 output status + bit + 30 + 1 + read-only + + + COMP1POLARITY + Comparator 1 polarity selection + bit + 15 + 1 + read-write + + + COMP1LPTIMIN1 + Comparator 1 LPTIM input propagation + bit + 12 + 1 + read-write + + + COMP1WM + Comparator 1 window mode selection + bit + 8 + 1 + read-write + + + COMP1INNSEL + Comparator 1 Input Minus connection + configuration bit + 4 + 2 + read-write + + + COMP1EN + Comparator 1 enable bit + 0 + 1 + read-write + + + + + COMP2_CSR + COMP2_CSR + Comparator 2 control and status + register + 0x1C + 0x20 + 0x00000000 + + + COMP2LOCK + COMP2_CSR register lock + bit + 31 + 1 + read-only + + + COMP2VALUE + Comparator 2 output status + bit + 20 + 1 + read-only + + + COMP2POLARITY + Comparator 2 polarity selection + bit + 15 + 1 + read-write + + + COMP2LPTIMIN1 + Comparator 2 LPTIM input 1 propagation + bit + 13 + 1 + read-write + + + COMP2LPTIMIN2 + Comparator 2 LPTIM input 2 propagation + bit + 12 + 1 + read-write + + + COMP2INPSEL + Comparator 2 Input Plus connection + configuration bit + 8 + 3 + read-write + + + COMP2INNSEL + Comparator 2 Input Minus connection + configuration bit + 4 + 3 + read-write + + + COMP2SPEED + Comparator 2 power mode selection + bit + 3 + 1 + read-write + + + COMP2EN + Comparator 2 enable bit + 0 + 1 + read-write + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + SSOE + SS output enable + 2 + 1 + + + FRF + Frame format + 4 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + CHSIDE + Channel side + 2 + 1 + read-only + + + UDR + Underrun flag + 3 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + MODF + Mode fault + 5 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMOD + I2S mode selection + 11 + 1 + + + I2SE + I2S Enable + 10 + 1 + + + I2SCFG + I2S configuration mode + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPOL + Steady state clock + polarity + 3 + 1 + + + DATLEN + Data length to be + transferred + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 0x00000010 + + + MCKOE + Master clock output enable + 9 + 1 + + + ODD + Odd factor for the + prescaler + 8 + 1 + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI1 + SPI1_global_interrupt + 25 + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + SPI2 + SPI2 global interrupt + 26 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match interrupt enable (slave + only) + 3 + 1 + + + NACKIE + Not acknowledge received interrupt + enable + 4 + 1 + + + STOPIE + STOP detection Interrupt + enable + 5 + 1 + + + TCIE + Transfer Complete interrupt + enable + 6 + 1 + + + ERRIE + Error interrupts enable + 7 + 1 + + + DNF + Digital noise filter + 8 + 4 + + + ANFOFF + Analog noise filter OFF + 12 + 1 + + + TXDMAEN + DMA transmission requests + enable + 14 + 1 + + + RXDMAEN + DMA reception requests + enable + 15 + 1 + + + SBC + Slave byte control + 16 + 1 + + + NOSTRETCH + Clock stretching disable + 17 + 1 + + + WUPEN + Wakeup from STOP enable + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable + 20 + 1 + + + SMBDEN + SMBus Device Default address + enable + 21 + 1 + + + ALERTEN + SMBUS alert enable + 22 + 1 + + + PECEN + PEC enable + 23 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master + mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave + mode) + 15 + 1 + + + STOP + Stop generation (master + mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read + direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master + mode) + 11 + 1 + + + RD_WRN + Transfer direction (master + mode) + 10 + 1 + + + SADD + Slave address bit (master + mode) + 0 + 10 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master + mode) + 0 + 8 + + + SCLH + SCL high period (master + mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout + detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout + enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave + mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave + mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection + flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave + mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master + mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received + flag + 4 + 1 + read-only + + + ADDR + Address matched (slave + mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty + (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status + (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty + (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag + clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag + clear + 10 + 1 + + + ARLOCF + Arbitration lost flag + clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking + register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C1 + I2C1 global interrupt + 23 + + + I2C2 + I2C2 global interrupt + 24 + + + + I2C3 + 0x40007800 + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + I2C3 + I2C3 global interrupt + 21 + + + + CR + CR + power control register + 0x0 + 0x20 + read-write + 0x00001000 + + + LPDS + Low-power deep sleep + 0 + 1 + + + PDDS + Power down deepsleep + 1 + 1 + + + CWUF + Clear wakeup flag + 2 + 1 + + + CSBF + Clear standby flag + 3 + 1 + + + PVDE + Power voltage detector + enable + 4 + 1 + + + PLS + PVD level selection + 5 + 3 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + ULP + Ultra-low-power mode + 9 + 1 + + + FWU + Fast wakeup + 10 + 1 + + + VOS + Voltage scaling range + selection + 11 + 2 + + + DS_EE_KOFF + Deep sleep mode with Flash memory kept + off + 13 + 1 + + + LPRUN + Low power run mode + 14 + 1 + + + + + CSR + CSR + power control/status register + 0x4 + 0x20 + 0x00000000 + + + BRE + Backup regulator enable + 9 + 1 + read-write + + + EWUP + Enable WKUP pin + 8 + 1 + read-write + + + BRR + Backup regulator ready + 3 + 1 + read-only + + + PVDO + PVD output + 2 + 1 + read-only + + + SBF + Standby flag + 1 + 1 + read-only + + + WUF + Wakeup flag + 0 + 1 + read-only + + + VOSF + Voltage Scaling select + flag + 4 + 1 + read-only + + + REGLPF + Regulator LP flag + 5 + 1 + read-only + + + + + + + Flash + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LATENCY + Latency + 0 + 1 + + + PRFTEN + Prefetch enable + 1 + 1 + + + SLEEP_PD + Flash mode during Sleep + 3 + 1 + + + RUN_PD + Flash mode during Run + 4 + 1 + + + DESAB_BUF + Disable Buffer + 5 + 1 + + + PRE_READ + Pre-read data address + 6 + 1 + + + + + PECR + PECR + Program/erase control register + 0x4 + 0x20 + read-write + 0x00000007 + + + PELOCK + FLASH_PECR and data EEPROM + lock + 0 + 1 + + + PRGLOCK + Program memory lock + 1 + 1 + + + OPTLOCK + Option bytes block lock + 2 + 1 + + + PROG + Program memory selection + 3 + 1 + + + DATA + Data EEPROM selection + 4 + 1 + + + FTDW + Fixed time data write for Byte, Half + Word and Word programming + 8 + 1 + + + ERASE + Page or Double Word erase + mode + 9 + 1 + + + FPRG + Half Page/Double Word programming + mode + 10 + 1 + + + PARALLELBANK + Parallel bank mode + 15 + 1 + + + EOPIE + End of programming interrupt + enable + 16 + 1 + + + ERRIE + Error interrupt enable + 17 + 1 + + + OBL_LAUNCH + Launch the option byte + loading + 18 + 1 + + + + + PDKEYR + PDKEYR + Power down key register + 0x8 + 0x20 + write-only + 0x00000000 + + + PDKEYR + RUN_PD in FLASH_ACR key + 0 + 32 + + + + + PEKEYR + PEKEYR + Program/erase key register + 0xC + 0x20 + write-only + 0x00000000 + + + PEKEYR + FLASH_PEC and data EEPROM + key + 0 + 32 + + + + + PRGKEYR + PRGKEYR + Program memory key register + 0x10 + 0x20 + write-only + 0x00000000 + + + PRGKEYR + Program memory key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0x14 + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x18 + 0x20 + 0x00000004 + + + BSY + Write/erase operations in + progress + 0 + 1 + read-only + + + EOP + End of operation + 1 + 1 + read-only + + + ENDHV + End of high voltage + 2 + 1 + read-only + + + READY + Flash memory module ready after low + power mode + 3 + 1 + read-only + + + WRPERR + Write protected error + 8 + 1 + read-write + + + PGAERR + Programming alignment + error + 9 + 1 + read-write + + + SIZERR + Size error + 10 + 1 + read-write + + + OPTVERR + Option validity error + 11 + 1 + read-write + + + RDERR + RDERR + 14 + 1 + read-write + + + NOTZEROERR + NOTZEROERR + 16 + 1 + read-write + + + FWWERR + FWWERR + 17 + 1 + read-write + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0x00F80000 + + + RDPRT + Read protection + 0 + 8 + + + BOR_LEV + BOR_LEV + 16 + 4 + + + SPRMOD + Selection of protection mode of WPR + bits + 8 + 1 + + + + + WRPR + WRPR + Write protection register + 0x20 + 0x20 + read-write + 0x00000000 + + + WRP + Write protection + 0 + 16 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + 1 + + + EXTI0_1 + EXTI Line[1:0] interrupts + 5 + + + EXTI2_3 + EXTI Line[3:2] interrupts + 6 + + + EXTI4_15 + EXTI Line15 and EXTI4 interrupts + 7 + + + + IMR + IMR + Interrupt mask register + (EXTI_IMR) + 0x0 + 0x20 + read-write + 0xFF840000 + + + IM0 + Interrupt Mask on line 0 + 0 + 1 + + + IM1 + Interrupt Mask on line 1 + 1 + 1 + + + IM2 + Interrupt Mask on line 2 + 2 + 1 + + + IM3 + Interrupt Mask on line 3 + 3 + 1 + + + IM4 + Interrupt Mask on line 4 + 4 + 1 + + + IM5 + Interrupt Mask on line 5 + 5 + 1 + + + IM6 + Interrupt Mask on line 6 + 6 + 1 + + + IM7 + Interrupt Mask on line 7 + 7 + 1 + + + IM8 + Interrupt Mask on line 8 + 8 + 1 + + + IM9 + Interrupt Mask on line 9 + 9 + 1 + + + IM10 + Interrupt Mask on line 10 + 10 + 1 + + + IM11 + Interrupt Mask on line 11 + 11 + 1 + + + IM12 + Interrupt Mask on line 12 + 12 + 1 + + + IM13 + Interrupt Mask on line 13 + 13 + 1 + + + IM14 + Interrupt Mask on line 14 + 14 + 1 + + + IM15 + Interrupt Mask on line 15 + 15 + 1 + + + IM16 + Interrupt Mask on line 16 + 16 + 1 + + + IM17 + Interrupt Mask on line 17 + 17 + 1 + + + IM18 + Interrupt Mask on line 18 + 18 + 1 + + + IM19 + Interrupt Mask on line 19 + 19 + 1 + + + IM20 + Interrupt Mask on line 20 + 20 + 1 + + + IM21 + Interrupt Mask on line 21 + 21 + 1 + + + IM22 + Interrupt Mask on line 22 + 22 + 1 + + + IM23 + Interrupt Mask on line 23 + 23 + 1 + + + IM24 + Interrupt Mask on line 24 + 24 + 1 + + + IM25 + Interrupt Mask on line 25 + 25 + 1 + + + IM26 + Interrupt Mask on line 27 + 26 + 1 + + + IM28 + Interrupt Mask on line 27 + 28 + 1 + + + IM29 + Interrupt Mask on line 27 + 29 + 1 + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + EM0 + Event Mask on line 0 + 0 + 1 + + + EM1 + Event Mask on line 1 + 1 + 1 + + + EM2 + Event Mask on line 2 + 2 + 1 + + + EM3 + Event Mask on line 3 + 3 + 1 + + + EM4 + Event Mask on line 4 + 4 + 1 + + + EM5 + Event Mask on line 5 + 5 + 1 + + + EM6 + Event Mask on line 6 + 6 + 1 + + + EM7 + Event Mask on line 7 + 7 + 1 + + + EM8 + Event Mask on line 8 + 8 + 1 + + + EM9 + Event Mask on line 9 + 9 + 1 + + + EM10 + Event Mask on line 10 + 10 + 1 + + + EM11 + Event Mask on line 11 + 11 + 1 + + + EM12 + Event Mask on line 12 + 12 + 1 + + + EM13 + Event Mask on line 13 + 13 + 1 + + + EM14 + Event Mask on line 14 + 14 + 1 + + + EM15 + Event Mask on line 15 + 15 + 1 + + + EM16 + Event Mask on line 16 + 16 + 1 + + + EM17 + Event Mask on line 17 + 17 + 1 + + + EM18 + Event Mask on line 18 + 18 + 1 + + + EM19 + Event Mask on line 19 + 19 + 1 + + + EM20 + Event Mask on line 20 + 20 + 1 + + + EM21 + Event Mask on line 21 + 21 + 1 + + + EM22 + Event Mask on line 22 + 22 + 1 + + + EM23 + Event Mask on line 23 + 23 + 1 + + + EM24 + Event Mask on line 24 + 24 + 1 + + + EM25 + Event Mask on line 25 + 25 + 1 + + + EM26 + Event Mask on line 26 + 26 + 1 + + + EM28 + Event Mask on line 28 + 28 + 1 + + + EM29 + Event Mask on line 29 + 29 + 1 + + + + + RTSR + RTSR + Rising Trigger selection register + (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + RT0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + RT1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + RT2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + RT3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + RT4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + RT5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + RT6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + RT7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + RT8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + RT9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + RT10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + RT11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + RT12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + RT13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + RT14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + RT15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + RT16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + RT17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + RT19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + RT20 + Rising trigger event configuration of + line 20 + 20 + 1 + + + RT21 + Rising trigger event configuration of + line 21 + 21 + 1 + + + RT22 + Rising trigger event configuration of + line 22 + 22 + 1 + + + + + FTSR + FTSR + Falling Trigger selection register + (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + FT0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + FT1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + FT2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + FT3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + FT4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + FT5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + FT6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + FT7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + FT8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + FT9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + FT10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + FT11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + FT12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + FT13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + FT14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + FT15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + FT16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + FT17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + FT19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + FT20 + Falling trigger event configuration of + line 20 + 20 + 1 + + + FT21 + Falling trigger event configuration of + line 21 + 21 + 1 + + + FT22 + Falling trigger event configuration of + line 22 + 22 + 1 + + + + + SWIER + SWIER + Software interrupt event register + (EXTI_SWIER) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWI0 + Software Interrupt on line + 0 + 0 + 1 + + + SWI1 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20 + 1 + + + SWI21 + Software Interrupt on line + 21 + 21 + 1 + + + SWI22 + Software Interrupt on line + 22 + 22 + 1 + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PIF0 + Pending bit 0 + 0 + 1 + + + PIF1 + Pending bit 1 + 1 + 1 + + + PIF2 + Pending bit 2 + 2 + 1 + + + PIF3 + Pending bit 3 + 3 + 1 + + + PIF4 + Pending bit 4 + 4 + 1 + + + PIF5 + Pending bit 5 + 5 + 1 + + + PIF6 + Pending bit 6 + 6 + 1 + + + PIF7 + Pending bit 7 + 7 + 1 + + + PIF8 + Pending bit 8 + 8 + 1 + + + PIF9 + Pending bit 9 + 9 + 1 + + + PIF10 + Pending bit 10 + 10 + 1 + + + PIF11 + Pending bit 11 + 11 + 1 + + + PIF12 + Pending bit 12 + 12 + 1 + + + PIF13 + Pending bit 13 + 13 + 1 + + + PIF14 + Pending bit 14 + 14 + 1 + + + PIF15 + Pending bit 15 + 15 + 1 + + + PIF16 + Pending bit 16 + 16 + 1 + + + PIF17 + Pending bit 17 + 17 + 1 + + + PIF19 + Pending bit 19 + 19 + 1 + + + PIF20 + Pending bit 20 + 20 + 1 + + + PIF21 + Pending bit 21 + 21 + 1 + + + PIF22 + Pending bit 22 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Channel-x selection + 18 + 1 + + + CHSEL17 + Channel-x selection + 17 + 1 + + + CHSEL16 + Channel-x selection + 16 + 1 + + + CHSEL15 + Channel-x selection + 15 + 1 + + + CHSEL14 + Channel-x selection + 14 + 1 + + + CHSEL13 + Channel-x selection + 13 + 1 + + + CHSEL12 + Channel-x selection + 12 + 1 + + + CHSEL11 + Channel-x selection + 11 + 1 + + + CHSEL10 + Channel-x selection + 10 + 1 + + + CHSEL9 + Channel-x selection + 9 + 1 + + + CHSEL8 + Channel-x selection + 8 + 1 + + + CHSEL7 + Channel-x selection + 7 + 1 + + + CHSEL6 + Channel-x selection + 6 + 1 + + + CHSEL5 + Channel-x selection + 5 + 1 + + + CHSEL4 + Channel-x selection + 4 + 1 + + + CHSEL3 + Channel-x selection + 3 + 1 + + + CHSEL2 + Channel-x selection + 2 + 1 + + + CHSEL1 + Channel-x selection + 1 + 1 + + + CHSEL0 + Channel-x selection + 0 + 1 + + + + + DR + DR + data register + 0x40 + 0x20 + read-only + 0x00000000 + + + DATA + Converted data + 0 + 16 + + + + + CALFACT + CALFACT + ADC Calibration factor + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT + Calibration factor + 0 + 7 + + + + + CCR + CCR + ADC common configuration + register + 0x308 + 0x20 + read-write + 0x00000000 + + + PRESC + ADC prescaler + 18 + 4 + + + VREFEN + VREFINT enable + 22 + 1 + + + TSEN + Temperature sensor enable + 23 + 1 + + + LFMEN + Low Frequency Mode enable + 25 + 1 + + + + + + + DBGMCU + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + ADC_COMP + ADC and comparator 1 and 2 + 12 + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 12 + + + REV_ID + Revision Identifier + 16 + 16 + + + + + CR + CR + Debug MCU Configuration + Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + DBG_SLEEP + Debug Sleep Mode + 0 + 1 + + + + + APB1_FZ + APB1_FZ + APB Low Freeze Register + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER2_STOP + Debug Timer 2 stopped when Core is + halted + 0 + 1 + + + DBG_TIMER6_STOP + Debug Timer 6 stopped when Core is + halted + 4 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is + halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core + is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when + Core is halted + 12 + 1 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout mode stopped when + core is halted + 21 + 1 + + + DBG_I2C2_STOP + I2C2 SMBUS timeout mode stopped when + core is halted + 22 + 1 + + + DBG_LPTIMER_STOP + LPTIM1 counter stopped when core is + halted + 31 + 1 + + + + + APB2_FZ + APB2_FZ + APB High Freeze Register + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIMER21_STOP + Debug Timer 21 stopped when Core is + halted + 2 + 1 + + + DBG_TIMER22_STO + Debug Timer 22 stopped when Core is + halted + 6 + 1 + + + + + + + TIM2 + General-purpose-timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 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TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt 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1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + OR + OR + TIM21 option register + 0x50 + 0x20 + read-write + 0x00000000 + + + ETR_RMP + Timer21 ETR remap + 0 + 2 + + + TI1_RMP + Timer21 TI1 + 2 + 3 + + + TI2_RMP + Timer21 TI2 + 5 + 1 + + + + + + + TIM22 + General-purpose-timers + TIM + 0x40011400 + + 0x0 + 0x400 + registers + + + TIM21 + TIMER21 global interrupt + 20 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + DIR + Direction + 4 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS + Slave mode selection + 0 + 3 + + + TS + Trigger selection + 4 + 3 + + + MSM + Master/Slave mode + 7 + 1 + + + ETF + External trigger filter + 8 + 4 + + + ETPS + External trigger prescaler + 12 + 2 + + + ECE + External clock enable + 14 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + OR + OR + TIM22 option register + 0x50 + 0x20 + read-write + 0x00000000 + + + ETR_RMP + Timer22 ETR remap + 0 + 2 + + + TI1_RMP + Timer22 TI1 + 2 + 2 + + + + + + + LPUSART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40004800 + + 0x0 + 0x400 + registers + + + TIM22 + TIMER22 global interrupt + 22 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + M1 + Word length + 28 + 1 + + + DEAT4 + Driver Enable assertion + time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion + time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR + BRR + 0 + 20 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + + + ISR + ISR + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x00C0 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E100 + + 0x0 + 0x33D + registers + + + + ISER + ISER + Interrupt Set Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER + ICER + Interrupt Clear Enable + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR + ISPR + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR + ICPR + Interrupt Clear-Pending + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register 0 + 0x300 + 0x20 + read-write + 0x00000000 + + + PRI_0 + priority for interrupt 0 + 0 + 8 + + + PRI_1 + priority for interrupt 1 + 8 + 8 + + + PRI_2 + priority for interrupt 2 + 16 + 8 + + + PRI_3 + priority for interrupt 3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register 1 + 0x304 + 0x20 + read-write + 0x00000000 + + + PRI_4 + priority for interrupt n + 0 + 8 + + + PRI_5 + priority for interrupt n + 8 + 8 + + + PRI_6 + priority for interrupt n + 16 + 8 + + + PRI_7 + priority for interrupt n + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register 2 + 0x308 + 0x20 + read-write + 0x00000000 + + + PRI_8 + priority for interrupt n + 0 + 8 + + + PRI_9 + priority for interrupt n + 8 + 8 + + + PRI_10 + priority for interrupt n + 16 + 8 + + + PRI_11 + priority for interrupt n + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register 3 + 0x30C + 0x20 + read-write + 0x00000000 + + + PRI_12 + priority for interrupt n + 0 + 8 + + + PRI_13 + priority for interrupt n + 8 + 8 + + + PRI_14 + priority for interrupt n + 16 + 8 + + + PRI_15 + priority for interrupt n + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register 4 + 0x310 + 0x20 + read-write + 0x00000000 + + + PRI_16 + priority for interrupt n + 0 + 8 + + + PRI_17 + priority for interrupt n + 8 + 8 + + + PRI_18 + priority for interrupt n + 16 + 8 + + + PRI_19 + priority for interrupt n + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register 5 + 0x314 + 0x20 + read-write + 0x00000000 + + + PRI_20 + priority for interrupt n + 0 + 8 + + + PRI_21 + priority for interrupt n + 8 + 8 + + + PRI_22 + priority for interrupt n + 16 + 8 + + + PRI_23 + priority for interrupt n + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register 6 + 0x318 + 0x20 + read-write + 0x00000000 + + + PRI_24 + priority for interrupt n + 0 + 8 + + + PRI_25 + priority for interrupt n + 8 + 8 + + + PRI_26 + priority for interrupt n + 16 + 8 + + + PRI_27 + priority for interrupt n + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register 7 + 0x31C + 0x20 + read-write + 0x00000000 + + + PRI_28 + priority for interrupt n + 0 + 8 + + + PRI_29 + priority for interrupt n + 8 + 8 + + + PRI_30 + priority for interrupt n + 16 + 8 + + + PRI_31 + priority for interrupt n + 24 + 8 + + + + + + + USB_SRAM + Universal serial bus full-speed device + interface + USB + 0x40006000 + + 0x0 + 0x800 + registers + + + + EP0R + EP0R + endpoint 0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP1R + EP1R + endpoint 1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP2R + EP2R + endpoint 2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP3R + EP3R + endpoint 3 register + 0xC + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP4R + EP4R + endpoint 4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP5R + EP5R + endpoint 5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP6R + EP6R + endpoint 6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP7R + EP7R + endpoint 7 register + 0x1C + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + CNTR + CNTR + control register + 0x40 + 0x20 + read-write + 0x00000003 + + + FRES + Force USB Reset + 0 + 1 + + + PDWN + Power down + 1 + 1 + + + LPMODE + Low-power mode + 2 + 1 + + + FSUSP + Force suspend + 3 + 1 + + + RESUME + Resume request + 4 + 1 + + + L1RESUME + LPM L1 Resume request + 5 + 1 + + + L1REQM + LPM L1 state request interrupt + mask + 7 + 1 + + + ESOFM + Expected start of frame interrupt + mask + 8 + 1 + + + SOFM + Start of frame interrupt + mask + 9 + 1 + + + RESETM + USB reset interrupt mask + 10 + 1 + + + SUSPM + Suspend mode interrupt + mask + 11 + 1 + + + WKUPM + Wakeup interrupt mask + 12 + 1 + + + ERRM + Error interrupt mask + 13 + 1 + + + PMAOVRM + Packet memory area over / underrun + interrupt mask + 14 + 1 + + + CTRM + Correct transfer interrupt + mask + 15 + 1 + + + + + ISTR + ISTR + interrupt status register + 0x44 + 0x20 + 0x00000000 + + + EP_ID + Endpoint Identifier + 0 + 4 + read-only + + + DIR + Direction of transaction + 4 + 1 + read-only + + + L1REQ + LPM L1 state request + 7 + 1 + read-write + + + ESOF + Expected start frame + 8 + 1 + read-write + + + SOF + start of frame + 9 + 1 + read-write + + + RESET + reset request + 10 + 1 + read-write + + + SUSP + Suspend mode request + 11 + 1 + read-write + + + WKUP + Wakeup + 12 + 1 + read-write + + + ERR + Error + 13 + 1 + read-write + + + PMAOVR + Packet memory area over / + underrun + 14 + 1 + read-write + + + CTR + Correct transfer + 15 + 1 + read-only + + + + + FNR + FNR + frame number register + 0x48 + 0x20 + read-only + 0x0000 + + + FN + Frame number + 0 + 11 + + + LSOF + Lost SOF + 11 + 2 + + + LCK + Locked + 13 + 1 + + + RXDM + Receive data - line status + 14 + 1 + + + RXDP + Receive data + line status + 15 + 1 + + + + + DADDR + DADDR + device address + 0x4C + 0x20 + read-write + 0x0000 + + + ADD + Device address + 0 + 7 + + + EF + Enable function + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTABLE + Buffer table + 3 + 13 + + + + + LPMCSR + LPMCSR + LPM control and status + register + 0x54 + 0x20 + 0x0000 + + + LPMEN + LPM support enable + 0 + 1 + read-write + + + LPMACK + LPM Token acknowledge + enable + 1 + 1 + read-write + + + REMWAKE + bRemoteWake value + 3 + 1 + read-only + + + BESL + BESL value + 4 + 4 + read-only + + + + + BCDR + BCDR + Battery charging detector + 0x58 + 0x20 + 0x0000 + + + BCDEN + Battery charging detector + 0 + 1 + read-write + + + DCDEN + Data contact detection + 1 + 1 + read-write + + + PDEN + Primary detection + 2 + 1 + read-write + + + SDEN + Secondary detection + 3 + 1 + read-write + + + DCDET + Data contact detection + 4 + 1 + read-only + + + PDET + Primary detection + 5 + 1 + read-only + + + SDET + Secondary detection + 6 + 1 + read-only + + + PS2DET + DM pull-up detection + status + 7 + 1 + read-only + + + DPPU + DP pull-up control + 15 + 1 + read-write + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + MPU_TYPER + MPU_TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction + regions + 16 + 8 + + + + + MPU_CTRL + MPU_CTRL + MPU control register + 0x4 + 0x20 + read-only + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard + fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to + default memory map + 2 + 1 + + + + + MPU_RNR + MPU_RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + MPU_RBAR + MPU_RBAR + MPU region base address + register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + MPU_RASR + MPU_RASR + MPU region attribute and size + register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection + region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable + bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CSR + CSR + SysTick control and status + register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request + enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + RVR + RVR + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + CVR + CVR + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value + register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS + value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Architecture + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 7 + 25 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + + + diff --git a/firmware/svd/STM32L0x3.svd b/firmware/svd/STM32L0x3.svd new file mode 100644 index 0000000..f128279 --- /dev/null +++ b/firmware/svd/STM32L0x3.svd @@ -0,0 +1,22518 @@ + + + STM32L0x3 + 1.3 + STM32L0x3 + + + CM0+ + r0p0 + little + false + false + 3 + false + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + AES + Advanced encryption standard hardware + accelerator + AES + 0x40026000 + + 0x0 + 0x400 + registers + + + AES_RNG_LPUART1 + AES global interrupt RNG global interrupt and + LPUART1 global interrupt through + 29 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAOUTEN + Enable DMA management of data output + phase + 12 + 1 + + + DMAINEN + Enable DMA management of data input + phase + 11 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + CCFIE + CCF flag interrupt enable + 9 + 1 + + + ERRC + Error clear + 8 + 1 + + + CCFC + Computation Complete Flag + Clear + 7 + 1 + + + CHMOD + AES chaining mode + 5 + 2 + + + MODE + AES operating mode + 3 + 2 + + + DATATYPE + Data type selection (for data in and + data out to/from the cryptographic + block) + 1 + 2 + + + EN + AES enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + WRERR + Write error flag + 2 + 1 + + + RDERR + Read error flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + DINR + DINR + data input register + 0x8 + 0x20 + read-write + 0x00000000 + + + AES_DINR + Data Input Register. + 0 + 32 + + + + + DOUTR + DOUTR + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + AES_DOUTR + Data output register + 0 + 32 + + + + + KEYR0 + KEYR0 + key register 0 + 0x10 + 0x20 + read-write + 0x00000000 + + + AES_KEYR0 + Data Output Register (LSB key + [31:0]) + 0 + 32 + + + + + KEYR1 + KEYR1 + key register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + AES_KEYR1 + AES key register (key + [63:32]) + 0 + 32 + + + + + KEYR2 + KEYR2 + key register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + AES_KEYR2 + AES key register (key + [95:64]) + 0 + 32 + + + + + KEYR3 + KEYR3 + key register 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + AES_KEYR3 + AES key register (MSB key + [127:96]) + 0 + 32 + + + + + IVR0 + IVR0 + initialization vector register + 0 + 0x20 + 0x20 + read-write + 0x00000000 + + + AES_IVR0 + initialization vector register (LSB IVR + [31:0]) + 0 + 32 + + + + + IVR1 + IVR1 + initialization vector register + 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + AES_IVR1 + Initialization Vector Register (IVR + [63:32]) + 0 + 32 + + + + + IVR2 + IVR2 + initialization vector register + 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + AES_IVR2 + Initialization Vector Register (IVR + [95:64]) + 0 + 32 + + + + + IVR3 + IVR3 + initialization vector register + 3 + 0x2C + 0x20 + read-write + 0x00000000 + + + AES_IVR3 + Initialization Vector Register (MSB IVR + [127:96]) + 0 + 32 + + + + + + + DAC + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable + 13 + 1 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + + BOFF1 + DAC channel1 output buffer + disable + 1 + 1 + + + EN1 + DAC channel1 enable + 0 + 1 + + + + + SWTRIGR + SWTRIGR + software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + + + DHR12R1 + DHR12R1 + channel1 12-bit right-aligned data holding + register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L1 + DHR12L1 + channel1 12-bit left-aligned data holding + register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R1 + DHR8R1 + channel1 8-bit right-aligned data holding + register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR1 + DAC channel1 DMA underrun + flag + 13 + 1 + + + + + DHR12R2 + DHR12R2 + channel2 12-bit right-aligned data holding + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L2 + DHR12L2 + channel2 12-bit left-aligned data holding + register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R2 + DHR8R2 + channel2 8-bit right-aligned data holding + register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + + + DHR12LD + DHR12LD + Dual DAC 12-bit left-aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 20 + 12 + + + + + DHR8RD + DHR8RD + Dual DAC 8-bit right-aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + + + DOR2 + DOR2 + channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + + + DMA1 + Direct memory access controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 9 + + + DMA1_Channel2_3 + DMA1 Channel2 and 3 interrupts + 10 + + + DMA1_Channel4_7 + DMA1 Channel4 to 7 interrupts + 11 + + + + ISR + ISR + interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF7 + Channel x transfer error flag (x = 1 + ..7) + 27 + 1 + + + HTIF7 + Channel x half transfer flag (x = 1 + ..7) + 26 + 1 + + + TCIF7 + Channel x transfer complete flag (x = 1 + ..7) + 25 + 1 + + + GIF7 + Channel x global interrupt flag (x = 1 + ..7) + 24 + 1 + + + TEIF6 + Channel x transfer error flag (x = 1 + ..7) + 23 + 1 + + + HTIF6 + Channel x half transfer flag (x = 1 + ..7) + 22 + 1 + + + TCIF6 + Channel x transfer complete flag (x = 1 + ..7) + 21 + 1 + + + GIF6 + Channel x global interrupt flag (x = 1 + ..7) + 20 + 1 + + + TEIF5 + Channel x transfer error flag (x = 1 + ..7) + 19 + 1 + + + HTIF5 + Channel x half transfer flag (x = 1 + ..7) + 18 + 1 + + + TCIF5 + Channel x transfer complete flag (x = 1 + ..7) + 17 + 1 + + + GIF5 + Channel x global interrupt flag (x = 1 + ..7) + 16 + 1 + + + TEIF4 + Channel x transfer error flag (x = 1 + ..7) + 15 + 1 + + + HTIF4 + Channel x half transfer flag (x = 1 + ..7) + 14 + 1 + + + TCIF4 + Channel x transfer complete flag (x = 1 + ..7) + 13 + 1 + + + GIF4 + Channel x global interrupt flag (x = 1 + ..7) + 12 + 1 + + + TEIF3 + Channel x transfer error flag (x = 1 + ..7) + 11 + 1 + + + HTIF3 + Channel x half transfer flag (x = 1 + ..7) + 10 + 1 + + + TCIF3 + Channel x transfer complete flag (x = 1 + ..7) + 9 + 1 + + + GIF3 + Channel x global interrupt flag (x = 1 + ..7) + 8 + 1 + + + TEIF2 + Channel x transfer error flag (x = 1 + ..7) + 7 + 1 + + + HTIF2 + Channel x half transfer flag (x = 1 + ..7) + 6 + 1 + + + TCIF2 + Channel x transfer complete flag (x = 1 + ..7) + 5 + 1 + + + GIF2 + Channel x global interrupt flag (x = 1 + ..7) + 4 + 1 + + + TEIF1 + Channel x transfer error flag (x = 1 + ..7) + 3 + 1 + + + HTIF1 + Channel x half transfer flag (x = 1 + ..7) + 2 + 1 + + + TCIF1 + Channel x transfer complete flag (x = 1 + ..7) + 1 + 1 + + + GIF1 + Channel x global interrupt flag (x = 1 + ..7) + 0 + 1 + + + + + IFCR + IFCR + interrupt flag clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + CTEIF7 + Channel x transfer error clear (x = 1 + ..7) + 27 + 1 + + + CHTIF7 + Channel x half transfer clear (x = 1 + ..7) + 26 + 1 + + + CTCIF7 + Channel x transfer complete clear (x = 1 + ..7) + 25 + 1 + + + CGIF7 + Channel x global interrupt clear (x = 1 + ..7) + 24 + 1 + + + CTEIF6 + Channel x transfer error clear (x = 1 + ..7) + 23 + 1 + + + CHTIF6 + Channel x half transfer clear (x = 1 + ..7) + 22 + 1 + + + CTCIF6 + Channel x transfer complete clear (x = 1 + ..7) + 21 + 1 + + + CGIF6 + Channel x global interrupt clear (x = 1 + ..7) + 20 + 1 + + + CTEIF5 + Channel x transfer error clear (x = 1 + ..7) + 19 + 1 + + + CHTIF5 + Channel x half transfer clear (x = 1 + ..7) + 18 + 1 + + + CTCIF5 + Channel x transfer complete clear (x = 1 + ..7) + 17 + 1 + + + CGIF5 + Channel x global interrupt clear (x = 1 + ..7) + 16 + 1 + + + CTEIF4 + Channel x transfer error clear (x = 1 + ..7) + 15 + 1 + + + CHTIF4 + Channel x half transfer clear (x = 1 + ..7) + 14 + 1 + + + CTCIF4 + Channel x transfer complete clear (x = 1 + ..7) + 13 + 1 + + + CGIF4 + Channel x global interrupt clear (x = 1 + ..7) + 12 + 1 + + + CTEIF3 + Channel x transfer error clear (x = 1 + ..7) + 11 + 1 + + + CHTIF3 + Channel x half transfer clear (x = 1 + ..7) + 10 + 1 + + + CTCIF3 + Channel x transfer complete clear (x = 1 + ..7) + 9 + 1 + + + CGIF3 + Channel x global interrupt clear (x = 1 + ..7) + 8 + 1 + + + CTEIF2 + Channel x transfer error clear (x = 1 + ..7) + 7 + 1 + + + CHTIF2 + Channel x half transfer clear (x = 1 + ..7) + 6 + 1 + + + CTCIF2 + Channel x transfer complete clear (x = 1 + ..7) + 5 + 1 + + + CGIF2 + Channel x global interrupt clear (x = 1 + ..7) + 4 + 1 + + + CTEIF1 + Channel x transfer error clear (x = 1 + ..7) + 3 + 1 + + + CHTIF1 + Channel x half transfer clear (x = 1 + ..7) + 2 + 1 + + + CTCIF1 + Channel x transfer complete clear (x = 1 + ..7) + 1 + 1 + + + CGIF1 + Channel x global interrupt clear (x = 1 + ..7) + 0 + 1 + + + + + CCR1 + CCR1 + channel x configuration + register + 0x8 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR1 + CNDTR1 + channel x number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + channel x peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + channel x memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + channel x configuration + register + 0x1C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR2 + CNDTR2 + channel x number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + channel x peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + channel x memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + channel x configuration + register + 0x30 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR3 + CNDTR3 + channel x number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + channel x peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + channel x memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR4 + CCR4 + channel x configuration + register + 0x44 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR4 + CNDTR4 + channel x number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR4 + CPAR4 + channel x peripheral address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR4 + CMAR4 + channel x memory address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR5 + CCR5 + channel x configuration + register + 0x58 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR5 + CNDTR5 + channel x number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR5 + CPAR5 + channel x peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR5 + CMAR5 + channel x memory address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR6 + CCR6 + channel x configuration + register + 0x6C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR6 + CNDTR6 + channel x number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR6 + CPAR6 + channel x peripheral address + register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR6 + CMAR6 + channel x memory address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR7 + CCR7 + channel x configuration + register + 0x80 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR7 + CNDTR7 + channel x number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR7 + CPAR7 + channel x peripheral address + register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR7 + CMAR7 + channel x memory address + register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CSELR + CSELR + channel selection register + 0xA8 + 0x20 + read-write + 0x00000000 + + + C7S + DMA channel 7 selection + 24 + 4 + + + C6S + DMA channel 6 selection + 20 + 4 + + + C5S + DMA channel 5 selection + 16 + 4 + + + C4S + DMA channel 4 selection + 12 + 4 + + + C3S + DMA channel 3 selection + 8 + 4 + + + C2S + DMA channel 2 selection + 4 + 4 + + + C1S + DMA channel 1 selection + 0 + 4 + + + + + + + CRC + Cyclic redundancy check calculation + unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits + 0 + 32 + + + + + IDR + IDR + Independent data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + General-purpose 8-bit data register + bits + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + 0x00000000 + + + REV_OUT + Reverse output data + 7 + 1 + read-write + + + REV_IN + Reverse input data + 5 + 2 + read-write + + + POLYSIZE + Polynomial size + 3 + 2 + read-write + + + RESET + RESET bit + 0 + 1 + write-only + + + + + INIT + INIT + Initial CRC value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC + value + 0 + 32 + + + + + POL + POL + polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + Polynomialcoefficients + Programmable polynomial + 0 + 32 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x50000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xEBFFFCFF + + + MODE0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + MODE1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODE2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODE3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODE4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODE5 + Port x configuration bits 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output data bit (y = + 0..15) + 12 + 1 + + + OD11 + Port output data bit (y = + 0..15) + 11 + 1 + + + OD10 + Port output data bit (y = + 0..15) + 10 + 1 + + + OD9 + Port output data bit (y = + 0..15) + 9 + 1 + + + OD8 + Port output data bit (y = + 0..15) + 8 + 1 + + + OD7 + Port output data bit (y = + 0..15) + 7 + 1 + + + OD6 + Port output data bit (y = + 0..15) + 6 + 1 + + + OD5 + Port output data bit (y = + 0..15) + 5 + 1 + + + OD4 + Port output data bit (y = + 0..15) + 4 + 1 + + + OD3 + Port output data bit (y = + 0..15) + 3 + 1 + + + OD2 + Port output data bit (y = + 0..15) + 2 + 1 + + + OD1 + Port output data bit (y = + 0..15) + 1 + 1 + + + OD0 + Port output data bit (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x reset bit y (y = + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL7 + Alternate function selection for port x + pin y (y = 0..7) + 28 + 4 + + + AFSEL6 + Alternate function selection for port x + pin y (y = 0..7) + 24 + 4 + + + AFSEL5 + Alternate function selection for port x + pin y (y = 0..7) + 20 + 4 + + + AFSEL4 + Alternate function selection for port x + pin y (y = 0..7) + 16 + 4 + + + AFSEL3 + Alternate function selection for port x + pin y (y = 0..7) + 12 + 4 + + + AFSEL2 + Alternate function selection for port x + pin y (y = 0..7) + 8 + 4 + + + AFSEL1 + Alternate function selection for port x + pin y (y = 0..7) + 4 + 4 + + + AFSEL0 + Alternate function selection for port x + pin y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + Alternate function selection for port x + pin y (y = 8..15) + 28 + 4 + + + AFSEL14 + Alternate function selection for port x + pin y (y = 8..15) + 24 + 4 + + + AFSEL13 + Alternate function selection for port x + pin y (y = 8..15) + 20 + 4 + + + AFSEL12 + Alternate function selection for port x + pin y (y = 8..15) + 16 + 4 + + + AFSEL11 + Alternate function selection for port x + pin y (y = 8..15) + 12 + 4 + + + AFSEL10 + Alternate function selection for port x + pin y (y = 8..15) + 8 + 4 + + + AFSEL9 + Alternate function selection for port x + pin y (y = 8..15) + 4 + 4 + + + AFSEL8 + Alternate function selection for port x + pin y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x Reset bit y (y= 0 .. + 15) + 15 + 1 + + + BR14 + Port x Reset bit y (y= 0 .. + 15) + 14 + 1 + + + BR13 + Port x Reset bit y (y= 0 .. + 15) + 13 + 1 + + + BR12 + Port x Reset bit y (y= 0 .. + 15) + 12 + 1 + + + BR11 + Port x Reset bit y (y= 0 .. + 15) + 11 + 1 + + + BR10 + Port x Reset bit y (y= 0 .. + 15) + 10 + 1 + + + BR9 + Port x Reset bit y (y= 0 .. + 15) + 9 + 1 + + + BR8 + Port x Reset bit y (y= 0 .. + 15) + 8 + 1 + + + BR7 + Port x Reset bit y (y= 0 .. + 15) + 7 + 1 + + + BR6 + Port x Reset bit y (y= 0 .. + 15) + 6 + 1 + + + BR5 + Port x Reset bit y (y= 0 .. + 15) + 5 + 1 + + + BR4 + Port x Reset bit y (y= 0 .. + 15) + 4 + 1 + + + BR3 + Port x Reset bit y (y= 0 .. + 15) + 3 + 1 + + + BR2 + Port x Reset bit y (y= 0 .. + 15) + 2 + 1 + + + BR1 + Port x Reset bit y (y= 0 .. + 15) + 1 + 1 + + + BR0 + Port x Reset bit y (y= 0 .. + 15) + 0 + 1 + + + + + + + GPIOC + 0x50000800 + + + GPIOD + 0x50000C00 + + + GPIOH + 0x50001C00 + + + GPIOE + 0x50001000 + + + LPTIM + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + LPTIM1 + LPTIMER1 interrupt through + EXTI29 + 13 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt + Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value. + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value. + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value. + 0 + 16 + + + + + + + RNG + Random number generator + RNG + 0x40025000 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator + enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt + status + 6 + 1 + read-write + + + CEIS + Clock error interrupt + status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC global interrupt + 2 + + + + TR + TR + RTC time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + RTC date register + 0x4 + 0x20 + read-write + 0x00000000 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + CR + CR + RTC control register + 0x8 + 0x20 + 0x00000000 + + + COE + Calibration output enable + 23 + 1 + read-write + + + OSEL + Output selection + 21 + 2 + read-write + + + POL + Output polarity + 20 + 1 + read-write + + + COSEL + Calibration output + selection + 19 + 1 + read-write + + + BKP + Backup + 18 + 1 + read-write + + + SUB1H + Subtract 1 hour (winter time + change) + 17 + 1 + write-only + + + ADD1H + Add 1 hour (summer time + change) + 16 + 1 + write-only + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + read-write + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + read-write + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + TSE + timestamp enable + 11 + 1 + read-write + + + WUTE + Wakeup timer enable + 10 + 1 + read-write + + + ALRBE + Alarm B enable + 9 + 1 + read-write + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + FMT + Hour format + 6 + 1 + read-write + + + BYPSHAD + Bypass the shadow + registers + 5 + 1 + read-write + + + REFCKON + RTC_REFIN reference clock detection + enable (50 or 60 Hz) + 4 + 1 + read-write + + + TSEDGE + Time-stamp event active + edge + 3 + 1 + read-write + + + WUCKSEL + Wakeup clock selection + 0 + 3 + read-write + + + + + ISR + ISR + RTC initialization and status + register + 0xC + 0x20 + 0x00000000 + + + TAMP2F + RTC_TAMP2 detection flag + 14 + 1 + read-write + + + TAMP1F + RTC_TAMP1 detection flag + 13 + 1 + read-write + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + + + ALRBF + Alarm B flag + 9 + 1 + read-write + + + ALRAF + Alarm A flag + 8 + 1 + read-write + + + INIT + Initialization mode + 7 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + RSF + Registers synchronization + flag + 5 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + + + PRER + PRER + RTC prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler + factor + 0 + 16 + + + + + WUTR + WUTR + RTC wakeup timer register + 0x14 + 0x20 + read-write + 0x00000000 + + + WUT + Wakeup auto-reload value + bits + 0 + 16 + + + + + ALRMAR + ALRMAR + RTC alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format. + 28 + 2 + + + DU + Date units or day in BCD + format. + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format. + 20 + 2 + + + HU + Hour units in BCD format. + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format. + 4 + 3 + + + SU + Second units in BCD + format. + 0 + 4 + + + + + ALRMBR + ALRMBR + RTC alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + SSR + SSR + RTC sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + RTC shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + + + TSTR + TSTR + RTC timestamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format. + 20 + 2 + + + HU + Hour units in BCD format. + 16 + 4 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + ST + Second tens in BCD format. + 4 + 3 + + + SU + Second units in BCD + format. + 0 + 4 + + + + + TSDR + TSDR + RTC timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + RTC time-stamp sub second + register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + RTC calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 + ppm + 15 + 1 + + + CALW8 + Use a 8-second calibration cycle + period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle + period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAMPCR + TAMPCR + RTC tamper configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP2MF + Tamper 2 mask flag + 21 + 1 + + + TAMP2NOERASE + Tamper 2 no erase + 20 + 1 + + + TAMP2IE + Tamper 2 interrupt enable + 19 + 1 + + + TAMP1MF + Tamper 1 mask flag + 18 + 1 + + + TAMP1NOERASE + Tamper 1 no erase + 17 + 1 + + + TAMP1IE + Tamper 1 interrupt enable + 16 + 1 + + + TAMPPUDIS + RTC_TAMPx pull-up disable + 15 + 1 + + + TAMPPRCH + RTC_TAMPx precharge + duration + 13 + 2 + + + TAMPFLT + RTC_TAMPx filter count + 11 + 2 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TAMP2_TRG + Active level for RTC_TAMP2 + input + 4 + 1 + + + TAMP2E + RTC_TAMP2 input detection + enable + 3 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for RTC_TAMP1 + input + 1 + 1 + + + TAMP1E + RTC_TAMP1 input detection + enable + 0 + 1 + + + + + ALRMASSR + ALRMASSR + RTC alarm A sub second + register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBSSR + ALRMBSSR + RTC alarm B sub second + register + 0x48 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + OR + OR + option register + 0x4C + 0x20 + read-write + 0x00000000 + + + RTC_OUT_RMP + RTC_ALARM on PC13 output + type + 1 + 1 + + + RTC_ALARM_TYPE + RTC_ALARM on PC13 output + type + 0 + 1 + + + + + BKP0R + BKP0R + RTC backup registers + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + RTC backup registers + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + RTC backup registers + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + RTC backup registers + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + RTC backup registers + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt + enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt + enable + 26 + 1 + + + DEAT4 + Driver Enable assertion + time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion + time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + 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IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear + flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear + flag + 8 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + + + USART2 + 0x40004400 + + + USART4 + 0x40004C00 + + USART4_USART5 + USART4/USART5 global interrupt + 14 + + + USART1 + USART1 global interrupt + 27 + + + + USART5 + 0x40005000 + + USART2 + USART2 global interrupt + 28 + + + + TSC + Touch sensing controller + TSC + 0x40024000 + + 0x0 + 0x400 + registers + + + TSC + Touch sensing interrupt + 8 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CTPH + Charge transfer pulse high + 28 + 4 + + + CTPL + Charge transfer pulse low + 24 + 4 + + + SSD + Spread spectrum deviation + 17 + 7 + + + SSE + Spread spectrum enable + 16 + 1 + + + SSPSC + Spread spectrum prescaler + 15 + 1 + + + PGPSC + pulse generator prescaler + 12 + 3 + + + MCV + Max count value + 5 + 3 + + + IODEF + I/O Default mode + 4 + 1 + + + SYNCPOL + Synchronization pin + polarity + 3 + 1 + + + AM + Acquisition mode + 2 + 1 + + + START + Start a new acquisition + 1 + 1 + + + TSCE + Touch sensing controller + enable + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + MCEIE + Max count error interrupt + enable + 1 + 1 + + + EOAIE + End of acquisition interrupt + enable + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x8 + 0x20 + read-write + 0x00000000 + + + MCEIC + Max count error interrupt + clear + 1 + 1 + + + EOAIC + End of acquisition interrupt + clear + 0 + 1 + + + + + ISR + ISR + interrupt status register + 0xC + 0x20 + read-write + 0x00000000 + + + MCEF + Max count error flag + 1 + 1 + + + EOAF + End of acquisition flag + 0 + 1 + + + + + IOHCR + IOHCR + I/O hysteresis control + register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOASCR + IOASCR + I/O analog switch control + register + 0x18 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOSCR + IOSCR + I/O sampling control register + 0x20 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOCCR + IOCCR + I/O channel control register + 0x28 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOGCSR + IOGCSR + I/O group control status + register + 0x30 + 0x20 + 0x00000000 + + + G8S + Analog I/O group x status + 23 + 1 + read-only + + + G7S + Analog I/O group x status + 22 + 1 + read-only + + + G6S + Analog I/O group x status + 21 + 1 + read-only + + + G5S + Analog I/O group x status + 20 + 1 + read-only + + + G4S + Analog I/O group x status + 19 + 1 + read-only + + + G3S + Analog I/O group x status + 18 + 1 + read-only + + + G2S + Analog I/O group x status + 17 + 1 + read-only + + + G1S + Analog I/O group x status + 16 + 1 + read-only + + + G8E + Analog I/O group x enable + 7 + 1 + read-write + + + G7E + Analog I/O group x enable + 6 + 1 + read-write + + + G6E + Analog I/O group x enable + 5 + 1 + read-write + + + G5E + Analog I/O group x enable + 4 + 1 + read-write + + + G4E + Analog I/O group x enable + 3 + 1 + read-write + + + G3E + Analog I/O group x enable + 2 + 1 + read-write + + + G2E + Analog I/O group x enable + 1 + 1 + read-write + + + G1E + Analog I/O group x enable + 0 + 1 + read-write + + + + + IOG1CR + IOG1CR + I/O group x counter register + 0x34 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG2CR + IOG2CR + I/O group x counter register + 0x38 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG3CR + IOG3CR + I/O group x counter register + 0x3C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG4CR + IOG4CR + I/O group x counter register + 0x40 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG5CR + IOG5CR + I/O group x counter register + 0x44 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG6CR + IOG6CR + I/O group x counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG7CR + IOG7CR + I/O group x counter register + 0x4C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG8CR + IOG8CR + I/O group x counter register + 0x50 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read + 0x0000) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value + update + 2 + 1 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window + value + 0 + 12 + + + + + + + WWDG + System window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early wakeup interrupt + 9 + 1 + + + WDGTB1 + Timer base + 8 + 1 + + + WDGTB0 + WDGTB0 + 7 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + USB_FS + Universal serial bus full-speed device + interface + USB + 0x40005C00 + + 0x0 + 0x400 + registers + + + USB + USB event interrupt through + EXTI18 + 31 + + + + EP0R + EP0R + endpoint register + 0x0 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP1R + EP1R + endpoint register + 0x4 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP2R + EP2R + endpoint register + 0x8 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP3R + EP3R + endpoint register + 0xC + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP4R + EP4R + endpoint register + 0x10 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP5R + EP5R + endpoint register + 0x14 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP6R + EP6R + endpoint register + 0x18 + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + EP7R + EP7R + endpoint register + 0x1C + 0x20 + read-write + 0x0 + + + CTR_RX + CTR_RX + 15 + 1 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + SETUP + SETUP + 11 + 1 + + + EPTYPE + EPTYPE + 9 + 2 + + + EP_KIND + EP_KIND + 8 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + STAT_TX + STAT_TX + 4 + 2 + + + EA + EA + 0 + 4 + + + + + CNTR + CNTR + control register + 0x40 + 0x20 + read-write + 0x0 + + + CTRM + CTRM + 15 + 1 + + + PMAOVRM + PMAOVRM + 14 + 1 + + + ERRM + ERRM + 13 + 1 + + + WKUPM + WKUPM + 12 + 1 + + + SUSPM + SUSPM + 11 + 1 + + + RESETM + RESETM + 10 + 1 + + + SOFM + SOFM + 9 + 1 + + + ESOFM + ESOFM + 8 + 1 + + + L1REQM + L1REQM + 7 + 1 + + + L1RESUME + L1RESUME + 5 + 1 + + + RESUME + RESUME + 4 + 1 + + + FSUSP + FSUSP + 3 + 1 + + + LPMODE + LPMODE + 2 + 1 + + + PDWN + PDWN + 1 + 1 + + + FRES + FRES + 0 + 1 + + + + + ISTR + ISTR + interrupt status register + 0x44 + 0x20 + read-write + 0x0 + + + CTR + CTR + 15 + 1 + + + PMAOVR + PMAOVR + 14 + 1 + + + ERR + ERR + 13 + 1 + + + WKUP + WKUP + 12 + 1 + + + SUSP + SUSP + 11 + 1 + + + RESET + RESET + 10 + 1 + + + SOF + SOF + 9 + 1 + + + ESOF + ESOF + 8 + 1 + + + L1REQ + L1REQ + 7 + 1 + + + DIR + DIR + 4 + 1 + + + EP_ID + EP_ID + 0 + 4 + + + + + FNR + FNR + frame number register + 0x48 + 0x20 + read-only + 0x0 + + + RXDP + RXDP + 15 + 1 + + + RXDM + RXDM + 14 + 1 + + + LCK + LCK + 13 + 1 + + + LSOF + LSOF + 11 + 2 + + + FN + FN + 0 + 11 + + + + + DADDR + DADDR + device address + 0x4C + 0x20 + read-write + 0x0 + + + EF + EF + 7 + 1 + + + ADD + ADD + 0 + 7 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x0 + + + BTABLE + BTABLE + 3 + 13 + + + + + LPMCSR + LPMCSR + LPM control and status + register + 0x54 + 0x20 + 0x0 + + + BESL + BESL + 4 + 4 + read-only + + + REMWAKE + REMWAKE + 3 + 1 + read-only + + + LPMACK + LPMACK + 1 + 1 + read-write + + + LPMEN + LPMEN + 0 + 1 + read-write + + + + + BCDR + BCDR + Battery charging detector + 0x58 + 0x20 + 0x0 + + + DPPU + DPPU + 15 + 1 + read-write + + + PS2DET + PS2DET + 7 + 1 + read-only + + + SDET + SDET + 6 + 1 + read-only + + + PDET + PDET + 5 + 1 + read-only + + + DCDET + DCDET + 4 + 1 + read-only + + + SDEN + SDEN + 3 + 1 + read-write + + + PDEN + PDEN + 2 + 1 + read-write + + + DCDEN + DCDEN + 1 + 1 + read-write + + + BCDEN + BCDEN + 0 + 1 + read-write + + + + + + + CRS + Clock recovery system + CRS + 0x40006C00 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00002000 + + + TRIM + HSI48 oscillator smooth + trimming + 8 + 6 + + + SWSYNC + Generate software SYNC + event + 7 + 1 + + + AUTOTRIMEN + Automatic trimming enable + 6 + 1 + + + CEN + Frequency error counter + enable + 5 + 1 + + + ESYNCIE + Expected SYNC interrupt + enable + 3 + 1 + + + ERRIE + Synchronization or trimming error + interrupt enable + 2 + 1 + + + SYNCWARNIE + SYNC warning interrupt + enable + 1 + 1 + + + SYNCOKIE + SYNC event OK interrupt + enable + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0x4 + 0x20 + read-write + 0x2022BB7F + + + SYNCPOL + SYNC polarity selection + 31 + 1 + + + SYNCSRC + SYNC signal source + selection + 28 + 2 + + + SYNCDIV + SYNC divider + 24 + 3 + + + FELIM + Frequency error limit + 16 + 8 + + + RELOAD + Counter reload value + 0 + 16 + + + + + ISR + ISR + interrupt and status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FECAP + Frequency error capture + 16 + 16 + + + FEDIR + Frequency error direction + 15 + 1 + + + TRIMOVF + Trimming overflow or + underflow + 10 + 1 + + + SYNCMISS + SYNC missed + 9 + 1 + + + SYNCERR + SYNC error + 8 + 1 + + + ESYNCF + Expected SYNC flag + 3 + 1 + + + ERRF + Error flag + 2 + 1 + + + SYNCWARNF + SYNC warning flag + 1 + 1 + + + SYNCOKF + SYNC event OK flag + 0 + 1 + + + + + ICR + ICR + interrupt flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + ESYNCC + Expected SYNC clear flag + 3 + 1 + + + ERRC + Error clear flag + 2 + 1 + + + SYNCWARNC + SYNC warning clear flag + 1 + 1 + + + SYNCOKC + SYNC event OK clear flag + 0 + 1 + + + + + + + Firewall + Firewall + Firewall + 0x40011C00 + + 0x0 + 0x400 + registers + + + + FIREWALL_CSSA + FIREWALL_CSSA + Code segment start address + 0x0 + 0x20 + read-write + 0x00000000 + + + ADD + code segment start address + 8 + 16 + + + + + FIREWALL_CSL + FIREWALL_CSL + Code segment length + 0x4 + 0x20 + read-write + 0x00000000 + + + LENG + code segment length + 8 + 14 + + + + + FIREWALL_NVDSSA + FIREWALL_NVDSSA + Non-volatile data segment start + address + 0x8 + 0x20 + read-write + 0x00000000 + + + ADD + Non-volatile data segment start + address + 8 + 16 + + + + + FIREWALL_NVDSL + FIREWALL_NVDSL + Non-volatile data segment + length + 0xC + 0x20 + read-write + 0x00000000 + + + LENG + Non-volatile data segment + length + 8 + 14 + + + + + FIREWALL_VDSSA + FIREWALL_VDSSA + Volatile data segment start + address + 0x10 + 0x20 + read-write + 0x00000000 + + + ADD + Volatile data segment start + address + 6 + 10 + + + + + FIREWALL_VDSL + FIREWALL_VDSL + Volatile data segment length + 0x14 + 0x20 + read-write + 0x00000000 + + + LENG + Non-volatile data segment + length + 6 + 10 + + + + + FIREWALL_CR + FIREWALL_CR + Configuration register + 0x20 + 0x20 + read-write + 0x00000000 + + + VDE + Volatile data execution + 2 + 1 + + + VDS + Volatile data shared + 1 + 1 + + + FPA + Firewall pre alarm + 0 + 1 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 4 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000300 + + + PLLRDY + PLL clock ready flag + 25 + 1 + read-only + + + PLLON + PLL enable bit + 24 + 1 + read-write + + + RTCPRE + TC/LCD prescaler + 20 + 2 + read-write + + + CSSLSEON + Clock security system on HSE enable + bit + 19 + 1 + read-write + + + HSEBYP + HSE clock bypass bit + 18 + 1 + read-write + + + HSERDY + HSE clock ready flag + 17 + 1 + read-only + + + HSEON + HSE clock enable bit + 16 + 1 + read-write + + + MSIRDY + MSI clock ready flag + 9 + 1 + read-only + + + MSION + MSI clock enable bit + 8 + 1 + read-write + + + HSI16DIVF + HSI16DIVF + 4 + 1 + read-only + + + HSI16DIVEN + HSI16DIVEN + 3 + 1 + read-write + + + HSI16RDYF + Internal high-speed clock ready + flag + 2 + 1 + read-write + + + HSI16KERON + High-speed internal clock enable bit for + some IP kernels + 1 + 1 + read-only + + + HSI16ON + 16 MHz high-speed internal clock + enable + 0 + 1 + read-write + + + HSI16OUTEN + 16 MHz high-speed internal clock output + enable + 5 + 1 + read-write + + + + + ICSCR + ICSCR + Internal clock sources calibration + register + 0x4 + 0x20 + 0x0000B000 + + + MSITRIM + MSI clock trimming + 24 + 8 + read-write + + + MSICAL + MSI clock calibration + 16 + 8 + read-only + + + MSIRANGE + MSI clock ranges + 13 + 3 + read-write + + + HSI16TRIM + High speed internal clock + trimming + 8 + 5 + read-write + + + HSI16CAL + nternal high speed clock + calibration + 0 + 8 + read-only + + + + + CRRCR + CRRCR + Clock recovery RC register + 0x8 + 0x20 + 0x00000000 + + + HSI48CAL + 48 MHz HSI clock + calibration + 8 + 8 + read-only + + + HSI48RDY + 48MHz HSI clock ready flag + 1 + 1 + read-only + + + HSI48ON + 48MHz HSI clock enable bit + 0 + 1 + read-write + + + HSI48DIV6EN + 48 MHz HSI clock divided by 6 output + enable + 2 + 1 + read-write + + + + + CFGR + CFGR + Clock configuration register + 0xC + 0x20 + 0x00000000 + + + MCOPRE + Microcontroller clock output + prescaler + 28 + 3 + read-write + + + MCOSEL + Microcontroller clock output + selection + 24 + 4 + read-write + + + PLLDIV + PLL output division + 22 + 2 + read-write + + + PLLMUL + PLL multiplication factor + 18 + 4 + read-write + + + PLLSRC + PLL entry clock source + 16 + 1 + read-write + + + STOPWUCK + Wake-up from stop clock + selection + 15 + 1 + read-write + + + PPRE2 + APB high-speed prescaler + (APB2) + 11 + 3 + read-write + + + PPRE1 + APB low-speed prescaler + (APB1) + 8 + 3 + read-write + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + SWS + System clock switch status + 2 + 2 + read-only + + + SW + System clock switch + 0 + 2 + read-write + + + + + CIER + CIER + Clock interrupt enable + register + 0x10 + 0x20 + read-only + 0x00000000 + + + CSSLSE + LSE CSS interrupt flag + 7 + 1 + + + HSI48RDYIE + HSI48 ready interrupt flag + 6 + 1 + + + MSIRDYIE + MSI ready interrupt flag + 5 + 1 + + + PLLRDYIE + PLL ready interrupt flag + 4 + 1 + + + HSERDYIE + HSE ready interrupt flag + 3 + 1 + + + HSI16RDYIE + HSI16 ready interrupt flag + 2 + 1 + + + LSERDYIE + LSE ready interrupt flag + 1 + 1 + + + LSIRDYIE + LSI ready interrupt flag + 0 + 1 + + + + + CIFR + CIFR + Clock interrupt flag register + 0x14 + 0x20 + read-only + 0x00000000 + + + CSSHSEF + Clock Security System Interrupt + flag + 8 + 1 + + + CSSLSEF + LSE Clock Security System Interrupt + flag + 7 + 1 + + + HSI48RDYF + HSI48 ready interrupt flag + 6 + 1 + + + MSIRDYF + MSI ready interrupt flag + 5 + 1 + + + PLLRDYF + PLL ready interrupt flag + 4 + 1 + + + HSERDYF + HSE ready interrupt flag + 3 + 1 + + + HSI16RDYF + HSI16 ready interrupt flag + 2 + 1 + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x18 + 0x20 + read-only + 0x00000000 + + + CSSHSEC + Clock Security System Interrupt + clear + 8 + 1 + + + CSSLSEC + LSE Clock Security System Interrupt + clear + 7 + 1 + + + HSI48RDYC + HSI48 ready Interrupt + clear + 6 + 1 + + + MSIRDYC + MSI ready Interrupt clear + 5 + 1 + + + PLLRDYC + PLL ready Interrupt clear + 4 + 1 + + + HSERDYC + HSE ready Interrupt clear + 3 + 1 + + + HSI16RDYC + HSI16 ready Interrupt + clear + 2 + 1 + + + LSERDYC + LSE ready Interrupt clear + 1 + 1 + + + LSIRDYC + LSI ready Interrupt clear + 0 + 1 + + + + + IOPRSTR + IOPRSTR + GPIO reset register + 0x1C + 0x20 + read-write + 0x00000000 + + + IOPHRST + I/O port H reset + 7 + 1 + + + IOPDRST + I/O port D reset + 3 + 1 + + + IOPCRST + I/O port A reset + 2 + 1 + + + IOPBRST + I/O port B reset + 1 + 1 + + + IOPARST + I/O port A reset + 0 + 1 + + + IOPERST + I/O port E reset + 4 + 1 + + + + + AHBRSTR + AHBRSTR + AHB peripheral reset register + 0x20 + 0x20 + read-write + 0x00000000 + + + CRYPRST + Crypto module reset + 24 + 1 + + + RNGRST + Random Number Generator module + reset + 20 + 1 + + + TOUCHRST + Touch Sensing reset + 16 + 1 + + + CRCRST + Test integration module + reset + 12 + 1 + + + MIFRST + Memory interface reset + 8 + 1 + + + DMARST + DMA reset + 0 + 1 + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x24 + 0x20 + read-write + 0x000000000 + + + DBGRST + DBG reset + 22 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + ADCRST + ADC interface reset + 9 + 1 + + + TM12RST + TIM22 timer reset + 5 + 1 + + + TIM21RST + TIM21 timer reset + 2 + 1 + + + SYSCFGRST + System configuration controller + reset + 0 + 1 + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + LPTIM1RST + Low power timer reset + 31 + 1 + + + DACRST + DAC interface reset + 29 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + CRSRST + Clock recovery system + reset + 27 + 1 + + + USBRST + USB reset + 23 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + LPUART1RST + LPUART1 reset + 18 + 1 + + + LPUART12RST + UART2 reset + 17 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + WWDRST + Window watchdog reset + 11 + 1 + + + TIM6RST + Timer 6 reset + 4 + 1 + + + TIM2RST + Timer2 reset + 0 + 1 + + + TIM3RST + Timer3 reset + 1 + 1 + + + TIM7RST + Timer 7 reset + 5 + 1 + + + USART4RST + USART4 reset + 19 + 1 + + + USART5RST + USART5 reset + 20 + 1 + + + I2C3RST + I2C3 reset + 30 + 1 + + + + + IOPENR + IOPENR + GPIO clock enable register + 0x2C + 0x20 + read-write + 0x00000000 + + + IOPHEN + I/O port H clock enable + bit + 7 + 1 + + + IOPDEN + I/O port D clock enable + bit + 3 + 1 + + + IOPCEN + IO port A clock enable bit + 2 + 1 + + + IOPBEN + IO port B clock enable bit + 1 + 1 + + + IOPAEN + IO port A clock enable bit + 0 + 1 + + + IOPEEN + I/O port E clock enable + bit + 4 + 1 + + + + + AHBENR + AHBENR + AHB peripheral clock enable + register + 0x30 + 0x20 + read-write + 0x00000100 + + + CRYPEN + Crypto clock enable bit + 24 + 1 + + + RNGEN + Random Number Generator clock enable + bit + 20 + 1 + + + TOUCHEN + Touch Sensing clock enable + bit + 16 + 1 + + + CRCEN + CRC clock enable bit + 12 + 1 + + + MIFEN + NVM interface clock enable + bit + 8 + 1 + + + DMAEN + DMA clock enable bit + 0 + 1 + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable + register + 0x34 + 0x20 + read-write + 0x00000000 + + + DBGEN + DBG clock enable bit + 22 + 1 + + + USART1EN + USART1 clock enable bit + 14 + 1 + + + SPI1EN + SPI1 clock enable bit + 12 + 1 + + + ADCEN + ADC clock enable bit + 9 + 1 + + + MIFIEN + MiFaRe Firewall clock enable + bit + 7 + 1 + + + TIM22EN + TIM22 timer clock enable + bit + 5 + 1 + + + TIM21EN + TIM21 timer clock enable + bit + 2 + 1 + + + SYSCFGEN + System configuration controller clock + enable bit + 0 + 1 + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + LPTIM1EN + Low power timer clock enable + bit + 31 + 1 + + + DACEN + DAC interface clock enable + bit + 29 + 1 + + + PWREN + Power interface clock enable + bit + 28 + 1 + + + CRSEN + Clock recovery system clock enable + bit + 27 + 1 + + + USBEN + USB clock enable bit + 23 + 1 + + + I2C2EN + I2C2 clock enable bit + 22 + 1 + + + I2C1EN + I2C1 clock enable bit + 21 + 1 + + + LPUART1EN + LPUART1 clock enable bit + 18 + 1 + + + USART2EN + UART2 clock enable bit + 17 + 1 + + + SPI2EN + SPI2 clock enable bit + 14 + 1 + + + WWDGEN + Window watchdog clock enable + bit + 11 + 1 + + + TIM6EN + Timer 6 clock enable bit + 4 + 1 + + + TIM2EN + Timer2 clock enable bit + 0 + 1 + + + TIM3EN + Timer3 clock enable bit + 1 + 1 + + + TIM7EN + Timer 7 clock enable bit + 5 + 1 + + + USART4EN + USART4 clock enable bit + 19 + 1 + + + USART5EN + USART5 clock enable bit + 20 + 1 + + + I2C3EN + I2C3 clock enable bit + 30 + 1 + + + + + IOPSMEN + IOPSMEN + GPIO clock enable in sleep mode + register + 0x3C + 0x20 + read-write + 0x0000008F + + + IOPHSMEN + IOPHSMEN + 7 + 1 + + + IOPDSMEN + IOPDSMEN + 3 + 1 + + + IOPCSMEN + IOPCSMEN + 2 + 1 + + + IOPBSMEN + IOPBSMEN + 1 + 1 + + + IOPASMEN + IOPASMEN + 0 + 1 + + + IOPESMEN + Port E clock enable during Sleep mode + bit + 4 + 1 + + + + + AHBSMENR + AHBSMENR + AHB peripheral clock enable in sleep mode + register + 0x40 + 0x20 + read-write + 0x01111301 + + + CRYPSMEN + Crypto clock enable during sleep mode + bit + 24 + 1 + + + RNGSMEN + Random Number Generator clock enable + during sleep mode bit + 20 + 1 + + + TOUCHSMEN + Touch Sensing clock enable during sleep + mode bit + 16 + 1 + + + CRCSMEN + CRC clock enable during sleep mode + bit + 12 + 1 + + + SRAMSMEN + SRAM interface clock enable during sleep + mode bit + 9 + 1 + + + MIFSMEN + NVM interface clock enable during sleep + mode bit + 8 + 1 + + + DMASMEN + DMA clock enable during sleep mode + bit + 0 + 1 + + + + + APB2SMENR + APB2SMENR + APB2 peripheral clock enable in sleep mode + register + 0x44 + 0x20 + read-write + 0x00405225 + + + DBGSMEN + DBG clock enable during sleep mode + bit + 22 + 1 + + + USART1SMEN + USART1 clock enable during sleep mode + bit + 14 + 1 + + + SPI1SMEN + SPI1 clock enable during sleep mode + bit + 12 + 1 + + + ADCSMEN + ADC clock enable during sleep mode + bit + 9 + 1 + + + TIM22SMEN + TIM22 timer clock enable during sleep + mode bit + 5 + 1 + + + TIM21SMEN + TIM21 timer clock enable during sleep + mode bit + 2 + 1 + + + SYSCFGSMEN + System configuration controller clock + enable during sleep mode bit + 0 + 1 + + + + + APB1SMENR + APB1SMENR + APB1 peripheral clock enable in sleep mode + register + 0x48 + 0x20 + read-write + 0xB8E64A11 + + + LPTIM1SMEN + Low power timer clock enable during + sleep mode bit + 31 + 1 + + + DACSMEN + DAC interface clock enable during sleep + mode bit + 29 + 1 + + + PWRSMEN + Power interface clock enable during + sleep mode bit + 28 + 1 + + + CRSSMEN + Clock recovery system clock enable + during sleep mode bit + 27 + 1 + + + USBSMEN + USB clock enable during sleep mode + bit + 23 + 1 + + + I2C2SMEN + I2C2 clock enable during sleep mode + bit + 22 + 1 + + + I2C1SMEN + I2C1 clock enable during sleep mode + bit + 21 + 1 + + + LPUART1SMEN + LPUART1 clock enable during sleep mode + bit + 18 + 1 + + + USART2SMEN + UART2 clock enable during sleep mode + bit + 17 + 1 + + + SPI2SMEN + SPI2 clock enable during sleep mode + bit + 14 + 1 + + + WWDGSMEN + Window watchdog clock enable during + sleep mode bit + 11 + 1 + + + TIM6SMEN + Timer 6 clock enable during sleep mode + bit + 4 + 1 + + + TIM2SMEN + Timer2 clock enable during sleep mode + bit + 0 + 1 + + + TIM3SMEN + Timer3 clock enable during Sleep mode + bit + 1 + 1 + + + TIM7SMEN + Timer 7 clock enable during Sleep mode + bit + 5 + 1 + + + USART4SMEN + USART4 clock enable during Sleep mode + bit + 19 + 1 + + + USART5SMEN + USART5 clock enable during Sleep mode + bit + 20 + 1 + + + I2C3SMEN + 2C3 clock enable during Sleep mode + bit + 30 + 1 + + + + + CCIPR + CCIPR + Clock configuration register + 0x4C + 0x20 + read-write + 0x00000000 + + + HSI48MSEL + 48 MHz HSI48 clock source selection + bit + 26 + 1 + + + LPTIM1SEL1 + Low Power Timer clock source selection + bits + 19 + 1 + + + LPTIM1SEL0 + LPTIM1SEL0 + 18 + 1 + + + I2C1SEL1 + I2C1 clock source selection + bits + 13 + 1 + + + I2C1SEL0 + I2C1SEL0 + 12 + 1 + + + LPUART1SEL1 + LPUART1 clock source selection + bits + 11 + 1 + + + LPUART1SEL0 + LPUART1SEL0 + 10 + 1 + + + USART2SEL1 + USART2 clock source selection + bits + 3 + 1 + + + USART2SEL0 + USART2SEL0 + 2 + 1 + + + USART1SEL1 + USART1 clock source selection + bits + 1 + 1 + + + USART1SEL0 + USART1SEL0 + 0 + 1 + + + I2C3SEL + I2C3 clock source selection + bits + 16 + 2 + + + + + CSR + CSR + Control and status register + 0x50 + 0x20 + 0x0C000000 + + + LPWRSTF + Low-power reset flag + 31 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + IWDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + PINRSTF + PIN reset flag + 26 + 1 + read-write + + + OBLRSTF + OBLRSTF + 25 + 1 + read-write + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + RTCRST + RTC software reset bit + 19 + 1 + read-write + + + RTCEN + RTC clock enable bit + 18 + 1 + read-write + + + RTCSEL + RTC and LCD clock source selection + bits + 16 + 2 + read-write + + + CSSLSED + CSS on LSE failure detection + flag + 14 + 1 + read-write + + + CSSLSEON + CSSLSEON + 13 + 1 + read-write + + + LSEDRV + LSEDRV + 11 + 2 + read-write + + + LSEBYP + External low-speed oscillator bypass + bit + 10 + 1 + read-write + + + LSERDY + External low-speed oscillator ready + bit + 9 + 1 + read-only + + + LSEON + External low-speed oscillator enable + bit + 8 + 1 + read-write + + + LSIRDY + Internal low-speed oscillator ready + bit + 1 + 1 + read-write + + + LSION + Internal low-speed oscillator + enable + 0 + 1 + read-write + + + + + + + SYSCFG_COMP + System configuration controller and + Comparator + SYSCFG + 0x40010000 + + 0x0 + 0x400 + registers + + + + CFGR1 + CFGR1 + SYSCFG configuration register + 1 + 0x0 + 0x20 + 0x00000000 + + + BOOT_MODE + Boot mode selected by the boot pins + status bits + 8 + 2 + read-only + + + MEM_MODE + Memory mapping selection + bits + 0 + 2 + read-write + + + + + CFGR2 + CFGR2 + SYSCFG configuration register + 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + I2C2_FMP + I2C2 Fm+ drive capability enable + bit + 13 + 1 + + + I2C1_FMP + I2C1 Fm+ drive capability enable + bit + 12 + 1 + + + I2C_PB9_FMP + Fm+ drive capability on PB9 enable + bit + 11 + 1 + + + I2C_PB8_FMP + Fm+ drive capability on PB8 enable + bit + 10 + 1 + + + I2C_PB7_FMP + Fm+ drive capability on PB7 enable + bit + 9 + 1 + + + I2C_PB6_FMP + Fm+ drive capability on PB6 enable + bit + 8 + 1 + + + FWDISEN + Firewall disable bit + 0 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to + 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to + 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to + 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to + 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to + 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to + 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to + 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to + 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to + 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to + 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to + 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to + 15) + 12 + 4 + + + EXTI14 + EXTI14 + 8 + 4 + + + EXTI13 + EXTI13 + 4 + 4 + + + EXTI12 + EXTI12 + 0 + 4 + + + + + CFGR3 + CFGR3 + SYSCFG configuration register + 3 + 0x20 + 0x20 + 0x00000000 + + + REF_LOCK + REF_CTRL lock bit + 31 + 1 + write-only + + + VREFINT_RDYF + VREFINT ready flag + 30 + 1 + read-only + + + VREFINT_COMP_RDYF + VREFINT for comparator ready + flag + 29 + 1 + read-only + + + VREFINT_ADC_RDYF + VREFINT for ADC ready flag + 28 + 1 + read-only + + + SENSOR_ADC_RDYF + Sensor for ADC ready flag + 27 + 1 + read-only + + + REF_RC48MHz_RDYF + VREFINT for 48 MHz RC oscillator ready + flag + 26 + 1 + read-only + + + ENREF_RC48MHz + VREFINT reference for 48 MHz RC + oscillator enable bit + 13 + 1 + read-write + + + ENBUF_VREFINT_COMP + VREFINT reference for comparator 2 + enable bit + 12 + 1 + read-write + + + ENBUF_SENSOR_ADC + Sensor reference for ADC enable + bit + 9 + 1 + read-write + + + ENBUF_BGAP_ADC + VREFINT reference for ADC enable + bit + 8 + 1 + read-write + + + SEL_VREF_OUT + BGAP_ADC connection bit + 4 + 2 + read-write + + + EN_BGAP + Vref Enable bit + 0 + 1 + read-write + + + + + COMP1_CSR + COMP1_CSR + Comparator 1 control and status + register + 0x18 + 0x20 + 0x00000000 + + + COMP1LOCK + COMP1_CSR register lock + bit + 31 + 1 + read-only + + + COMP1VALUE + Comparator 1 output status + bit + 30 + 1 + read-only + + + COMP1POLARITY + Comparator 1 polarity selection + bit + 15 + 1 + read-write + + + COMP1LPTIMIN1 + Comparator 1 LPTIM input propagation + bit + 12 + 1 + read-write + + + COMP1WM + Comparator 1 window mode selection + bit + 8 + 1 + read-write + + + COMP1INNSEL + Comparator 1 Input Minus connection + configuration bit + 4 + 2 + read-write + + + COMP1EN + Comparator 1 enable bit + 0 + 1 + read-write + + + + + COMP2_CSR + COMP2_CSR + Comparator 2 control and status + register + 0x1C + 0x20 + 0x00000000 + + + COMP2LOCK + COMP2_CSR register lock + bit + 31 + 1 + read-only + + + COMP2VALUE + Comparator 2 output status + bit + 20 + 1 + read-only + + + COMP2POLARITY + Comparator 2 polarity selection + bit + 15 + 1 + read-write + + + COMP2LPTIMIN1 + Comparator 2 LPTIM input 1 propagation + bit + 13 + 1 + read-write + + + COMP2LPTIMIN2 + Comparator 2 LPTIM input 2 propagation + bit + 12 + 1 + read-write + + + COMP2INPSEL + Comparator 2 Input Plus connection + configuration bit + 8 + 3 + read-write + + + COMP2INNSEL + Comparator 2 Input Minus connection + configuration bit + 4 + 3 + read-write + + + COMP2SPEED + Comparator 2 power mode selection + bit + 3 + 1 + read-write + + + COMP2EN + Comparator 2 enable bit + 0 + 1 + read-write + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + SSOE + SS output enable + 2 + 1 + + + FRF + Frame format + 4 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + CHSIDE + Channel side + 2 + 1 + read-only + + + UDR + Underrun flag + 3 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + MODF + Mode fault + 5 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMOD + I2S mode selection + 11 + 1 + + + I2SE + I2S Enable + 10 + 1 + + + I2SCFG + I2S configuration mode + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPOL + Steady state clock + polarity + 3 + 1 + + + DATLEN + Data length to be + transferred + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 0x00000010 + + + MCKOE + Master clock output enable + 9 + 1 + + + ODD + Odd factor for the + prescaler + 8 + 1 + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI1 + SPI1_global_interrupt + 25 + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + SPI2 + SPI2 global interrupt + 26 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match interrupt enable (slave + only) + 3 + 1 + + + NACKIE + Not acknowledge received interrupt + enable + 4 + 1 + + + STOPIE + STOP detection Interrupt + enable + 5 + 1 + + + TCIE + Transfer Complete interrupt + enable + 6 + 1 + + + ERRIE + Error interrupts enable + 7 + 1 + + + DNF + Digital noise filter + 8 + 4 + + + ANFOFF + Analog noise filter OFF + 12 + 1 + + + TXDMAEN + DMA transmission requests + enable + 14 + 1 + + + RXDMAEN + DMA reception requests + enable + 15 + 1 + + + SBC + Slave byte control + 16 + 1 + + + NOSTRETCH + Clock stretching disable + 17 + 1 + + + WUPEN + Wakeup from STOP enable + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable + 20 + 1 + + + SMBDEN + SMBus Device Default address + enable + 21 + 1 + + + ALERTEN + SMBUS alert enable + 22 + 1 + + + PECEN + PEC enable + 23 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master + mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave + mode) + 15 + 1 + + + STOP + Stop generation (master + mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read + direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master + mode) + 11 + 1 + + + RD_WRN + Transfer direction (master + mode) + 10 + 1 + + + SADD + Slave address bit (master + mode) + 0 + 10 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master + mode) + 0 + 8 + + + SCLH + SCL high period (master + mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout + detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout + enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave + mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave + mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection + flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave + mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master + mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received + flag + 4 + 1 + read-only + + + ADDR + Address matched (slave + mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty + (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status + (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty + (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag + clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag + clear + 10 + 1 + + + ARLOCF + Arbitration lost flag + clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking + register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C1 + I2C1 global interrupt + 23 + + + I2C2 + I2C2 global interrupt + 24 + + + + I2C3 + 0x40007800 + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + I2C3 + I2C3 global interrupt + 21 + + + + CR + CR + power control register + 0x0 + 0x20 + read-write + 0x00001000 + + + LPDS + Low-power deep sleep + 0 + 1 + + + PDDS + Power down deepsleep + 1 + 1 + + + CWUF + Clear wakeup flag + 2 + 1 + + + CSBF + Clear standby flag + 3 + 1 + + + PVDE + Power voltage detector + enable + 4 + 1 + + + PLS + PVD level selection + 5 + 3 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + ULP + Ultra-low-power mode + 9 + 1 + + + FWU + Fast wakeup + 10 + 1 + + + VOS + Voltage scaling range + selection + 11 + 2 + + + DS_EE_KOFF + Deep sleep mode with Flash memory kept + off + 13 + 1 + + + LPRUN + Low power run mode + 14 + 1 + + + + + CSR + CSR + power control/status register + 0x4 + 0x20 + 0x00000000 + + + BRE + Backup regulator enable + 9 + 1 + read-write + + + EWUP + Enable WKUP pin + 8 + 1 + read-write + + + BRR + Backup regulator ready + 3 + 1 + read-only + + + PVDO + PVD output + 2 + 1 + read-only + + + SBF + Standby flag + 1 + 1 + read-only + + + WUF + Wakeup flag + 0 + 1 + read-only + + + VOSF + Voltage Scaling select + flag + 4 + 1 + read-only + + + REGLPF + Regulator LP flag + 5 + 1 + read-only + + + + + + + Flash + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LATENCY + Latency + 0 + 1 + + + PRFTEN + Prefetch enable + 1 + 1 + + + SLEEP_PD + Flash mode during Sleep + 3 + 1 + + + RUN_PD + Flash mode during Run + 4 + 1 + + + DESAB_BUF + Disable Buffer + 5 + 1 + + + PRE_READ + Pre-read data address + 6 + 1 + + + + + PECR + PECR + Program/erase control register + 0x4 + 0x20 + read-write + 0x00000007 + + + PELOCK + FLASH_PECR and data EEPROM + lock + 0 + 1 + + + PRGLOCK + Program memory lock + 1 + 1 + + + OPTLOCK + Option bytes block lock + 2 + 1 + + + PROG + Program memory selection + 3 + 1 + + + DATA + Data EEPROM selection + 4 + 1 + + + FTDW + Fixed time data write for Byte, Half + Word and Word programming + 8 + 1 + + + ERASE + Page or Double Word erase + mode + 9 + 1 + + + FPRG + Half Page/Double Word programming + mode + 10 + 1 + + + PARALLELBANK + Parallel bank mode + 15 + 1 + + + EOPIE + End of programming interrupt + enable + 16 + 1 + + + ERRIE + Error interrupt enable + 17 + 1 + + + OBL_LAUNCH + Launch the option byte + loading + 18 + 1 + + + + + PDKEYR + PDKEYR + Power down key register + 0x8 + 0x20 + write-only + 0x00000000 + + + PDKEYR + RUN_PD in FLASH_ACR key + 0 + 32 + + + + + PEKEYR + PEKEYR + Program/erase key register + 0xC + 0x20 + write-only + 0x00000000 + + + PEKEYR + FLASH_PEC and data EEPROM + key + 0 + 32 + + + + + PRGKEYR + PRGKEYR + Program memory key register + 0x10 + 0x20 + write-only + 0x00000000 + + + PRGKEYR + Program memory key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0x14 + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x18 + 0x20 + 0x00000004 + + + BSY + Write/erase operations in + progress + 0 + 1 + read-only + + + EOP + End of operation + 1 + 1 + read-only + + + ENDHV + End of high voltage + 2 + 1 + read-only + + + READY + Flash memory module ready after low + power mode + 3 + 1 + read-only + + + WRPERR + Write protected error + 8 + 1 + read-write + + + PGAERR + Programming alignment + error + 9 + 1 + read-write + + + SIZERR + Size error + 10 + 1 + read-write + + + OPTVERR + Option validity error + 11 + 1 + read-write + + + RDERR + RDERR + 14 + 1 + read-write + + + NOTZEROERR + NOTZEROERR + 16 + 1 + read-write + + + FWWERR + FWWERR + 17 + 1 + read-write + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0x00F80000 + + + RDPRT + Read protection + 0 + 8 + + + BOR_LEV + BOR_LEV + 16 + 4 + + + SPRMOD + Selection of protection mode of WPR + bits + 8 + 1 + + + + + WRPR + WRPR + Write protection register + 0x20 + 0x20 + read-write + 0x00000000 + + + WRP + Write protection + 0 + 16 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + 1 + + + EXTI0_1 + EXTI Line[1:0] interrupts + 5 + + + EXTI2_3 + EXTI Line[3:2] interrupts + 6 + + + EXTI4_15 + EXTI Line15 and EXTI4 interrupts + 7 + + + + IMR + IMR + Interrupt mask register + (EXTI_IMR) + 0x0 + 0x20 + read-write + 0xFF840000 + + + IM0 + Interrupt Mask on line 0 + 0 + 1 + + + IM1 + Interrupt Mask on line 1 + 1 + 1 + + + IM2 + Interrupt Mask on line 2 + 2 + 1 + + + IM3 + Interrupt Mask on line 3 + 3 + 1 + + + IM4 + Interrupt Mask on line 4 + 4 + 1 + + + IM5 + Interrupt Mask on line 5 + 5 + 1 + + + IM6 + Interrupt Mask on line 6 + 6 + 1 + + + IM7 + Interrupt Mask on line 7 + 7 + 1 + + + IM8 + Interrupt Mask on line 8 + 8 + 1 + + + IM9 + Interrupt Mask on line 9 + 9 + 1 + + + IM10 + Interrupt Mask on line 10 + 10 + 1 + + + IM11 + Interrupt Mask on line 11 + 11 + 1 + + + IM12 + Interrupt Mask on line 12 + 12 + 1 + + + IM13 + Interrupt Mask on line 13 + 13 + 1 + + + IM14 + Interrupt Mask on line 14 + 14 + 1 + + + IM15 + Interrupt Mask on line 15 + 15 + 1 + + + IM16 + Interrupt Mask on line 16 + 16 + 1 + + + IM17 + Interrupt Mask on line 17 + 17 + 1 + + + IM18 + Interrupt Mask on line 18 + 18 + 1 + + + IM19 + Interrupt Mask on line 19 + 19 + 1 + + + IM20 + Interrupt Mask on line 20 + 20 + 1 + + + IM21 + Interrupt Mask on line 21 + 21 + 1 + + + IM22 + Interrupt Mask on line 22 + 22 + 1 + + + IM23 + Interrupt Mask on line 23 + 23 + 1 + + + IM24 + Interrupt Mask on line 24 + 24 + 1 + + + IM25 + Interrupt Mask on line 25 + 25 + 1 + + + IM26 + Interrupt Mask on line 27 + 26 + 1 + + + IM28 + Interrupt Mask on line 27 + 28 + 1 + + + IM29 + Interrupt Mask on line 27 + 29 + 1 + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + EM0 + Event Mask on line 0 + 0 + 1 + + + EM1 + Event Mask on line 1 + 1 + 1 + + + EM2 + Event Mask on line 2 + 2 + 1 + + + EM3 + Event Mask on line 3 + 3 + 1 + + + EM4 + Event Mask on line 4 + 4 + 1 + + + EM5 + Event Mask on line 5 + 5 + 1 + + + EM6 + Event Mask on line 6 + 6 + 1 + + + EM7 + Event Mask on line 7 + 7 + 1 + + + EM8 + Event Mask on line 8 + 8 + 1 + + + EM9 + Event Mask on line 9 + 9 + 1 + + + EM10 + Event Mask on line 10 + 10 + 1 + + + EM11 + Event Mask on line 11 + 11 + 1 + + + EM12 + Event Mask on line 12 + 12 + 1 + + + EM13 + Event Mask on line 13 + 13 + 1 + + + EM14 + Event Mask on line 14 + 14 + 1 + + + EM15 + Event Mask on line 15 + 15 + 1 + + + EM16 + Event Mask on line 16 + 16 + 1 + + + EM17 + Event Mask on line 17 + 17 + 1 + + + EM18 + Event Mask on line 18 + 18 + 1 + + + EM19 + Event Mask on line 19 + 19 + 1 + + + EM20 + Event Mask on line 20 + 20 + 1 + + + EM21 + Event Mask on line 21 + 21 + 1 + + + EM22 + Event Mask on line 22 + 22 + 1 + + + EM23 + Event Mask on line 23 + 23 + 1 + + + EM24 + Event Mask on line 24 + 24 + 1 + + + EM25 + Event Mask on line 25 + 25 + 1 + + + EM26 + Event Mask on line 26 + 26 + 1 + + + EM28 + Event Mask on line 28 + 28 + 1 + + + EM29 + Event Mask on line 29 + 29 + 1 + + + + + RTSR + RTSR + Rising Trigger selection register + (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + RT0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + RT1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + RT2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + RT3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + RT4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + RT5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + RT6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + RT7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + RT8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + RT9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + RT10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + RT11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + RT12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + RT13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + RT14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + RT15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + RT16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + RT17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + RT19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + RT20 + Rising trigger event configuration of + line 20 + 20 + 1 + + + RT21 + Rising trigger event configuration of + line 21 + 21 + 1 + + + RT22 + Rising trigger event configuration of + line 22 + 22 + 1 + + + + + FTSR + FTSR + Falling Trigger selection register + (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + FT0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + FT1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + FT2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + FT3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + FT4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + FT5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + FT6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + FT7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + FT8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + FT9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + FT10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + FT11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + FT12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + FT13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + FT14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + FT15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + FT16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + FT17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + FT19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + FT20 + Falling trigger event configuration of + line 20 + 20 + 1 + + + FT21 + Falling trigger event configuration of + line 21 + 21 + 1 + + + FT22 + Falling trigger event configuration of + line 22 + 22 + 1 + + + + + SWIER + SWIER + Software interrupt event register + (EXTI_SWIER) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWI0 + Software Interrupt on line + 0 + 0 + 1 + + + SWI1 + Software Interrupt on line + 1 + 1 + 1 + + + SWI2 + Software Interrupt on line + 2 + 2 + 1 + + + SWI3 + Software Interrupt on line + 3 + 3 + 1 + + + SWI4 + Software Interrupt on line + 4 + 4 + 1 + + + SWI5 + Software Interrupt on line + 5 + 5 + 1 + + + SWI6 + Software Interrupt on line + 6 + 6 + 1 + + + SWI7 + Software Interrupt on line + 7 + 7 + 1 + + + SWI8 + Software Interrupt on line + 8 + 8 + 1 + + + SWI9 + Software Interrupt on line + 9 + 9 + 1 + + + SWI10 + Software Interrupt on line + 10 + 10 + 1 + + + SWI11 + Software Interrupt on line + 11 + 11 + 1 + + + SWI12 + Software Interrupt on line + 12 + 12 + 1 + + + SWI13 + Software Interrupt on line + 13 + 13 + 1 + + + SWI14 + Software Interrupt on line + 14 + 14 + 1 + + + SWI15 + Software Interrupt on line + 15 + 15 + 1 + + + SWI16 + Software Interrupt on line + 16 + 16 + 1 + + + SWI17 + Software Interrupt on line + 17 + 17 + 1 + + + SWI19 + Software Interrupt on line + 19 + 19 + 1 + + + SWI20 + Software Interrupt on line + 20 + 20 + 1 + + + SWI21 + Software Interrupt on line + 21 + 21 + 1 + + + SWI22 + Software Interrupt on line + 22 + 22 + 1 + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PIF0 + Pending bit 0 + 0 + 1 + + + PIF1 + Pending bit 1 + 1 + 1 + + + PIF2 + Pending bit 2 + 2 + 1 + + + PIF3 + Pending bit 3 + 3 + 1 + + + PIF4 + Pending bit 4 + 4 + 1 + + + PIF5 + Pending bit 5 + 5 + 1 + + + PIF6 + Pending bit 6 + 6 + 1 + + + PIF7 + Pending bit 7 + 7 + 1 + + + PIF8 + Pending bit 8 + 8 + 1 + + + PIF9 + Pending bit 9 + 9 + 1 + + + PIF10 + Pending bit 10 + 10 + 1 + + + PIF11 + Pending bit 11 + 11 + 1 + + + PIF12 + Pending bit 12 + 12 + 1 + + + PIF13 + Pending bit 13 + 13 + 1 + + + PIF14 + Pending bit 14 + 14 + 1 + + + PIF15 + Pending bit 15 + 15 + 1 + + + PIF16 + Pending bit 16 + 16 + 1 + + + PIF17 + Pending bit 17 + 17 + 1 + + + PIF19 + Pending bit 19 + 19 + 1 + + + PIF20 + Pending bit 20 + 20 + 1 + + + PIF21 + Pending bit 21 + 21 + 1 + + + PIF22 + Pending bit 22 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Channel-x selection + 18 + 1 + + + CHSEL17 + Channel-x selection + 17 + 1 + + + CHSEL16 + Channel-x selection + 16 + 1 + + + CHSEL15 + Channel-x selection + 15 + 1 + + + CHSEL14 + Channel-x selection + 14 + 1 + + + CHSEL13 + Channel-x selection + 13 + 1 + + + CHSEL12 + Channel-x selection + 12 + 1 + + + CHSEL11 + Channel-x selection + 11 + 1 + + + CHSEL10 + Channel-x selection + 10 + 1 + + + CHSEL9 + Channel-x selection + 9 + 1 + + + CHSEL8 + Channel-x selection + 8 + 1 + + + CHSEL7 + Channel-x selection + 7 + 1 + + + CHSEL6 + Channel-x selection + 6 + 1 + + + CHSEL5 + Channel-x selection + 5 + 1 + + + CHSEL4 + Channel-x selection + 4 + 1 + + + CHSEL3 + Channel-x selection + 3 + 1 + + + CHSEL2 + Channel-x selection + 2 + 1 + + + CHSEL1 + Channel-x selection + 1 + 1 + + + CHSEL0 + Channel-x selection + 0 + 1 + + + + + DR + DR + data register + 0x40 + 0x20 + read-only + 0x00000000 + + + DATA + Converted data + 0 + 16 + + + + + CALFACT + CALFACT + ADC Calibration factor + 0xB4 + 0x20 + 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when Core is + halted + 0 + 1 + + + DBG_TIMER6_STOP + Debug Timer 6 stopped when Core is + halted + 4 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is + halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core + is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when + Core is halted + 12 + 1 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout mode stopped when + core is halted + 21 + 1 + + + DBG_I2C2_STOP + I2C2 SMBUS timeout mode stopped when + core is halted + 22 + 1 + + + DBG_LPTIMER_STOP + LPTIM1 counter stopped when core is + halted + 31 + 1 + + + + + APB2_FZ + APB2_FZ + APB High Freeze Register + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIMER21_STOP + Debug Timer 21 stopped when Core is + halted + 2 + 1 + + + DBG_TIMER22_STO + Debug Timer 22 stopped when Core is + halted + 6 + 1 + + + + + + + TIM2 + General-purpose-timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 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drive enable + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x00000020 + + + FCRSF + LCD Frame Control Register + Synchronization flag + 5 + 1 + read-only + + + RDY + Ready flag + 4 + 1 + read-only + + + UDD + Update Display Done + 3 + 1 + read-only + + + UDR + Update display request + 2 + 1 + write-only + + + SOF + Start of frame flag + 1 + 1 + read-only + + + ENS + ENS + 0 + 1 + read-only + + + + + CLR + CLR + clear register + 0xC + 0x20 + write-only + 0x00000000 + + + UDDC + Update display done clear + 3 + 1 + + + SOFC + Start of frame flag clear + 1 + 1 + + + + + RAM_COM0 + RAM_COM0 + display memory + 0x14 + 0x20 + read-write + 0x00000000 + + + S30 + S30 + 30 + 1 + + + S29 + S29 + 29 + 1 + + + S28 + S28 + 28 + 1 + + + S27 + S27 + 27 + 1 + + + S26 + S26 + 26 + 1 + + + S25 + S25 + 25 + 1 + + + S24 + S24 + 24 + 1 + + + S23 + S23 + 23 + 1 + + + S22 + S22 + 22 + 1 + + + S21 + S21 + 21 + 1 + + + S20 + S20 + 20 + 1 + + + S19 + S19 + 19 + 1 + + + S18 + S18 + 18 + 1 + + + S17 + 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read-write + 0x00000000 + + + S31 + S31 + 31 + 1 + + + S30 + S30 + 30 + 1 + + + S29 + S29 + 29 + 1 + + + S28 + S28 + 28 + 1 + + + S27 + S27 + 27 + 1 + + + S26 + S26 + 26 + 1 + + + S25 + S25 + 25 + 1 + + + S24 + S24 + 24 + 1 + + + S23 + S23 + 23 + 1 + + + S22 + S22 + 22 + 1 + + + S21 + S21 + 21 + 1 + + + S20 + S20 + 20 + 1 + + + S19 + S19 + 19 + 1 + + + S18 + S18 + 18 + 1 + + + S17 + S17 + 17 + 1 + + + S16 + S16 + 16 + 1 + + + S15 + S15 + 15 + 1 + + + S14 + S14 + 14 + 1 + + + S13 + S13 + 13 + 1 + + + S12 + S12 + 12 + 1 + + + S11 + S11 + 11 + 1 + + + S10 + S10 + 10 + 1 + + + S09 + S09 + 9 + 1 + + + S08 + S08 + 8 + 1 + + + S07 + S07 + 7 + 1 + + + S06 + S06 + 6 + 1 + + + S05 + S05 + 5 + 1 + + + S04 + S04 + 4 + 1 + + + S03 + S03 + 3 + 1 + + + S02 + S02 + 2 + 1 + + + S01 + S01 + 1 + 1 + + + S00 + S00 + 0 + 1 + + + + + RAM_COM6 + RAM_COM6 + display memory + 0x44 + 0x20 + read-write + 0x00000000 + + + S31 + S31 + 31 + 1 + + + S30 + S30 + 30 + 1 + + + S29 + S29 + 29 + 1 + + + S28 + S28 + 28 + 1 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1 + + + S22 + S22 + 22 + 1 + + + S21 + S21 + 21 + 1 + + + S20 + S20 + 20 + 1 + + + S19 + S19 + 19 + 1 + + + S18 + S18 + 18 + 1 + + + S17 + S17 + 17 + 1 + + + S16 + S16 + 16 + 1 + + + S15 + S15 + 15 + 1 + + + S14 + S14 + 14 + 1 + + + S13 + S13 + 13 + 1 + + + S12 + S12 + 12 + 1 + + + S11 + S11 + 11 + 1 + + + S10 + S10 + 10 + 1 + + + S09 + S09 + 9 + 1 + + + S08 + S08 + 8 + 1 + + + S07 + S07 + 7 + 1 + + + S06 + S06 + 6 + 1 + + + S05 + S05 + 5 + 1 + + + S04 + S04 + 4 + 1 + + + S03 + S03 + 3 + 1 + + + S02 + S02 + 2 + 1 + + + S01 + S01 + 1 + 1 + + + S00 + S00 + 0 + 1 + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + MPU_TYPER + MPU_TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction + regions + 16 + 8 + + + + + MPU_CTRL + MPU_CTRL + MPU control register + 0x4 + 0x20 + read-only + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard + fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to + default memory map + 2 + 1 + + + + + MPU_RNR + MPU_RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + MPU_RBAR + MPU_RBAR + MPU region base address + register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + MPU_RASR + MPU_RASR + MPU region attribute and size + register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection + region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable + bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CSR + CSR + SysTick control and status + register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request + enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + RVR + RVR + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + CVR + CVR + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value + register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS + value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Architecture + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 7 + 25 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + + + diff --git a/firmware/syscalls/syscalls.c b/firmware/syscalls/syscalls.c new file mode 100644 index 0000000..ff4453f --- /dev/null +++ b/firmware/syscalls/syscalls.c @@ -0,0 +1,42 @@ + + +extern char __ld_sheap; // Defined by the linker +extern char __ld_eheap; +char* _sbrk(int incr) { + + static char *heap_end; + char *prev_heap_end; + + if (heap_end == 0) { + heap_end = &__ld_sheap; + } + prev_heap_end = heap_end; + if (heap_end + incr > &__ld_eheap) { + return 0; + } + + heap_end += incr; + return (char*) prev_heap_end; + } +int _isatty(int fd) { + return 1; +} +int _close(int fd) { + return 0; +} +int _open(int fd) { + return 0; +} +int _fstat(void) { + return 0; +} +int _lseek(void) { + return 0; +} +int _read(void) { + return 0; +} +int _write(int fd, const void *buf, int count) { + //sendString((char*)buf, count); + return count; +} diff --git a/firmware/unique-id.c b/firmware/unique-id.c new file mode 100644 index 0000000..9ccda56 --- /dev/null +++ b/firmware/unique-id.c @@ -0,0 +1,11 @@ +#include "unique-id.h" + +#define UNIQUE_ID_BASE_ADDR 0x1FF80050UL + +void unique_id_get(uint64_t *lot_wafer_number, uint32_t *unique_number) +{ + if (lot_wafer_number) + *lot_wafer_number = *((uint64_t *)UNIQUE_ID_BASE_ADDR); + if (unique_number) + *unique_number = *((uint32_t *)(UNIQUE_ID_BASE_ADDR + 0x14UL)); +} diff --git a/firmware/unique-id.h b/firmware/unique-id.h new file mode 100644 index 0000000..6789027 --- /dev/null +++ b/firmware/unique-id.h @@ -0,0 +1,8 @@ +#ifndef _UNIQUE_ID_H_ +#define _UNIQUE_ID_H_ + +#include + +void unique_id_get(uint64_t *lot_wafer_number, uint32_t *unique_number); + +#endif /* _UNIQUE_ID_H_ */ diff --git a/firmware/usb.c b/firmware/usb.c new file mode 100644 index 0000000..fcb9986 --- /dev/null +++ b/firmware/usb.c @@ -0,0 +1,668 @@ +#include "usb.h" +#include +#include + +#define ENDPOINT_COUNT (8) + +enum endpoint_state {EP_STATE_DISABLED, EP_STATE_NAK, EP_STATE_STALL, EP_STATE_VALID}; + +static void (*ep_rx_data_callback)(uint8_t endpoint, const uint8_t *buffer, uint32_t len) = NULL; +static enum control_state (*ep_rx_setup_received_callback)(uint8_t endpoint, const struct setup_packet *setup_pkg) = NULL; +static void (*ep_tx_complete_callback)(uint8_t endpoint); +static void (*usb_sof_callback)(void) = NULL; +static void (*usb_reset_callback)(void) = NULL; +static void (*usb_configured_callback)(uint16_t config_idx) = NULL; + +struct usb_endpoint_info { + uint16_t rx_pma_size; + uint16_t tx_pma_size; + enum usb_ep_type type; + struct setup_packet last_setup; + enum control_state ctrl_state; + volatile uint16_t *ep_reg; + + uint32_t tx_count; + const uint8_t *tx_ptr; + + uint32_t rx_size; + uint8_t *rx_buffer; +}; + +static const struct usb_descriptor_entry *usb_descriptors = NULL; +static uint16_t * const pma_base_ptr = (uint16_t *)0x40006000UL; + +struct usb_endpoint_info endpoints[ENDPOINT_COUNT]; + +static void setup_usb_clock(void) +{ + uint32_t reload_val; + const uint32_t felim = 0x22; + const uint32_t f_target = 48000000UL; + const uint32_t f_usb_sof = 1000UL; + + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; + /* Enable the internal voltage reference. This is needed for HSI48 */ + SYSCFG->CFGR3 |= SYSCFG_CFGR3_EN_VREFINT; + while (!(SYSCFG->CFGR3 & SYSCFG_CFGR3_VREFINT_RDYF)); + SYSCFG->CFGR3 |= SYSCFG_CFGR3_ENREF_HSI48; + + RCC->CRRCR = RCC_CRRCR_HSI48ON; + while(!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)); + RCC->CCIPR |= RCC_CCIPR_HSI48SEL; + + /* Configure Clock recovery from USB SOF (1kHz) */ + RCC->APB1ENR |= RCC_APB1ENR_CRSEN; + reload_val = (f_target / f_usb_sof) - 1; + CRS->CFGR = (reload_val & 0xFFFF) | (felim << 16) | CRS_CFGR_SYNCSRC_1; + CRS->CR = CRS_CR_CEN | CRS_CR_AUTOTRIMEN; +} + +void usb_init(const struct usb_callbacks *callbacks) +{ + setup_usb_clock(); + + /* Activate register clock for USB */ + RCC->APB1ENR |= RCC_APB1ENR_USBEN; + + /* Power up the USB interface but hold in reset */ + USB->CNTR = USB_CNTR_FRES; + + endpoints[0].ep_reg = &USB->EP0R; + endpoints[1].ep_reg = &USB->EP1R; + endpoints[2].ep_reg = &USB->EP2R; + endpoints[3].ep_reg = &USB->EP3R; + endpoints[4].ep_reg = &USB->EP4R; + endpoints[5].ep_reg = &USB->EP5R; + endpoints[6].ep_reg = &USB->EP6R; + endpoints[7].ep_reg = &USB->EP7R; + + /* Setup the callbacks */ + ep_rx_data_callback = callbacks->ep_rx_data_callback; + ep_tx_complete_callback = callbacks->ep_tx_complete_callback; + ep_rx_setup_received_callback = callbacks->ep_rx_setup_received_callback; + usb_configured_callback = callbacks->usb_configured_callback; + usb_reset_callback = callbacks->usb_reset_callback; + usb_sof_callback = callbacks->usb_sof_callback; +} + +static void write_b_table(uint32_t addr, uint16_t value) +{ + volatile uint16_t *ptr = pma_base_ptr; + + ptr += (addr >> 1); + *ptr = value; +} + +static uint16_t read_b_table(uint32_t addr) +{ + volatile uint16_t *ptr = pma_base_ptr; + + ptr += (addr >> 1); + return *ptr; +} + +static uint16_t read_rx_pma(uint8_t ep, uint8_t *buff, uint32_t size) +{ + uint16_t rx_btable_entry; + uint16_t pma_addr; + uint8_t *app_addr; + uint16_t count; + uint16_t i; + + rx_btable_entry = read_b_table(ep * 8 + 6); + count = rx_btable_entry & 0x3FF; + + pma_addr = read_b_table(ep * 8 + 4); + app_addr = (uint8_t *)pma_base_ptr; + app_addr += (pma_addr >> 0); + + /* Byte addresed writes seem to work just fine */ + for (i = 0; i < count && i < size; i++) { + buff[i] = app_addr[i]; + } + + return count; +} + +static void write_tx_pma(uint8_t ep, const uint8_t *src, uint32_t len) +{ + uint16_t tx_addr; + uint16_t *pma = pma_base_ptr; + uint32_t i; + uint32_t halfword_cnt; + bool padding; + + write_b_table(ep * 8 + 2, len); + + if (!len) + return; + + tx_addr = read_b_table(ep * 8); + padding = len % 2 ? true : false; + halfword_cnt = len >> 1; + + pma += tx_addr >> 1; + + for (i = 0; i < halfword_cnt; i++) { + pma[i] = (uint16_t)src[2 * i] | (((uint16_t)src[2 * i + 1]) << 8); + } + + if (padding) { + pma[i] = (uint16_t)src[2 * i]; + } + +} + +static const struct usb_descriptor_entry *find_descriptor_from_setup_request(uint16_t w_index, uint16_t w_value) +{ + int i; + const struct usb_descriptor_entry *entry = NULL; + + for (i = 0; usb_descriptors[i].descriptor != NULL; i++) { + if (usb_descriptors[i].w_index == w_index && usb_descriptors[i].w_value == w_value) { + entry = &usb_descriptors[i]; + break; + } + } + + return entry; +} + +void usb_endpoint_config(enum usb_ep_type type, uint8_t epnum, bool rx, bool tx) +{ + uint16_t epreg = 0; + struct usb_endpoint_info *ep_info; + + if (epnum >= ENDPOINT_COUNT) + return; + + ep_info = &endpoints[epnum]; + + write_b_table(epnum * 8 + 0, 64 + epnum * 136); + write_b_table(epnum * 8 + 2, 0); + write_b_table(epnum * 8 + 4, 64 + epnum * 136 + 72); + write_b_table(epnum * 8 + 6, (1 << 10) | (1<<15)); + + epreg = *ep_info->ep_reg; + epreg &= ~(1<<15); + + switch (type) { + case EP_CONTROL: + epreg |= (1<<9); + ep_info->type = EP_CONTROL; + ep_info->ctrl_state = CONTROL_SETUP; + ep_info->tx_pma_size = 64; + ep_info->rx_pma_size = 64; + case EP_BULK: + ep_info->type = EP_BULK; + ep_info->ctrl_state = CONTROL_SETUP; + ep_info->tx_pma_size = 64; + ep_info->rx_pma_size = 64; + break; + case EP_INTERRUPT: + epreg |= (1<<10) | (1<<9); + ep_info->type = EP_INTERRUPT; + ep_info->ctrl_state = CONTROL_SETUP; + ep_info->tx_pma_size = 64; + ep_info->rx_pma_size = 64; + break; + case EP_ISOCHRON: + epreg |= (1<<10); + ep_info->type = EP_ISOCHRON; + ep_info->ctrl_state = CONTROL_SETUP; + ep_info->tx_pma_size = 64; + ep_info->rx_pma_size = 64; + break; + default: + return; + break; + } + + if (tx) { + epreg |= (1<<5); + } + + if (rx) { + epreg |= (1<<13); + } + + epreg |= epnum; + + *ep_info->ep_reg = epreg; +} + +static void usb_endpoint_reset_int_flags(uint8_t endpoint, bool rx, bool tx) +{ + uint16_t ep_reg; + + if (endpoint >= ENDPOINT_COUNT) + return; + + ep_reg = *endpoints[endpoint].ep_reg; + ep_reg &= ~((1<<14) | (1<<6) | (1<<5) | (1<<13) | (1<<12) | (1<<4)); + + /* Dont clear flag */ + if (rx) { + ep_reg &= ~(1<<15); + } else { + ep_reg |= (1<<15); + } + if (tx) { + ep_reg &= ~(1<<7); + } else { + ep_reg |= (1<<7); + } + + + *endpoints[endpoint].ep_reg = ep_reg; +} + +static void usb_endpoint_set_rx_state(uint8_t endpoint, enum endpoint_state state) +{ + uint16_t ep_reg; + uint16_t ep_rx_target = 0; + + if (endpoint >= ENDPOINT_COUNT) + return; + + ep_reg = *endpoints[endpoint].ep_reg; + + /* Mask out all toggle flags that we don't want to change */ + ep_reg &= ~((1<<14) | (1<<6) | (1<<5) | (1<<4)); + + /* Dont clear flag */ + ep_reg |= (1<<15) | (1<<7); + + /* Prepare the target value */ + switch (state) { + case EP_STATE_DISABLED: + ep_rx_target = 0; + break; + case EP_STATE_NAK: + ep_rx_target = (1<<13); + break; + case EP_STATE_VALID: + ep_rx_target = (1<<13) | (1<<12); + break; + case EP_STATE_STALL: + ep_rx_target = (1<<12); + default: + return; + } + + /* Generate toggle mask for the TX bits */ + ep_reg ^= ep_rx_target; + + *endpoints[endpoint].ep_reg = ep_reg; +} + +static void usb_endpoint_set_tx_state(uint8_t endpoint, enum endpoint_state state) +{ + uint16_t ep_reg; + uint16_t ep_tx_target = 0; + + if (endpoint >= ENDPOINT_COUNT) + return; + + ep_reg = *endpoints[endpoint].ep_reg; + + /* Mask out all toggle flags that we don't want to change */ + ep_reg &= ~((1<<14) | (1<<13) | (1<<12) | (1<<6)); + + /* Dont clear flag */ + ep_reg |= (1<<15) | (1<<7); + + /* Prepare the target value */ + switch (state) { + case EP_STATE_DISABLED: + ep_tx_target = 0; + break; + case EP_STATE_NAK: + ep_tx_target = (1<<5); + break; + case EP_STATE_VALID: + ep_tx_target = (1<<5) | (1<<4); + break; + case EP_STATE_STALL: + ep_tx_target = (1<<4); + default: + return; + } + + /* Generate toggle mask for the TX bits */ + ep_reg ^= ep_tx_target; + + *endpoints[endpoint].ep_reg = ep_reg; +} + +void usb_endpoint_stall(uint8_t endpoint, bool tx_dir, bool rx_dir) +{ + if (tx_dir) + usb_endpoint_set_tx_state(endpoint, EP_STATE_STALL); +} + + +int usb_endpoint_send(uint8_t endpoint, const uint8_t *data, uint32_t len) +{ + struct usb_endpoint_info *epinfo; + uint32_t tx_cnt; + + if (endpoint >= ENDPOINT_COUNT) + return -1001; + + epinfo = &endpoints[endpoint]; + if (epinfo->tx_pma_size == 0) + return -1; + + tx_cnt = len < epinfo->tx_pma_size ? len : epinfo->tx_pma_size; + + /* Copy data to pma and save the data pointer to the next word to be transmitted */ + if (tx_cnt < len) { + epinfo->tx_ptr = &data[tx_cnt]; + epinfo->tx_count = len - tx_cnt; + } else { + epinfo->tx_count = 0; + epinfo->tx_ptr = NULL; + } + + write_tx_pma(endpoint, data, tx_cnt); + + /* Prepare endpoint for TX */ + usb_endpoint_set_tx_state(endpoint, EP_STATE_VALID); + + return 0; +} + +int usb_endpoint_prepare_receive(uint8_t endpoint, uint8_t *buffer, uint32_t bufflen) +{ + struct usb_endpoint_info *info; + + if (endpoint >= ENDPOINT_COUNT) + return -1001; + + info = &endpoints[endpoint]; + + if (info->rx_buffer || info->rx_size) { + return -1; + } + + __disable_irq(); + info->rx_buffer = buffer; + info->rx_size = bufflen; + usb_endpoint_set_rx_state(endpoint, EP_STATE_VALID); + __enable_irq(); + + return 0; +} + +void usb_endpoint_send_status_stage(uint8_t endpoint) +{ + struct usb_endpoint_info *info; + + if (endpoint >= ENDPOINT_COUNT) + return; + + info = &endpoints[endpoint]; + info->ctrl_state = CONTROL_STATUS_TX; + usb_endpoint_send(endpoint, NULL, 0); +} + +void usb_enable(const struct usb_descriptor_entry *descriptors) +{ + if (!descriptors) + return; + + usb_descriptors = descriptors; + + /* Enable device with address 0 */ + USB->DADDR = USB_DADDR_EF; + + /* Clear all interrupts */ + USB->ISTR = 0; + + /* Set buffer description table to beginning of PMA */ + USB->BTABLE = 0x0U; + + /* Actiovate USB module (clear reset bit) and setup the interrupt masks */ + USB->CNTR = USB_CNTR_CTRM | USB_CNTR_ERRM | USB_CNTR_RESETM | USB_CNTR_SOFM; + + /* Enable internal D+ pullup to tell the host we're here */ + USB->BCDR = USB_BCDR_DPPU; + + NVIC_EnableIRQ(USB_IRQn); +} + + +static void usb_handle_reset(void) +{ + int i; + + /* Reset USB address */ + USB->DADDR = USB_DADDR_EF; + + for (i = 0; i < ENDPOINT_COUNT; i++) { + endpoints[i].rx_size = 0; + endpoints[i].rx_buffer = NULL; + endpoints[i].tx_count = 0; + endpoints[i].tx_ptr = NULL; + } + + usb_endpoint_config(EP_CONTROL, 0, true, true); + usb_endpoint_set_rx_state(0, EP_STATE_VALID); +} + +void usb_ep0_send_status(void) +{ + struct usb_endpoint_info *ep_info; + + ep_info = &endpoints[0]; + ep_info->ctrl_state = CONTROL_STATUS_TX; + + usb_endpoint_send(0, NULL, 0); +} + +void usb_ep0_handle_setup(void) +{ + uint16_t cnt; + enum control_state next_state; + const struct usb_descriptor_entry *descriptor; + struct usb_endpoint_info *ep_info; + struct setup_packet *setup; + + ep_info = &endpoints[0]; + ep_info->ctrl_state = CONTROL_SETUP; + + setup = &ep_info->last_setup; + + cnt = read_rx_pma(0, (uint8_t *)setup, 8); + + if (cnt != 8) { + usb_endpoint_stall(0, true, true); + return; + } + + if ((setup->bm_req_type == 0x80 || setup->bm_req_type == 0x81 || setup->bm_req_type == 0x82) && setup->b_request == 6) { + /* Get descriptor request */ + descriptor = find_descriptor_from_setup_request(setup->w_index, setup->w_value); + if (!descriptor) { + usb_endpoint_stall(0, true, true); + } + + cnt = setup->w_length < descriptor->size ? setup->w_length : descriptor->size; + + usb_endpoint_send(0, descriptor->descriptor, cnt); + ep_info->ctrl_state = CONTROL_DATA_TX; + } else if (setup->bm_req_type == 0x00 && setup->b_request == 5) { + /* Set address command + * Send out status stage and set address after status has finished + */ + usb_ep0_send_status(); + } else if (setup->bm_req_type == 0x00 && setup->b_request == 9) { + /* Set configuration */ + if (usb_configured_callback) + usb_configured_callback(setup->w_value); + usb_ep0_send_status(); + } else { + next_state = CONTROL_NOT_HANDLED; + + /* Check if the callback for setup requests is set and try to handle it this way */ + if (ep_rx_setup_received_callback) + next_state = ep_rx_setup_received_callback(0, setup); + + /* We could not handle the setup request if handle state != 0 */ + if (next_state == CONTROL_NOT_HANDLED) { + usb_endpoint_stall(0, true, true); + } else { + /* Control handled */ + switch (next_state) { + case CONTROL_STATUS_TX: + usb_ep0_send_status(); + break; + case CONTROL_DATA_TX: + break; + case CONTROL_DATA_RX: + break; + default: + usb_endpoint_stall(0, true, true); + break; + } + } + + ep_info->ctrl_state = (next_state != CONTROL_NOT_HANDLED ? next_state : CONTROL_SETUP); + } + + return; +} + +void usb_ep0_handle_tx(void) +{ + struct usb_endpoint_info *info = &endpoints[0]; + + if (info->tx_count) { + /* Do the rest */ + usb_endpoint_send(0, info->tx_ptr, info->tx_count); + } else { + if (info->ctrl_state == CONTROL_DATA_TX) { + info->ctrl_state = CONTROL_STATUS_RX; + /* Listen for new setup packets */ + usb_endpoint_set_rx_state(0, EP_STATE_VALID); + } else if (info->ctrl_state == CONTROL_STATUS_TX) { + /* we've sent a status back. Check if we should set our address now */ + if (info->last_setup.bm_req_type == 0x00 && info->last_setup.b_request == 0x5) { + USB->DADDR = USB_DADDR_EF | info->last_setup.w_value; + } + + info->ctrl_state = CONTROL_SETUP; + /* Listen for new setup packets */ + usb_endpoint_set_rx_state(0, EP_STATE_VALID); + } else { + if (ep_tx_complete_callback) + ep_tx_complete_callback(0); + } + } +} + +void usb_handle_rx_packet(uint8_t ep) +{ + uint16_t epreg; + struct usb_endpoint_info *info; + uint16_t pkg_len; + uint8_t *buffer; + + info = &endpoints[ep]; + epreg = *info->ep_reg; + + usb_endpoint_reset_int_flags(ep, true, false); + + + if (epreg & (1<<11) && ep == 0) { + info->ctrl_state = CONTROL_SETUP; + usb_ep0_handle_setup(); + } else if (ep == 0 && info->ctrl_state == CONTROL_STATUS_RX) { + info->ctrl_state = CONTROL_SETUP; + + /* Check the received status frame */ + pkg_len = read_rx_pma(0, NULL, 0); + if (pkg_len != 0) { + usb_endpoint_stall(0, true, true); + } else { + /* Ready to receive next datum */ + usb_endpoint_set_rx_state(0, EP_STATE_VALID); + } + } else { + if (epreg & (1<<11)) { + (void)read_rx_pma(ep, (uint8_t *)&info->last_setup, 8); + if (ep_rx_setup_received_callback) + ep_rx_setup_received_callback(ep, &info->last_setup); + } + + if (info->rx_buffer && info->rx_size) { + pkg_len = read_rx_pma(ep, info->rx_buffer, info->rx_size); + buffer = info->rx_buffer; + info->rx_size = 0; + info->rx_buffer = 0; + ep_rx_data_callback(ep, buffer, pkg_len); + } + + } +} + +void usb_handle_tx_packet_sent(uint8_t ep) +{ + struct usb_endpoint_info *info = &endpoints[ep]; + + usb_endpoint_reset_int_flags(ep, false, true); + + if (ep == 0) { + usb_ep0_handle_tx(); + } else { + if (info->tx_count && info->tx_ptr) { + usb_endpoint_send(ep, info->tx_ptr, info->tx_count); + } else { + if (ep_tx_complete_callback) + ep_tx_complete_callback(ep); + } + } +} + +void USB_IRQHandler(void) +{ + uint16_t istr = USB->ISTR; + uint8_t endpoint; + bool dir_tx; + + if (istr & USB_ISTR_RESET) { + USB->ISTR = (uint16_t)(~USB_ISTR_RESET); + usb_handle_reset(); + if (usb_reset_callback) + usb_reset_callback(); + } + + if (istr & USB_ISTR_CTR) { + /* correct transfer interrupt */ + endpoint = istr & USB_ISTR_EP_ID; + dir_tx = (istr & USB_ISTR_DIR) ? false : true; + + if (dir_tx) { + usb_handle_tx_packet_sent(endpoint); + } else { + usb_handle_rx_packet(endpoint); + } + + /* Clear interrupt */ + USB->ISTR = (uint16_t)(~USB_ISTR_CTR); + + } + + if (istr & USB_ISTR_SOF) { + USB->ISTR = (uint16_t)(~USB_ISTR_SOF); + if (usb_sof_callback) + usb_sof_callback(); + } + + if (istr & USB_ISTR_ERR) { + USB->ISTR = (uint16_t)(~USB_ISTR_ERR); + } + + __DSB(); +} diff --git a/firmware/usb.h b/firmware/usb.h new file mode 100644 index 0000000..bc84036 --- /dev/null +++ b/firmware/usb.h @@ -0,0 +1,54 @@ +#ifndef _USB_H_ +#define _USB_H_ + +#include +#include + +enum control_state {CONTROL_SETUP, CONTROL_DATA_TX, CONTROL_DATA_RX, CONTROL_STATUS_RX, CONTROL_STATUS_TX, CONTROL_NOT_HANDLED}; + + +struct usb_descriptor_entry { + uint16_t w_index; + uint16_t w_value; + const uint8_t *descriptor; + uint32_t size; +}; + +enum usb_ep_type { + EP_CONTROL, + EP_BULK, + EP_ISOCHRON, + EP_INTERRUPT +}; + +struct setup_packet { + uint8_t bm_req_type; + uint8_t b_request; + uint16_t w_value; + uint16_t w_index; + uint16_t w_length; +}; + +struct usb_callbacks { + void (*ep_rx_data_callback)(uint8_t endpoint, const uint8_t *buffer, uint32_t len); + enum control_state (*ep_rx_setup_received_callback)(uint8_t endpoint, const struct setup_packet *setup_pkg); + void (*ep_tx_complete_callback)(uint8_t endpoint); + void (*usb_sof_callback)(void); + void (*usb_reset_callback)(void); + void (*usb_configured_callback)(uint16_t config_idx); +}; + +void usb_init(const struct usb_callbacks *callbacks); + +void usb_enable(const struct usb_descriptor_entry *descriptors); +void usb_endpoint_send_status_stage(uint8_t endpoint); + +void usb_endpoint_stall(uint8_t endpoint, bool tx_dir, bool rx_dir); + +void usb_endpoint_config(enum usb_ep_type type, uint8_t epnum, bool rx, bool tx); + +int usb_endpoint_prepare_receive(uint8_t endpoint, uint8_t *buffer, uint32_t bufflen); + +int usb_endpoint_send(uint8_t endpoint, const uint8_t *data, uint32_t len); + +#endif /* _USB_H_ */ diff --git a/sustain-kbd-config/.gitignore b/sustain-kbd-config/.gitignore new file mode 100644 index 0000000..983c8d0 --- /dev/null +++ b/sustain-kbd-config/.gitignore @@ -0,0 +1,60 @@ +# Created by https://www.toptal.com/developers/gitignore/api/c++ +# Edit at https://www.toptal.com/developers/gitignore?templates=c++ + +### C++ ### +# Prerequisites +*.d + +# Compiled Object files +*.slo +*.lo +*.o +*.obj + +# Precompiled Headers +*.gch +*.pch + +# Compiled Dynamic libraries +*.so +*.dylib +*.dll + +# Fortran module files +*.mod +*.smod + +# Compiled Static libraries +*.lai +*.la +*.a +*.lib + +# Executables +*.exe +*.out +*.app + +# End of https://www.toptal.com/developers/gitignore/api/c++ + +# Created by https://www.toptal.com/developers/gitignore/api/cmake +# Edit at https://www.toptal.com/developers/gitignore?templates=cmake + +### CMake ### +CMakeLists.txt.user +CMakeCache.txt +CMakeFiles +CMakeScripts +Testing +Makefile +cmake_install.cmake +install_manifest.txt +compile_commands.json +CTestTestfile.cmake +_deps + +### CMake Patch ### +# External projects +*-prefix/ + +# End of https://www.toptal.com/developers/gitignore/api/cmake diff --git a/sustain-kbd-config/CMakeLists.txt b/sustain-kbd-config/CMakeLists.txt new file mode 100644 index 0000000..004e4a8 --- /dev/null +++ b/sustain-kbd-config/CMakeLists.txt @@ -0,0 +1,74 @@ +cmake_minimum_required(VERSION 3.5) + +project(sustain-kbd-config VERSION 0.1 LANGUAGES CXX) + +set(CMAKE_INCLUDE_CURRENT_DIR ON) + +set(CMAKE_AUTOUIC ON) +set(CMAKE_AUTOMOC ON) +set(CMAKE_AUTORCC ON) + +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) + + +find_package(PkgConfig REQUIRED) +pkg_search_module(LIBUSB REQUIRED libusb-1.0) + +# QtCreator supports the following variables for Android, which are identical to qmake Android variables. +# Check https://doc.qt.io/qt/deployment-android.html for more information. +# They need to be set before the find_package( ...) calls below. + +#if(ANDROID) +# set(ANDROID_PACKAGE_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/android") +# if (ANDROID_ABI STREQUAL "armeabi-v7a") +# set(ANDROID_EXTRA_LIBS +# ${CMAKE_CURRENT_SOURCE_DIR}/path/to/libcrypto.so +# ${CMAKE_CURRENT_SOURCE_DIR}/path/to/libssl.so) +# endif() +#endif() + +find_package(QT NAMES Qt6 Qt5 COMPONENTS Widgets REQUIRED) +find_package(Qt${QT_VERSION_MAJOR} COMPONENTS Widgets REQUIRED) + +set(PROJECT_SOURCES + main.cpp + mainwindow.cpp + mainwindow.h + mainwindow.ui + libusbwrapper.cpp + libusbwrapper.h + sustainpedalkeyboard.h + sustainpedalkeyboard.cpp +) + +if(${QT_VERSION_MAJOR} GREATER_EQUAL 6) + qt_add_executable(sustain-kbd-config + MANUAL_FINALIZATION + ${PROJECT_SOURCES} + ) +else() + if(ANDROID) + add_library(sustain-kbd-config SHARED + ${PROJECT_SOURCES} + ) + else() + add_executable(sustain-kbd-config + ${PROJECT_SOURCES} + ) + endif() +endif() + +target_link_libraries(sustain-kbd-config PRIVATE Qt${QT_VERSION_MAJOR}::Widgets ${LIBUSB_LDFLAGS}) +target_include_directories(${PROJECT_NAME} PRIVATE ${LIBUSB_INCLUDE_DIRS}) + +set_target_properties(sustain-kbd-config PROPERTIES + MACOSX_BUNDLE_GUI_IDENTIFIER my.example.com + MACOSX_BUNDLE_BUNDLE_VERSION ${PROJECT_VERSION} + MACOSX_BUNDLE_SHORT_VERSION_STRING ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR} + CXX_STANDARD 17 +) + +if(QT_VERSION_MAJOR EQUAL 6) + qt_finalize_executable(sustain-kbd-config) +endif() diff --git a/sustain-kbd-config/libusbwrapper.cpp b/sustain-kbd-config/libusbwrapper.cpp new file mode 100644 index 0000000..853889d --- /dev/null +++ b/sustain-kbd-config/libusbwrapper.cpp @@ -0,0 +1,137 @@ +#include "libusbwrapper.h" +#include +#include + +UsbDevice::UsbDevice(libusb_device *device) +{ + int res; + + this->dev = device; + res = libusb_get_device_descriptor(device, &this->devdesc); + this->device_handle = nullptr; + + if (res == 0) { + this->vendor_id = devdesc.idVendor; + this->product_id = devdesc.idProduct; + } + +} + +UsbDevice::UsbDevice(UsbDevice &&d) +{ + vendor_id = std::move(d.vendor_id); + product_id = std::move(d.product_id); + dev = d.dev; + devdesc = d.devdesc; + device_handle = std::move(d.device_handle); +} + +UsbDevice::~UsbDevice() +{ + /* Nothing to do here. Our device handle will be automatically closed once the shared pointer is released */ +} + +std::vector UsbDevice::find_devices(uint16_t vendor_id, uint16_t product_id) +{ + auto ret_vector = std::vector(); + libusb_device **devlist; + + int res = libusb_get_device_list(NULL, &devlist); + if (res > 0) { + for (int idx = 0; idx < res; idx++) { + auto d = UsbDevice(devlist[idx]); + if (d.get_product_id() == product_id && d.get_vendor_id() == vendor_id) + ret_vector.push_back(std::move(d)); + } + } + + return ret_vector; +} + +bool UsbDevice::opened() +{ + return !!(this->device_handle != nullptr); +} + +int UsbDevice::open() +{ + int ret; + libusb_device_handle *handle; + + if (this->dev) { + ret = libusb_open(this->dev, &handle); + } else { + handle = libusb_open_device_with_vid_pid(NULL, this->vendor_id, this->product_id); + if (!handle) + ret = -1; + else + ret = 0; + } + + device_handle = std::make_shared(handle); + + return ret; +} + + +uint16_t UsbDevice::get_vendor_id() +{ + return this->vendor_id; +} + +uint16_t UsbDevice::get_product_id() +{ + return this->product_id; +} + +int UsbDevice::control_transfer(uint8_t request_type, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, unsigned char *data, uint16_t wLength, unsigned int timeout) +{ + if (!opened()) + return -1000; + + return libusb_control_transfer(this->device_handle->m_handle, request_type, bRequest, wValue, wIndex, data, wLength, timeout); +} + +const std::string &UsbDevice::get_serial_number() +{ + char buffer[256] = {0}; + + if (!opened()) + return serial; + if (devdesc.iSerialNumber == 0) + return serial; + + if (serial.length() > 0) { + return serial; + } + + int res = libusb_get_string_descriptor_ascii(device_handle->m_handle, devdesc.iSerialNumber, (unsigned char *)buffer, 255); + if (res > 0) { + serial = std::string(buffer); + return serial; + } else { + return serial; + } +} + +void LibUsbInit() +{ + libusb_init(NULL); +} + +void LibUsbDeInit() +{ + libusb_exit(NULL); +} + +UsbDeviceHandle::UsbDeviceHandle(libusb_device_handle *handle) +{ + m_handle = handle; +} + +UsbDeviceHandle::~UsbDeviceHandle() +{ + if (m_handle) + libusb_close(m_handle); + m_handle = NULL; +} diff --git a/sustain-kbd-config/libusbwrapper.h b/sustain-kbd-config/libusbwrapper.h new file mode 100644 index 0000000..14095b0 --- /dev/null +++ b/sustain-kbd-config/libusbwrapper.h @@ -0,0 +1,47 @@ +#ifndef LIBUSBWRAPPER_H +#define LIBUSBWRAPPER_H + +#include +#include +#include +#include +#include + +void LibUsbInit(); +void LibUsbDeInit(); + +class UsbDeviceHandle { +public: + UsbDeviceHandle(libusb_device_handle *handle); + ~UsbDeviceHandle(); + libusb_device_handle *m_handle; +}; + +class UsbDevice { +public: + UsbDevice(libusb_device *device); + UsbDevice(const UsbDevice &d) = default; + UsbDevice(UsbDevice &&d); + ~UsbDevice(); + static std::vector find_devices(uint16_t vendor_id, uint16_t product_id); + + bool opened(); + int open(); + uint16_t get_vendor_id(); + uint16_t get_product_id(); + int control_transfer(uint8_t request_type, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, + unsigned char *data, uint16_t wLength, unsigned int timeout); + const std::string &get_serial_number(); + +private: + std::shared_ptr device_handle; + libusb_device *dev; + uint16_t vendor_id; + uint16_t product_id; + std::string serial; + struct libusb_device_descriptor devdesc; + +}; + + +#endif // LIBUSBWRAPPER_H diff --git a/sustain-kbd-config/main.cpp b/sustain-kbd-config/main.cpp new file mode 100644 index 0000000..72fa04c --- /dev/null +++ b/sustain-kbd-config/main.cpp @@ -0,0 +1,23 @@ +#include "mainwindow.h" +#include "libusbwrapper.h" +#include + +#include + +int main(int argc, char *argv[]) +{ + int ret; + + QApplication a(argc, argv); + MainWindow w; + + LibUsbInit(); + + w.show(); + + ret = a.exec(); + + LibUsbDeInit(); + + return ret; +} diff --git a/sustain-kbd-config/mainwindow.cpp b/sustain-kbd-config/mainwindow.cpp new file mode 100644 index 0000000..a3f57b6 --- /dev/null +++ b/sustain-kbd-config/mainwindow.cpp @@ -0,0 +1,228 @@ +#include "mainwindow.h" +#include "./ui_mainwindow.h" +#include "libusbwrapper.h" +#include +#include +#include + +MainWindow::MainWindow(QWidget *parent) + : QMainWindow(parent) + , ui(new Ui::MainWindow) +{ + ui->setupUi(this); + connect(ui->rescanButton, SIGNAL(clicked()), this, SLOT(rescan_clicked())); + connect(this, SIGNAL(close()), this, SLOT(on_close())); + connect(ui->deviceComboBox, SIGNAL(currentTextChanged(QString)), this, SLOT(device_changed(QString))); + connect(ui->clearKeycodesButton, SIGNAL(clicked()), this, SLOT(clear_keyboard_config())); +} + +MainWindow::~MainWindow() +{ + delete ui; +} + +void MainWindow::rescan_device_list() +{ + if (this->m_usb_devices.size()) { + /* Close old devices */ + m_usb_devices.clear(); + } + + auto temp_vector = UsbDevice::find_devices(0xDEAD, 0xBEEF); + this->m_usb_devices = std::vector(temp_vector.begin(), temp_vector.end()); + + ui->deviceComboBox->clear(); + + /* Update combo box with devices */ + for (auto &dev : m_usb_devices) { + dev.open(); + auto sn = dev.get_serial_number(); + ui->deviceComboBox->addItem(QString::fromStdString(sn)); + } + +} + +UsbDevice *MainWindow::get_device_from_sn(const std::string &sn) +{ + for (auto &d : m_usb_devices) { + if (d.get_serial_number() == sn) + return &d; + } + + return NULL; +} + +UsbHidKeyEvent MainWindow::create_key_event_pedal1() +{ + UsbHidKeyEvent event; + + event.left_control = ui->checkBoxLControl_1->isChecked(); + event.left_shift = ui->checkBoxLShift_1->isChecked(); + event.left_alt = ui->checkBoxLAlt_1->isChecked(); + event.left_super = ui->checkBoxLSuper_1->isChecked(); + event.right_control = ui->checkBoxRControl_1->isChecked(); + event.right_shift = ui->checkBoxRShift_1->isChecked(); + event.right_alt = ui->checkBoxRAlt_1->isChecked(); + event.right_super = ui->checkBoxRSuper_1->isChecked(); + + event.keycodes[0] = (uint8_t)ui->keycode1_1->value(); + event.keycodes[1] = (uint8_t)ui->keycode2_1->value(); + event.keycodes[2] = (uint8_t)ui->keycode3_1->value(); + + return event; +} + +UsbHidKeyEvent MainWindow::create_key_event_pedal2() +{ + UsbHidKeyEvent event; + + event.left_control = ui->checkBoxLControl_2->isChecked(); + event.left_shift = ui->checkBoxLShift_2->isChecked(); + event.left_alt = ui->checkBoxLAlt_2->isChecked(); + event.left_super = ui->checkBoxLSuper_2->isChecked(); + event.right_control = ui->checkBoxRControl_2->isChecked(); + event.right_shift = ui->checkBoxRShift_2->isChecked(); + event.right_alt = ui->checkBoxRAlt_2->isChecked(); + event.right_super = ui->checkBoxRSuper_2->isChecked(); + + event.keycodes[0] = (uint8_t)ui->keycode1_2->value(); + event.keycodes[1] = (uint8_t)ui->keycode2_2->value(); + event.keycodes[2] = (uint8_t)ui->keycode3_2->value(); + + return event; +} + +void MainWindow::rescan_clicked() +{ + rescan_device_list(); +} + +void MainWindow::device_changed(QString sn) +{ + auto dev = get_device_from_sn(sn.toStdString()); + if (m_currently_selected_dev.get()) { + m_currently_selected_dev->set_active_indicator(false); + } + m_currently_selected_dev.reset(); + + if (dev == NULL) { + enable_pedal_gui_elements(false); + return; + } + + enable_pedal_gui_elements(true); + + m_currently_selected_dev = std::make_unique(*dev); + + m_currently_selected_dev->set_active_indicator(true); + update_gui_from_keyboard(); +} + +void MainWindow::clear_keyboard_config() +{ + if (!m_currently_selected_dev.get()) { + QMessageBox::warning(this, "Error", "No device selected!"); + return; + } + + UsbHidKeyEvent empty_key; + + if (m_currently_selected_dev->program_keyboard_keycode(0, empty_key)) { + QMessageBox::warning(this, "Error", "Request to device failed!"); + return; + } + + if (m_currently_selected_dev->program_keyboard_keycode(1, empty_key)) { + QMessageBox::warning(this, "Error", "Request to device failed!"); + return; + } + update_gui_from_keyboard(); + QMessageBox::information(this, "Device Reset", "All configuration deleted!"); + +} + +void MainWindow::update_gui_from_keyboard() +{ + UsbHidKeyEvent pedal1, pedal2; + + if (!m_currently_selected_dev->read_keyboard_config(&pedal1, &pedal2)) { + ui->checkBoxLControl_1->setChecked(pedal1.left_control); + ui->checkBoxLShift_1->setChecked(pedal1.left_shift); + ui->checkBoxLAlt_1->setChecked(pedal1.left_alt); + ui->checkBoxLSuper_1->setChecked(pedal1.left_super); + ui->checkBoxRControl_1->setChecked(pedal1.right_control); + ui->checkBoxRShift_1->setChecked(pedal1.right_shift); + ui->checkBoxRAlt_1->setChecked(pedal1.right_alt); + ui->checkBoxRSuper_1->setChecked(pedal1.right_super); + + ui->checkBoxLControl_2->setChecked(pedal2.left_control); + ui->checkBoxLShift_2->setChecked(pedal2.left_shift); + ui->checkBoxLAlt_2->setChecked(pedal2.left_alt); + ui->checkBoxLSuper_2->setChecked(pedal2.left_super); + ui->checkBoxRControl_2->setChecked(pedal2.right_control); + ui->checkBoxRShift_2->setChecked(pedal2.right_shift); + ui->checkBoxRAlt_2->setChecked(pedal2.right_alt); + ui->checkBoxRSuper_2->setChecked(pedal2.right_super); + + ui->keycode1_1->setValue((int)pedal1.keycodes[0]); + ui->keycode2_1->setValue((int)pedal1.keycodes[1]); + ui->keycode3_1->setValue((int)pedal1.keycodes[2]); + + ui->keycode1_2->setValue((int)pedal2.keycodes[0]); + ui->keycode2_2->setValue((int)pedal2.keycodes[1]); + ui->keycode3_2->setValue((int)pedal2.keycodes[2]); + } +} + +void MainWindow::closeEvent(QCloseEvent *event) +{ + if (m_currently_selected_dev) + m_currently_selected_dev->set_active_indicator(false); + m_usb_devices.clear(); + m_currently_selected_dev.reset(); + m_currently_selected_dev = nullptr; +} + +void MainWindow::showEvent(QShowEvent *event) +{ + QMainWindow::showEvent(event); + enable_pedal_gui_elements(false); + rescan_device_list(); +} + + +void MainWindow::on_buttonProgPedal1_clicked() +{ + if (!m_currently_selected_dev.get()) + return; + auto ev = create_key_event_pedal1(); + m_currently_selected_dev->program_keyboard_keycode(0, ev); +} + + +void MainWindow::on_buttonProgPedal2_clicked() +{ + if (!m_currently_selected_dev.get()) + return; + + auto ev = create_key_event_pedal2(); + m_currently_selected_dev->program_keyboard_keycode(1, ev); +} + +void MainWindow::enable_pedal_gui_elements(bool enable) +{ + int count1 = ui->verticalLayoutPedal1->count(); + int count2 = ui->verticalLayoutPedal2->count(); + + for (int i = 0; i < count1; i++) { + ui->verticalLayoutPedal1->itemAt(i)->widget()->setEnabled(enable); + } + + for (int i = 0; i < count2; i++) { + ui->verticalLayoutPedal2->itemAt(i)->widget()->setEnabled(enable); + } + + ui->clearKeycodesButton->setEnabled(enable); + +} + diff --git a/sustain-kbd-config/mainwindow.h b/sustain-kbd-config/mainwindow.h new file mode 100644 index 0000000..464e4c6 --- /dev/null +++ b/sustain-kbd-config/mainwindow.h @@ -0,0 +1,47 @@ +#ifndef MAINWINDOW_H +#define MAINWINDOW_H + +#include +#include "sustainpedalkeyboard.h" +#include +#include +#include +#include + +QT_BEGIN_NAMESPACE +namespace Ui { class MainWindow; } +QT_END_NAMESPACE + +class MainWindow : public QMainWindow +{ + Q_OBJECT + +public: + MainWindow(QWidget *parent = nullptr); + ~MainWindow(); + +private: + Ui::MainWindow *ui; + void rescan_device_list(void); + UsbDevice *get_device_from_sn(const std::string &sn); + std::vector m_usb_devices; + std::unique_ptr m_currently_selected_dev; + UsbHidKeyEvent create_key_event_pedal1(); + UsbHidKeyEvent create_key_event_pedal2(); + +private slots: + void rescan_clicked(); + void device_changed(QString sn); + void clear_keyboard_config(); + void update_gui_from_keyboard(); + void on_buttonProgPedal1_clicked(); + + void on_buttonProgPedal2_clicked(); + void enable_pedal_gui_elements(bool enable); + +protected: + void closeEvent(QCloseEvent *event); + void showEvent(QShowEvent *event); + +}; +#endif // MAINWINDOW_H diff --git a/sustain-kbd-config/mainwindow.ui b/sustain-kbd-config/mainwindow.ui new file mode 100644 index 0000000..3afa84c --- /dev/null +++ b/sustain-kbd-config/mainwindow.ui @@ -0,0 +1,251 @@ + + + MainWindow + + + + 0 + 0 + 800 + 600 + + + + Shimatta Sustain Pedal Keyboard Configuration + + + + + + 10 + 10 + 501 + 492 + + + + + + + + + + + + Rescan Device List + + + + + + + + + + + + + + + + + Program VID:PID + + + + + + + + + Clear Keycodes + + + + + + + + + + + Left Control + + + + + + + Left Shift + + + + + + + Left Alt + + + + + + + Left Super + + + + + + + Right Control + + + + + + + Right Shift + + + + + + + Right Alt + + + + + + + Right Super + + + + + + + 255 + + + + + + + 255 + + + + + + + 255 + + + + + + + Program Pedal 1 + + + + + + + + + + + Left Control + + + + + + + Left Shift + + + + + + + Left Alt + + + + + + + Left Super + + + + + + + Right Control + + + + + + + Right Shift + + + + + + + Right Alt + + + + + + + Right Super + + + + + + + 255 + + + + + + + 255 + + + + + + + 255 + + + + + + + Program Pedal 2 + + + + + + + + + + + + + + diff --git a/sustain-kbd-config/sustainpedalkeyboard.cpp b/sustain-kbd-config/sustainpedalkeyboard.cpp new file mode 100644 index 0000000..f576fed --- /dev/null +++ b/sustain-kbd-config/sustainpedalkeyboard.cpp @@ -0,0 +1,155 @@ +#include "sustainpedalkeyboard.h" +#include + +SustainPedalKeyboard::SustainPedalKeyboard(libusb_device *device) : UsbDevice(device) +{ + m_control_timeout = 500; +} + +SustainPedalKeyboard::SustainPedalKeyboard(const UsbDevice &device) : UsbDevice(device) +{ + m_control_timeout = 500; +} + +SustainPedalKeyboard::~SustainPedalKeyboard() +{ +} + +int SustainPedalKeyboard::get_control_timeout() +{ + return m_control_timeout; +} + +void SustainPedalKeyboard::set_control_timeout(int timeout) +{ + m_control_timeout = timeout; +} + +int SustainPedalKeyboard::set_led(uint8_t led, bool state) +{ + int res = this->control_transfer((1<<6), 0x1, state ? 1 : 0, led, NULL, 0, m_control_timeout); + + return res; +} + +void SustainPedalKeyboard::set_active_indicator(bool state) +{ + (void)set_led(3, state); +} + +int SustainPedalKeyboard::program_keyboard_keycode(uint8_t pedal_idx, UsbHidKeyEvent &key) +{ + uint32_t word; + uint8_t data[4]; + + if (pedal_idx > 1) + return -1001; + + word = key.to_eeprom_word(); + + for (int i = 0; i < 4; i++) { + data[i] = word & 0xFF; + word >>= 8; + } + + int res = write_eeprom(pedal_idx * 4, data, 4); + if (res < 0) + return res; + else + return 0; +} + +int SustainPedalKeyboard::read_keyboard_config(UsbHidKeyEvent *pedal1, UsbHidKeyEvent *pedal2) +{ + unsigned char eeprom_data[8]; + + if (!pedal1 || !pedal2) + return -1000; + + int res = read_eeprom(0, eeprom_data, sizeof(eeprom_data)); + if (res != 8) { + return -1; + } + + pedal1->from_eeprom_data(&eeprom_data[0]); + pedal2->from_eeprom_data(&eeprom_data[4]); + + return 0; +} + + +int SustainPedalKeyboard::write_eeprom(uint16_t offset_addr, unsigned char *data, uint16_t len) +{ + return this->control_transfer((1<<6), 0x2, 0, offset_addr, data, len, m_control_timeout); +} + +int SustainPedalKeyboard::read_eeprom(uint16_t offset_addr, unsigned char *data, uint16_t len) +{ + int ret; + + ret = this->control_transfer(0x80 | (1<<6), 0x2, 0x0, offset_addr, data, len, m_control_timeout); + + return ret; +} + + +UsbHidKeyEvent::UsbHidKeyEvent() +{ + for (int i = 0; i < 3; i++) + keycodes[i] = 0; + left_control = false; + left_alt = false; + left_shift = false; + left_super = false; + right_control = false; + right_super = false; + right_alt = false; + right_shift = false; +} + +uint32_t UsbHidKeyEvent::to_eeprom_word() +{ + uint8_t modifiers = 0; + uint32_t ret; + + + if (left_control) + modifiers |= 1; + if (left_shift) + modifiers |= 2; + if (left_alt) + modifiers |= 4; + if (left_super) + modifiers |= 8; + if (right_control) + modifiers |= 16; + if (right_shift) + modifiers |= 32; + if (right_alt) + modifiers |= 64; + if (right_super) + modifiers |= 128; + + ret = (uint32_t)modifiers; + ret |= (((uint32_t)keycodes[0]) << 8); + ret |= (((uint32_t)keycodes[1]) << 16); + ret |= (((uint32_t)keycodes[2]) << 24); + + return ret; +} + +void UsbHidKeyEvent::from_eeprom_data(uint8_t data[4]) +{ + left_control = !!(data[0] & 1); + left_shift = !!(data[0] & 2); + left_alt = !!(data[0] & 4); + left_super = !!(data[0] & 8); + right_control = !!(data[0] & 16); + right_shift = !!(data[0] & 32); + right_alt = !!(data[0] & 64); + right_super = !!(data[0] & 128); + + for (int i = 0; i < 3; i++) { + keycodes[i] = data[i + 1]; + } +} diff --git a/sustain-kbd-config/sustainpedalkeyboard.h b/sustain-kbd-config/sustainpedalkeyboard.h new file mode 100644 index 0000000..ef2200c --- /dev/null +++ b/sustain-kbd-config/sustainpedalkeyboard.h @@ -0,0 +1,50 @@ +#ifndef SUSTAINPEDALKEYBOARD_H +#define SUSTAINPEDALKEYBOARD_H + +#include "libusbwrapper.h" + +class UsbHidKeyEvent { +public: + UsbHidKeyEvent(); + + bool left_control; + bool left_shift; + bool left_alt; + bool left_super; + bool right_control; + bool right_shift; + bool right_alt; + bool right_super; + + uint8_t keycodes[3]; + + uint32_t to_eeprom_word(); + void from_eeprom_data(uint8_t data[4]); +}; + +class SustainPedalKeyboard : public UsbDevice +{ +public: + SustainPedalKeyboard(libusb_device *device); + SustainPedalKeyboard(const UsbDevice &device); + ~SustainPedalKeyboard(); + + int get_control_timeout(); + void set_control_timeout(int timeout); + + int set_led(uint8_t led, bool state); + void set_active_indicator(bool state); + + int program_keyboard_keycode(uint8_t pedal_idx, UsbHidKeyEvent &key); + + int read_keyboard_config(UsbHidKeyEvent *pedal1, UsbHidKeyEvent *pedal2); + +private: + int write_eeprom(uint16_t offset_addr, unsigned char *data, uint16_t len); + int read_eeprom(uint16_t offset_addr, unsigned char *data, uint16_t len); + + int m_control_timeout; + +}; + +#endif // SUSTAINPEDALKEYBOARD_H