669 lines
15 KiB
C
669 lines
15 KiB
C
#include "usb.h"
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#include <stm32l0xx.h>
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#include <stddef.h>
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#define ENDPOINT_COUNT (8)
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enum endpoint_state {EP_STATE_DISABLED, EP_STATE_NAK, EP_STATE_STALL, EP_STATE_VALID};
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static void (*ep_rx_data_callback)(uint8_t endpoint, const uint8_t *buffer, uint32_t len) = NULL;
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static enum control_state (*ep_rx_setup_received_callback)(uint8_t endpoint, const struct setup_packet *setup_pkg) = NULL;
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static void (*ep_tx_complete_callback)(uint8_t endpoint);
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static void (*usb_sof_callback)(void) = NULL;
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static void (*usb_reset_callback)(void) = NULL;
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static void (*usb_configured_callback)(uint16_t config_idx) = NULL;
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struct usb_endpoint_info {
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uint16_t rx_pma_size;
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uint16_t tx_pma_size;
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enum usb_ep_type type;
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struct setup_packet last_setup;
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enum control_state ctrl_state;
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volatile uint16_t *ep_reg;
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uint32_t tx_count;
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const uint8_t *tx_ptr;
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uint32_t rx_size;
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uint8_t *rx_buffer;
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};
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static const struct usb_descriptor_entry *usb_descriptors = NULL;
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static uint16_t * const pma_base_ptr = (uint16_t *)0x40006000UL;
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struct usb_endpoint_info endpoints[ENDPOINT_COUNT];
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static void setup_usb_clock(void)
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{
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uint32_t reload_val;
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const uint32_t felim = 0x22;
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const uint32_t f_target = 48000000UL;
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const uint32_t f_usb_sof = 1000UL;
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RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
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/* Enable the internal voltage reference. This is needed for HSI48 */
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SYSCFG->CFGR3 |= SYSCFG_CFGR3_EN_VREFINT;
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while (!(SYSCFG->CFGR3 & SYSCFG_CFGR3_VREFINT_RDYF));
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SYSCFG->CFGR3 |= SYSCFG_CFGR3_ENREF_HSI48;
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RCC->CRRCR = RCC_CRRCR_HSI48ON;
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while(!(RCC->CRRCR & RCC_CRRCR_HSI48RDY));
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RCC->CCIPR |= RCC_CCIPR_HSI48SEL;
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/* Configure Clock recovery from USB SOF (1kHz) */
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RCC->APB1ENR |= RCC_APB1ENR_CRSEN;
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reload_val = (f_target / f_usb_sof) - 1;
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CRS->CFGR = (reload_val & 0xFFFF) | (felim << 16) | CRS_CFGR_SYNCSRC_1;
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CRS->CR = CRS_CR_CEN | CRS_CR_AUTOTRIMEN;
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}
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void usb_init(const struct usb_callbacks *callbacks)
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{
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setup_usb_clock();
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/* Activate register clock for USB */
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RCC->APB1ENR |= RCC_APB1ENR_USBEN;
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/* Power up the USB interface but hold in reset */
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USB->CNTR = USB_CNTR_FRES;
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endpoints[0].ep_reg = &USB->EP0R;
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endpoints[1].ep_reg = &USB->EP1R;
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endpoints[2].ep_reg = &USB->EP2R;
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endpoints[3].ep_reg = &USB->EP3R;
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endpoints[4].ep_reg = &USB->EP4R;
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endpoints[5].ep_reg = &USB->EP5R;
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endpoints[6].ep_reg = &USB->EP6R;
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endpoints[7].ep_reg = &USB->EP7R;
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/* Setup the callbacks */
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ep_rx_data_callback = callbacks->ep_rx_data_callback;
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ep_tx_complete_callback = callbacks->ep_tx_complete_callback;
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ep_rx_setup_received_callback = callbacks->ep_rx_setup_received_callback;
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usb_configured_callback = callbacks->usb_configured_callback;
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usb_reset_callback = callbacks->usb_reset_callback;
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usb_sof_callback = callbacks->usb_sof_callback;
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}
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static void write_b_table(uint32_t addr, uint16_t value)
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{
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volatile uint16_t *ptr = pma_base_ptr;
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ptr += (addr >> 1);
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*ptr = value;
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}
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static uint16_t read_b_table(uint32_t addr)
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{
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volatile uint16_t *ptr = pma_base_ptr;
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ptr += (addr >> 1);
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return *ptr;
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}
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static uint16_t read_rx_pma(uint8_t ep, uint8_t *buff, uint32_t size)
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{
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uint16_t rx_btable_entry;
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uint16_t pma_addr;
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uint8_t *app_addr;
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uint16_t count;
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uint16_t i;
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rx_btable_entry = read_b_table(ep * 8 + 6);
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count = rx_btable_entry & 0x3FF;
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pma_addr = read_b_table(ep * 8 + 4);
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app_addr = (uint8_t *)pma_base_ptr;
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app_addr += (pma_addr >> 0);
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/* Byte addresed writes seem to work just fine */
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for (i = 0; i < count && i < size; i++) {
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buff[i] = app_addr[i];
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}
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return count;
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}
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static void write_tx_pma(uint8_t ep, const uint8_t *src, uint32_t len)
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{
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uint16_t tx_addr;
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uint16_t *pma = pma_base_ptr;
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uint32_t i;
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uint32_t halfword_cnt;
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bool padding;
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write_b_table(ep * 8 + 2, len);
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if (!len)
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return;
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tx_addr = read_b_table(ep * 8);
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padding = len % 2 ? true : false;
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halfword_cnt = len >> 1;
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pma += tx_addr >> 1;
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for (i = 0; i < halfword_cnt; i++) {
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pma[i] = (uint16_t)src[2 * i] | (((uint16_t)src[2 * i + 1]) << 8);
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}
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if (padding) {
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pma[i] = (uint16_t)src[2 * i];
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}
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}
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static const struct usb_descriptor_entry *find_descriptor_from_setup_request(uint16_t w_index, uint16_t w_value)
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{
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int i;
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const struct usb_descriptor_entry *entry = NULL;
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for (i = 0; usb_descriptors[i].descriptor != NULL; i++) {
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if (usb_descriptors[i].w_index == w_index && usb_descriptors[i].w_value == w_value) {
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entry = &usb_descriptors[i];
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break;
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}
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}
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return entry;
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}
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void usb_endpoint_config(enum usb_ep_type type, uint8_t epnum, bool rx, bool tx)
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{
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uint16_t epreg = 0;
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struct usb_endpoint_info *ep_info;
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if (epnum >= ENDPOINT_COUNT)
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return;
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ep_info = &endpoints[epnum];
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write_b_table(epnum * 8 + 0, 64 + epnum * 136);
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write_b_table(epnum * 8 + 2, 0);
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write_b_table(epnum * 8 + 4, 64 + epnum * 136 + 72);
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write_b_table(epnum * 8 + 6, (1 << 10) | (1<<15));
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epreg = *ep_info->ep_reg;
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epreg &= ~(1<<15);
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switch (type) {
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case EP_CONTROL:
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epreg |= (1<<9);
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ep_info->type = EP_CONTROL;
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ep_info->ctrl_state = CONTROL_SETUP;
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ep_info->tx_pma_size = 64;
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ep_info->rx_pma_size = 64;
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case EP_BULK:
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ep_info->type = EP_BULK;
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ep_info->ctrl_state = CONTROL_SETUP;
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ep_info->tx_pma_size = 64;
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ep_info->rx_pma_size = 64;
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break;
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case EP_INTERRUPT:
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epreg |= (1<<10) | (1<<9);
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ep_info->type = EP_INTERRUPT;
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ep_info->ctrl_state = CONTROL_SETUP;
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ep_info->tx_pma_size = 64;
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ep_info->rx_pma_size = 64;
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break;
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case EP_ISOCHRON:
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epreg |= (1<<10);
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ep_info->type = EP_ISOCHRON;
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ep_info->ctrl_state = CONTROL_SETUP;
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ep_info->tx_pma_size = 64;
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ep_info->rx_pma_size = 64;
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break;
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default:
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return;
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break;
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}
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if (tx) {
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epreg |= (1<<5);
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}
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if (rx) {
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epreg |= (1<<13);
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}
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epreg |= epnum;
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*ep_info->ep_reg = epreg;
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}
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static void usb_endpoint_reset_int_flags(uint8_t endpoint, bool rx, bool tx)
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{
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uint16_t ep_reg;
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if (endpoint >= ENDPOINT_COUNT)
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return;
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ep_reg = *endpoints[endpoint].ep_reg;
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ep_reg &= ~((1<<14) | (1<<6) | (1<<5) | (1<<13) | (1<<12) | (1<<4));
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/* Dont clear flag */
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if (rx) {
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ep_reg &= ~(1<<15);
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} else {
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ep_reg |= (1<<15);
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}
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if (tx) {
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ep_reg &= ~(1<<7);
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} else {
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ep_reg |= (1<<7);
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}
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*endpoints[endpoint].ep_reg = ep_reg;
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}
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static void usb_endpoint_set_rx_state(uint8_t endpoint, enum endpoint_state state)
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{
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uint16_t ep_reg;
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uint16_t ep_rx_target = 0;
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if (endpoint >= ENDPOINT_COUNT)
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return;
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ep_reg = *endpoints[endpoint].ep_reg;
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/* Mask out all toggle flags that we don't want to change */
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ep_reg &= ~((1<<14) | (1<<6) | (1<<5) | (1<<4));
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/* Dont clear flag */
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ep_reg |= (1<<15) | (1<<7);
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/* Prepare the target value */
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switch (state) {
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case EP_STATE_DISABLED:
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ep_rx_target = 0;
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break;
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case EP_STATE_NAK:
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ep_rx_target = (1<<13);
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break;
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case EP_STATE_VALID:
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ep_rx_target = (1<<13) | (1<<12);
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break;
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case EP_STATE_STALL:
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ep_rx_target = (1<<12);
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default:
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return;
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}
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/* Generate toggle mask for the TX bits */
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ep_reg ^= ep_rx_target;
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*endpoints[endpoint].ep_reg = ep_reg;
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}
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static void usb_endpoint_set_tx_state(uint8_t endpoint, enum endpoint_state state)
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{
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uint16_t ep_reg;
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uint16_t ep_tx_target = 0;
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if (endpoint >= ENDPOINT_COUNT)
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return;
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ep_reg = *endpoints[endpoint].ep_reg;
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/* Mask out all toggle flags that we don't want to change */
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ep_reg &= ~((1<<14) | (1<<13) | (1<<12) | (1<<6));
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/* Dont clear flag */
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ep_reg |= (1<<15) | (1<<7);
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/* Prepare the target value */
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switch (state) {
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case EP_STATE_DISABLED:
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ep_tx_target = 0;
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break;
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case EP_STATE_NAK:
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ep_tx_target = (1<<5);
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break;
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case EP_STATE_VALID:
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ep_tx_target = (1<<5) | (1<<4);
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break;
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case EP_STATE_STALL:
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ep_tx_target = (1<<4);
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default:
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return;
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}
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/* Generate toggle mask for the TX bits */
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ep_reg ^= ep_tx_target;
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*endpoints[endpoint].ep_reg = ep_reg;
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}
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void usb_endpoint_stall(uint8_t endpoint, bool tx_dir, bool rx_dir)
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{
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if (tx_dir)
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usb_endpoint_set_tx_state(endpoint, EP_STATE_STALL);
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}
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int usb_endpoint_send(uint8_t endpoint, const uint8_t *data, uint32_t len)
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{
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struct usb_endpoint_info *epinfo;
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uint32_t tx_cnt;
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if (endpoint >= ENDPOINT_COUNT)
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return -1001;
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epinfo = &endpoints[endpoint];
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if (epinfo->tx_pma_size == 0)
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return -1;
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tx_cnt = len < epinfo->tx_pma_size ? len : epinfo->tx_pma_size;
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/* Copy data to pma and save the data pointer to the next word to be transmitted */
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if (tx_cnt < len) {
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epinfo->tx_ptr = &data[tx_cnt];
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epinfo->tx_count = len - tx_cnt;
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} else {
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epinfo->tx_count = 0;
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epinfo->tx_ptr = NULL;
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}
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write_tx_pma(endpoint, data, tx_cnt);
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/* Prepare endpoint for TX */
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usb_endpoint_set_tx_state(endpoint, EP_STATE_VALID);
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return 0;
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}
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int usb_endpoint_prepare_receive(uint8_t endpoint, uint8_t *buffer, uint32_t bufflen)
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{
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struct usb_endpoint_info *info;
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if (endpoint >= ENDPOINT_COUNT)
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return -1001;
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info = &endpoints[endpoint];
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if (info->rx_buffer || info->rx_size) {
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return -1;
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}
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__disable_irq();
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info->rx_buffer = buffer;
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info->rx_size = bufflen;
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usb_endpoint_set_rx_state(endpoint, EP_STATE_VALID);
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__enable_irq();
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return 0;
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}
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void usb_endpoint_send_status_stage(uint8_t endpoint)
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{
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struct usb_endpoint_info *info;
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if (endpoint >= ENDPOINT_COUNT)
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return;
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info = &endpoints[endpoint];
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info->ctrl_state = CONTROL_STATUS_TX;
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usb_endpoint_send(endpoint, NULL, 0);
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}
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void usb_enable(const struct usb_descriptor_entry *descriptors)
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{
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if (!descriptors)
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return;
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usb_descriptors = descriptors;
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/* Enable device with address 0 */
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USB->DADDR = USB_DADDR_EF;
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/* Clear all interrupts */
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USB->ISTR = 0;
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/* Set buffer description table to beginning of PMA */
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USB->BTABLE = 0x0U;
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/* Actiovate USB module (clear reset bit) and setup the interrupt masks */
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USB->CNTR = USB_CNTR_CTRM | USB_CNTR_ERRM | USB_CNTR_RESETM | USB_CNTR_SOFM;
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/* Enable internal D+ pullup to tell the host we're here */
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USB->BCDR = USB_BCDR_DPPU;
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NVIC_EnableIRQ(USB_IRQn);
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}
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static void usb_handle_reset(void)
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{
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int i;
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/* Reset USB address */
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USB->DADDR = USB_DADDR_EF;
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for (i = 0; i < ENDPOINT_COUNT; i++) {
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endpoints[i].rx_size = 0;
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endpoints[i].rx_buffer = NULL;
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endpoints[i].tx_count = 0;
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endpoints[i].tx_ptr = NULL;
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}
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usb_endpoint_config(EP_CONTROL, 0, true, true);
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usb_endpoint_set_rx_state(0, EP_STATE_VALID);
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}
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void usb_ep0_send_status(void)
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{
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struct usb_endpoint_info *ep_info;
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ep_info = &endpoints[0];
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ep_info->ctrl_state = CONTROL_STATUS_TX;
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usb_endpoint_send(0, NULL, 0);
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}
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void usb_ep0_handle_setup(void)
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{
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uint16_t cnt;
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enum control_state next_state;
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const struct usb_descriptor_entry *descriptor;
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struct usb_endpoint_info *ep_info;
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struct setup_packet *setup;
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ep_info = &endpoints[0];
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ep_info->ctrl_state = CONTROL_SETUP;
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setup = &ep_info->last_setup;
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cnt = read_rx_pma(0, (uint8_t *)setup, 8);
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if (cnt != 8) {
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usb_endpoint_stall(0, true, true);
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return;
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}
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if ((setup->bm_req_type == 0x80 || setup->bm_req_type == 0x81 || setup->bm_req_type == 0x82) && setup->b_request == 6) {
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/* Get descriptor request */
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descriptor = find_descriptor_from_setup_request(setup->w_index, setup->w_value);
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if (!descriptor) {
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usb_endpoint_stall(0, true, true);
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}
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cnt = setup->w_length < descriptor->size ? setup->w_length : descriptor->size;
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usb_endpoint_send(0, descriptor->descriptor, cnt);
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ep_info->ctrl_state = CONTROL_DATA_TX;
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} else if (setup->bm_req_type == 0x00 && setup->b_request == 5) {
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/* Set address command
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* Send out status stage and set address after status has finished
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*/
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usb_ep0_send_status();
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} else if (setup->bm_req_type == 0x00 && setup->b_request == 9) {
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/* Set configuration */
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if (usb_configured_callback)
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usb_configured_callback(setup->w_value);
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usb_ep0_send_status();
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} else {
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next_state = CONTROL_NOT_HANDLED;
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/* Check if the callback for setup requests is set and try to handle it this way */
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if (ep_rx_setup_received_callback)
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next_state = ep_rx_setup_received_callback(0, setup);
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/* We could not handle the setup request if handle state != 0 */
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if (next_state == CONTROL_NOT_HANDLED) {
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usb_endpoint_stall(0, true, true);
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} else {
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/* Control handled */
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switch (next_state) {
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case CONTROL_STATUS_TX:
|
|
usb_ep0_send_status();
|
|
break;
|
|
case CONTROL_DATA_TX:
|
|
break;
|
|
case CONTROL_DATA_RX:
|
|
break;
|
|
default:
|
|
usb_endpoint_stall(0, true, true);
|
|
break;
|
|
}
|
|
}
|
|
|
|
ep_info->ctrl_state = (next_state != CONTROL_NOT_HANDLED ? next_state : CONTROL_SETUP);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
void usb_ep0_handle_tx(void)
|
|
{
|
|
struct usb_endpoint_info *info = &endpoints[0];
|
|
|
|
if (info->tx_count) {
|
|
/* Do the rest */
|
|
usb_endpoint_send(0, info->tx_ptr, info->tx_count);
|
|
} else {
|
|
if (info->ctrl_state == CONTROL_DATA_TX) {
|
|
info->ctrl_state = CONTROL_STATUS_RX;
|
|
/* Listen for new setup packets */
|
|
usb_endpoint_set_rx_state(0, EP_STATE_VALID);
|
|
} else if (info->ctrl_state == CONTROL_STATUS_TX) {
|
|
/* we've sent a status back. Check if we should set our address now */
|
|
if (info->last_setup.bm_req_type == 0x00 && info->last_setup.b_request == 0x5) {
|
|
USB->DADDR = USB_DADDR_EF | info->last_setup.w_value;
|
|
}
|
|
|
|
info->ctrl_state = CONTROL_SETUP;
|
|
/* Listen for new setup packets */
|
|
usb_endpoint_set_rx_state(0, EP_STATE_VALID);
|
|
} else {
|
|
if (ep_tx_complete_callback)
|
|
ep_tx_complete_callback(0);
|
|
}
|
|
}
|
|
}
|
|
|
|
void usb_handle_rx_packet(uint8_t ep)
|
|
{
|
|
uint16_t epreg;
|
|
struct usb_endpoint_info *info;
|
|
uint16_t pkg_len;
|
|
uint8_t *buffer;
|
|
|
|
info = &endpoints[ep];
|
|
epreg = *info->ep_reg;
|
|
|
|
usb_endpoint_reset_int_flags(ep, true, false);
|
|
|
|
|
|
if (epreg & (1<<11) && ep == 0) {
|
|
info->ctrl_state = CONTROL_SETUP;
|
|
usb_ep0_handle_setup();
|
|
} else if (ep == 0 && info->ctrl_state == CONTROL_STATUS_RX) {
|
|
info->ctrl_state = CONTROL_SETUP;
|
|
|
|
/* Check the received status frame */
|
|
pkg_len = read_rx_pma(0, NULL, 0);
|
|
if (pkg_len != 0) {
|
|
usb_endpoint_stall(0, true, true);
|
|
} else {
|
|
/* Ready to receive next datum */
|
|
usb_endpoint_set_rx_state(0, EP_STATE_VALID);
|
|
}
|
|
} else {
|
|
if (epreg & (1<<11)) {
|
|
(void)read_rx_pma(ep, (uint8_t *)&info->last_setup, 8);
|
|
if (ep_rx_setup_received_callback)
|
|
ep_rx_setup_received_callback(ep, &info->last_setup);
|
|
}
|
|
|
|
if (info->rx_buffer && info->rx_size) {
|
|
pkg_len = read_rx_pma(ep, info->rx_buffer, info->rx_size);
|
|
buffer = info->rx_buffer;
|
|
info->rx_size = 0;
|
|
info->rx_buffer = 0;
|
|
ep_rx_data_callback(ep, buffer, pkg_len);
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
void usb_handle_tx_packet_sent(uint8_t ep)
|
|
{
|
|
struct usb_endpoint_info *info = &endpoints[ep];
|
|
|
|
usb_endpoint_reset_int_flags(ep, false, true);
|
|
|
|
if (ep == 0) {
|
|
usb_ep0_handle_tx();
|
|
} else {
|
|
if (info->tx_count && info->tx_ptr) {
|
|
usb_endpoint_send(ep, info->tx_ptr, info->tx_count);
|
|
} else {
|
|
if (ep_tx_complete_callback)
|
|
ep_tx_complete_callback(ep);
|
|
}
|
|
}
|
|
}
|
|
|
|
void USB_IRQHandler(void)
|
|
{
|
|
uint16_t istr = USB->ISTR;
|
|
uint8_t endpoint;
|
|
bool dir_tx;
|
|
|
|
if (istr & USB_ISTR_RESET) {
|
|
USB->ISTR = (uint16_t)(~USB_ISTR_RESET);
|
|
usb_handle_reset();
|
|
if (usb_reset_callback)
|
|
usb_reset_callback();
|
|
}
|
|
|
|
if (istr & USB_ISTR_CTR) {
|
|
/* correct transfer interrupt */
|
|
endpoint = istr & USB_ISTR_EP_ID;
|
|
dir_tx = (istr & USB_ISTR_DIR) ? false : true;
|
|
|
|
if (dir_tx) {
|
|
usb_handle_tx_packet_sent(endpoint);
|
|
} else {
|
|
usb_handle_rx_packet(endpoint);
|
|
}
|
|
|
|
/* Clear interrupt */
|
|
USB->ISTR = (uint16_t)(~USB_ISTR_CTR);
|
|
|
|
}
|
|
|
|
if (istr & USB_ISTR_SOF) {
|
|
USB->ISTR = (uint16_t)(~USB_ISTR_SOF);
|
|
if (usb_sof_callback)
|
|
usb_sof_callback();
|
|
}
|
|
|
|
if (istr & USB_ISTR_ERR) {
|
|
USB->ISTR = (uint16_t)(~USB_ISTR_ERR);
|
|
}
|
|
|
|
__DSB();
|
|
}
|