First layout
This commit is contained in:
parent
525b55dbf9
commit
a11571971a
5
fp-lib-table
Normal file
5
fp-lib-table
Normal file
@ -0,0 +1,5 @@
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(fp_lib_table
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(lib (name proz_fiducials)(type KiCad)(uri ${KIPRJMOD}/KiCadLibs/footprints/proz_fiducials.pretty)(options "")(descr ""))
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(lib (name proz_led)(type KiCad)(uri ${KIPRJMOD}/KiCadLibs/footprints/proz_led.pretty)(options "")(descr ""))
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(lib (name proz_unknown)(type KiCad)(uri ${KIPRJMOD}/KiCadLibs/footprints/proz_unknown.pretty)(options "")(descr ""))
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)
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@ -328,6 +328,27 @@ X GND 1 0 0 0 D 50 50 1 1 W N
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ENDDRAW
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ENDDEF
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#
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# proz_util_LightLine_x2
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#
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DEF proz_util_LightLine_x2 L 0 40 Y Y 1 F N
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F0 "L" 150 -50 50 H V C CNN
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F1 "proz_util_LightLine_x2" 150 300 50 H V C CNN
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F2 "" 190 270 50 H I C CNN
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F3 "" 190 270 50 H I C CNN
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DRAW
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A 209 93 57 850 379 1 1 4 N 214 150 254 128
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A 209 193 57 850 379 1 1 4 N 214 250 254 228
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P 2 1 1 4 150 24 150 56 N
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P 3 1 1 4 40 100 40 150 214 150 N
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P 3 1 1 4 40 200 40 250 214 250 N
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P 3 1 1 4 130 100 104 124 130 150 N
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P 3 1 1 4 130 200 104 224 130 250 N
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P 8 1 1 4 254 128 278 100 278 88 170 88 170 56 130 56 130 100 40 100 N
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P 8 1 1 4 254 228 278 200 278 188 170 188 170 156 130 156 130 200 40 200 N
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P 18 1 1 4 134 56 130 52 134 48 130 44 134 40 130 36 134 32 130 28 134 24 164 24 168 28 164 32 168 36 164 40 168 44 164 48 168 52 164 56 N
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ENDDRAW
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ENDDEF
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#
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# shimatta_connectors_10PIN_JTAG_SWD
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#
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DEF shimatta_connectors_10PIN_JTAG_SWD J 0 40 Y Y 1 F N
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File diff suppressed because it is too large
Load Diff
@ -1,29 +1,10 @@
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update=22/05/2015 07:44:53
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update=Sun 02 May 2021 01:42:11 AM CEST
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[pcbnew]
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version=1
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LastNetListRead=
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=1.500000000000
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PadSizeV=1.500000000000
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PcbTextSizeV=1.500000000000
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PcbTextSizeH=1.500000000000
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PcbTextThickness=0.300000000000
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ModuleTextSizeV=1.000000000000
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ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
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SolderMaskClearance=0.000000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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@ -31,3 +12,229 @@ NetIExt=net
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version=1
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LibDir=
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[eeschema/libraries]
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=
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CopperLayerCount=2
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BoardThickness=1.6
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AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.2
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MinViaDiameter=0.4
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MinViaDrill=0.3
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MinMicroViaDiameter=0.2
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MinMicroViaDrill=0.09999999999999999
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MinHoleToHole=0.25
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TrackWidth1=0.25
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TrackWidth2=0.3
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TrackWidth3=0.6
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ViaDiameter1=0.6
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ViaDrill1=0.3
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dPairWidth1=0.25
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dPairGap1=0.25
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dPairViaGap1=0.25
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SilkLineWidth=0.12
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SilkTextSizeV=1
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SilkTextSizeH=1
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SilkTextSizeThickness=0.15
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SilkTextItalic=0
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SilkTextUpright=1
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CopperLineWidth=0.2
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CopperTextSizeV=1.5
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CopperTextSizeH=1.5
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CopperTextThickness=0.3
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CopperTextItalic=0
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CopperTextUpright=1
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EdgeCutLineWidth=0.05
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CourtyardLineWidth=0.05
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OthersLineWidth=0.15
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OthersTextSizeV=1
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OthersTextSizeH=1
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OthersTextSizeThickness=0.15
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OthersTextItalic=0
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OthersTextUpright=1
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SolderMaskClearance=0
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SolderMaskMinWidth=0
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SolderPasteClearance=0
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SolderPasteRatio=-0
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[pcbnew/Layer.F.Cu]
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Name=F.Cu
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Type=0
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Enabled=1
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[pcbnew/Layer.In1.Cu]
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Name=In1.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In2.Cu]
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Name=In2.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In3.Cu]
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Name=In3.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In4.Cu]
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Name=In4.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In5.Cu]
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Name=In5.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In6.Cu]
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Name=In6.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In7.Cu]
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Name=In7.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In8.Cu]
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Name=In8.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In9.Cu]
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Name=In9.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In10.Cu]
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Name=In10.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In11.Cu]
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Name=In11.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In12.Cu]
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Name=In12.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In13.Cu]
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Name=In13.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In14.Cu]
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Name=In14.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In15.Cu]
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Name=In15.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In16.Cu]
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Name=In16.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In17.Cu]
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Name=In17.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In18.Cu]
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Name=In18.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In19.Cu]
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Name=In19.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In20.Cu]
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Name=In20.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In21.Cu]
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Name=In21.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In22.Cu]
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Name=In22.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In23.Cu]
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Name=In23.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In24.Cu]
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Name=In24.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In25.Cu]
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Name=In25.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In26.Cu]
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Name=In26.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In27.Cu]
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Name=In27.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In28.Cu]
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Name=In28.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In29.Cu]
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Name=In29.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In30.Cu]
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Name=In30.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.B.Cu]
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Name=B.Cu
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Type=0
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Enabled=1
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[pcbnew/Layer.B.Adhes]
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Enabled=1
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[pcbnew/Layer.F.Adhes]
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Enabled=1
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[pcbnew/Layer.B.Paste]
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Enabled=1
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[pcbnew/Layer.F.Paste]
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Enabled=1
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[pcbnew/Layer.B.SilkS]
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Enabled=1
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[pcbnew/Layer.F.SilkS]
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Enabled=1
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[pcbnew/Layer.B.Mask]
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Enabled=1
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[pcbnew/Layer.F.Mask]
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Enabled=1
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[pcbnew/Layer.Dwgs.User]
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Enabled=1
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[pcbnew/Layer.Cmts.User]
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Enabled=1
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[pcbnew/Layer.Eco1.User]
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Enabled=1
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[pcbnew/Layer.Eco2.User]
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Enabled=1
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[pcbnew/Layer.Edge.Cuts]
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Enabled=1
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[pcbnew/Layer.Margin]
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Enabled=1
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[pcbnew/Layer.B.CrtYd]
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Enabled=1
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[pcbnew/Layer.F.CrtYd]
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Enabled=1
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[pcbnew/Layer.B.Fab]
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Enabled=1
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[pcbnew/Layer.F.Fab]
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Enabled=1
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[pcbnew/Layer.Rescue]
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Enabled=0
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[pcbnew/Netclasses]
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[pcbnew/Netclasses/Default]
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Name=Default
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Clearance=0.2
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TrackWidth=0.25
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ViaDiameter=0.6
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ViaDrill=0.3
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uViaDiameter=0.3
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uViaDrill=0.1
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dPairWidth=0.25
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dPairGap=0.25
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dPairViaGap=0.25
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@ -487,7 +487,7 @@ L Connector:AudioJack2 J3
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U 1 1 60941036
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P 1100 4950
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F 0 "J3" H 920 4933 50 0000 R CNN
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F 1 "PEDAL1" H 920 5024 50 0000 R CNN
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F 1 "PEDAL2" H 920 5024 50 0000 R CNN
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F 2 "Connector_Audio:Jack_6.35mm_Neutrik_NMJ4HFD2_Horizontal" H 1100 4950 50 0001 C CNN
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F 3 "~" H 1100 4950 50 0001 C CNN
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1 1100 4950
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@ -719,14 +719,14 @@ F 3 "" H 5400 4100 50 0001 C CNN
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1 5400 4100
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1 0 0 -1
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$EndComp
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Text Label 4350 2850 0 50 ~ 0
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Text Label 4350 3450 0 50 ~ 0
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PEDAL1
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Text Label 4350 2950 0 50 ~ 0
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Text Label 4350 3550 0 50 ~ 0
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PEDAL2
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Wire Wire Line
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4350 2950 4800 2950
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4350 3550 4800 3550
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Wire Wire Line
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4800 2850 4350 2850
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4800 3450 4350 3450
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$Comp
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L Device:R R2
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U 1 1 609A9974
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@ -1010,4 +1010,30 @@ Wire Wire Line
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9650 5750 9650 5850
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Wire Wire Line
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8800 5750 8800 5850
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$Comp
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L proz_util:LightLine_x2 L1
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U 1 1 6091566B
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P 6950 4050
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F 0 "L1" H 7255 4233 50 0000 L CNN
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F 1 "LightLine_x2" H 7255 4142 50 0000 L CNN
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F 2 "proz_unknown:1271.1002" H 7140 4320 50 0001 C CNN
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F 3 "" H 7140 4320 50 0001 C CNN
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1 6950 4050
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1 0 0 -1
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$EndComp
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$Comp
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L proz_util:LightLine_x2 L2
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U 1 1 60917A37
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P 7700 4050
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F 0 "L2" H 8005 4233 50 0000 L CNN
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F 1 "LightLine_x2" H 8005 4142 50 0000 L CNN
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F 2 "proz_unknown:1271.1002" H 7890 4320 50 0001 C CNN
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F 3 "" H 7890 4320 50 0001 C CNN
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1 7700 4050
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1 0 0 -1
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$EndComp
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Text Label 1300 1750 0 50 ~ 0
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D+
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Text Label 1300 1850 0 50 ~ 0
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D-
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$EndSCHEMATC
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3
sym-lib-table
Normal file
3
sym-lib-table
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(sym_lib_table
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(lib (name proz_util)(type Legacy)(uri ${KIPRJMOD}/KiCadLibs/schematic/proz_util.lib)(options "")(descr ""))
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)
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