First layout

This commit is contained in:
Mario Hüttel 2021-05-03 22:38:26 +02:00
parent 525b55dbf9
commit a11571971a
6 changed files with 1929 additions and 260 deletions

5
fp-lib-table Normal file
View File

@ -0,0 +1,5 @@
(fp_lib_table
(lib (name proz_fiducials)(type KiCad)(uri ${KIPRJMOD}/KiCadLibs/footprints/proz_fiducials.pretty)(options "")(descr ""))
(lib (name proz_led)(type KiCad)(uri ${KIPRJMOD}/KiCadLibs/footprints/proz_led.pretty)(options "")(descr ""))
(lib (name proz_unknown)(type KiCad)(uri ${KIPRJMOD}/KiCadLibs/footprints/proz_unknown.pretty)(options "")(descr ""))
)

View File

@ -328,6 +328,27 @@ X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# proz_util_LightLine_x2
#
DEF proz_util_LightLine_x2 L 0 40 Y Y 1 F N
F0 "L" 150 -50 50 H V C CNN
F1 "proz_util_LightLine_x2" 150 300 50 H V C CNN
F2 "" 190 270 50 H I C CNN
F3 "" 190 270 50 H I C CNN
DRAW
A 209 93 57 850 379 1 1 4 N 214 150 254 128
A 209 193 57 850 379 1 1 4 N 214 250 254 228
P 2 1 1 4 150 24 150 56 N
P 3 1 1 4 40 100 40 150 214 150 N
P 3 1 1 4 40 200 40 250 214 250 N
P 3 1 1 4 130 100 104 124 130 150 N
P 3 1 1 4 130 200 104 224 130 250 N
P 8 1 1 4 254 128 278 100 278 88 170 88 170 56 130 56 130 100 40 100 N
P 8 1 1 4 254 228 278 200 278 188 170 188 170 156 130 156 130 200 40 200 N
P 18 1 1 4 134 56 130 52 134 48 130 44 134 40 130 36 134 32 130 28 134 24 164 24 168 28 164 32 168 36 164 40 168 44 164 48 168 52 164 56 N
ENDDRAW
ENDDEF
#
# shimatta_connectors_10PIN_JTAG_SWD
#
DEF shimatta_connectors_10PIN_JTAG_SWD J 0 40 Y Y 1 F N

File diff suppressed because it is too large Load Diff

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@ -1,29 +1,10 @@
update=22/05/2015 07:44:53
update=Sun 02 May 2021 01:42:11 AM CEST
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
@ -31,3 +12,229 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.3
TrackWidth3=0.6
ViaDiameter1=0.6
ViaDrill1=0.3
dPairWidth1=0.25
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.25
dPairGap=0.25
dPairViaGap=0.25

View File

@ -487,7 +487,7 @@ L Connector:AudioJack2 J3
U 1 1 60941036
P 1100 4950
F 0 "J3" H 920 4933 50 0000 R CNN
F 1 "PEDAL1" H 920 5024 50 0000 R CNN
F 1 "PEDAL2" H 920 5024 50 0000 R CNN
F 2 "Connector_Audio:Jack_6.35mm_Neutrik_NMJ4HFD2_Horizontal" H 1100 4950 50 0001 C CNN
F 3 "~" H 1100 4950 50 0001 C CNN
1 1100 4950
@ -719,14 +719,14 @@ F 3 "" H 5400 4100 50 0001 C CNN
1 5400 4100
1 0 0 -1
$EndComp
Text Label 4350 2850 0 50 ~ 0
Text Label 4350 3450 0 50 ~ 0
PEDAL1
Text Label 4350 2950 0 50 ~ 0
Text Label 4350 3550 0 50 ~ 0
PEDAL2
Wire Wire Line
4350 2950 4800 2950
4350 3550 4800 3550
Wire Wire Line
4800 2850 4350 2850
4800 3450 4350 3450
$Comp
L Device:R R2
U 1 1 609A9974
@ -1010,4 +1010,30 @@ Wire Wire Line
9650 5750 9650 5850
Wire Wire Line
8800 5750 8800 5850
$Comp
L proz_util:LightLine_x2 L1
U 1 1 6091566B
P 6950 4050
F 0 "L1" H 7255 4233 50 0000 L CNN
F 1 "LightLine_x2" H 7255 4142 50 0000 L CNN
F 2 "proz_unknown:1271.1002" H 7140 4320 50 0001 C CNN
F 3 "" H 7140 4320 50 0001 C CNN
1 6950 4050
1 0 0 -1
$EndComp
$Comp
L proz_util:LightLine_x2 L2
U 1 1 60917A37
P 7700 4050
F 0 "L2" H 8005 4233 50 0000 L CNN
F 1 "LightLine_x2" H 8005 4142 50 0000 L CNN
F 2 "proz_unknown:1271.1002" H 7890 4320 50 0001 C CNN
F 3 "" H 7890 4320 50 0001 C CNN
1 7700 4050
1 0 0 -1
$EndComp
Text Label 1300 1750 0 50 ~ 0
D+
Text Label 1300 1850 0 50 ~ 0
D-
$EndSCHEMATC

3
sym-lib-table Normal file
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@ -0,0 +1,3 @@
(sym_lib_table
(lib (name proz_util)(type Legacy)(uri ${KIPRJMOD}/KiCadLibs/schematic/proz_util.lib)(options "")(descr ""))
)