59 lines
2.2 KiB
VHDL
59 lines
2.2 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : 64x08 byte single port memory
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-- Project : Shimatta VHDL FLAC Decoder
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-------------------------------------------------------------------------------
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-- File : flacdec_64x08_memory.vhd
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-- Author : Mario Huettel <mario.huettel@linux.com>
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-- Company : Shimatta
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-- Created : 2023-10-06
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-- Last update: 2023-10-06
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: This is a 64 byte single ported RAM implementation. This file
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-- should be able to infer a BRAM on FPGA targets.
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-- Swap this implementation on an ASIC flow in order to instantiate a fitting
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-- memory instance.
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-- Two instances of this memory are used in the input FIFO of the Flac decoder
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-------------------------------------------------------------------------------
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-- Copyright (c) 2023
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity flacdec_64x08_memory is
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port (
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clk : in std_logic; -- Clock
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address : in std_logic_vector(5 downto 0); -- RAM data address
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write_enable : in std_logic; -- Write enable
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read_enable : in std_logic; -- Enable readout
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write_data : in std_logic_vector(7 downto 0); -- Write data
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read_data : out std_logic_vector(7 downto 0)); -- Read data
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end entity flacdec_64x08_memory;
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architecture RTL of flacdec_64x08_memory is
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type memory_arr_t is array(natural range <>) of std_logic_vector(7 downto 0);
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signal mem : memory_arr_t(0 to 63); -- Memory array
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signal addr_s : integer range 0 to 63; -- Memory access address
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begin -- architecture RTL
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addr_s <= to_integer(unsigned(address));
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memory_proc : process is
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begin
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wait until rising_edge(clk);
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if write_enable = '1' then
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mem(addr_s) <= write_data;
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end if;
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if read_enable = '1' then
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read_data <= mem(addr_s);
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end if;
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end process memory_proc;
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end architecture RTL;
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