-------------------------------------------------------------------------------
-- Title      : 64x08 byte single port memory
-- Project    : Shimatta VHDL FLAC Decoder
-------------------------------------------------------------------------------
-- File       : flacdec_64x08_memory.vhd
-- Author     : Mario Huettel  <mario.huettel@linux.com>
-- Company    : Shimatta
-- Created    : 2023-10-06
-- Last update: 2023-10-06
-- Platform   : 
-- Standard   : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a 64 byte single ported RAM implementation. This file
-- should be able to infer a BRAM on FPGA targets.
-- Swap this implementation on an ASIC flow in order to instantiate a fitting
-- memory instance.
-- Two instances of this memory are used in the input FIFO of the Flac decoder
-------------------------------------------------------------------------------
-- Copyright (c) 2023 
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity flacdec_64x08_memory is

    port (
        clk          : in  std_logic;                      -- Clock
        address      : in  std_logic_vector(5 downto 0);   -- RAM data address
        write_enable : in  std_logic;                      -- Write enable
        read_enable  : in  std_logic;                      -- Enable readout
        write_data   : in  std_logic_vector(7 downto 0);   -- Write data
        read_data    : out std_logic_vector(7 downto 0));  -- Read data

end entity flacdec_64x08_memory;

architecture RTL of flacdec_64x08_memory is
    type memory_arr_t is array(natural range <>) of std_logic_vector(7 downto 0);

    signal mem    : memory_arr_t(0 to 63);  -- Memory array
    signal addr_s : integer range 0 to 63;  -- Memory access address
begin  -- architecture RTL

    addr_s <= to_integer(unsigned(address));

    memory_proc : process is
    begin
        wait until rising_edge(clk);
        if write_enable = '1' then
            mem(addr_s) <= write_data;
        end if;
        if read_enable = '1' then
            read_data <= mem(addr_s);
        end if;
    end process memory_proc;

end architecture RTL;