------------------------------------------------------------------------------- -- Title : FIFO based on two single ported memory instances -- Project : Shimatta VHDL FLAC decoder ------------------------------------------------------------------------------- -- File : flacdec_double_mem_fifo.vhd -- Author : Mario Huettel -- Company : -- Created : 2023-10-06 -- Last update: 2023-10-07 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: This is a FIFO implementation based on two single ported memory -- instances, which will allow continuous read/write with minimal arbitration -- overhead. The memory instances have to be connected externally. ------------------------------------------------------------------------------- -- Copyright (c) 2023 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity flacdec_double_mem_fifo is generic ( ADDRESS_WIDTH : natural range 2 to 32 := 7; -- Adress width of the whole FIFO memory. Defining the FIFO size DATA_WIDTH : positive := 8); -- Data width in bits port ( clk : in std_logic; -- Clock rst_n : in std_logic; -- Async. low-active reset ---------------------------------------------------------------------- -- MEMORY 0 Connections ---------------------------------------------------------------------- mem0_address : out std_logic_vector(ADDRESS_WIDTH - 2 downto 0); mem0_write_enable : out std_logic; mem0_read_enable : out std_logic; mem0_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); mem0_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); ---------------------------------------------------------------------- -- MEMORY 1 Connections ---------------------------------------------------------------------- mem1_address : out std_logic_vector(ADDRESS_WIDTH - 2 downto 0); mem1_write_enable : out std_logic; mem1_read_enable : out std_logic; mem1_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); mem1_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); ---------------------------------------------------------------------- -- Input AXI Stream ---------------------------------------------------------------------- in_tdata : in std_logic_vector(DATA_WIDTH - 1 downto 0); in_tvalid : in std_logic; in_tready : out std_logic; ---------------------------------------------------------------------- -- Output AXI stream ---------------------------------------------------------------------- out_tdata : out std_logic_vector(DATA_WIDTH -1 downto 0); out_tvalid : out std_logic; out_tready : in std_logic; ---------------------------------------------------------------------- -- Control and status ---------------------------------------------------------------------- clear : in std_logic; flush_output : in std_logic; fill_level : out std_logic_vector(ADDRESS_WIDTH downto 0); empty : out std_logic; full : out std_logic; half_empty : out std_logic); end entity flacdec_double_mem_fifo; architecture RTL of flacdec_double_mem_fifo is constant FIFO_SIZE : natural := 2**ADDRESS_WIDTH; signal accepted_input_reg : std_logic_vector(DATA_WIDTH - 1 downto 0); signal accepted_input_valid_reg : std_logic; signal in_tready_s : std_logic; signal out_tvalid_reg : std_logic; signal out_tdata_buffer_reg : std_logic_vector(DATA_WIDTH - 1 downto 0); signal out_tdata_buffer_valid_reg : std_logic; signal fifo_read_out_data_s : std_logic_vector(DATA_WIDTH - 1 downto 0); signal out_ready_for_data_s : std_logic; signal write_pointer_reg : unsigned(ADDRESS_WIDTH downto 0); signal read_pointer_reg : unsigned(ADDRESS_WIDTH downto 0); signal write_address_s : std_logic_vector(ADDRESS_WIDTH - 1 downto 0); signal read_address_s : std_logic_vector(ADDRESS_WIDTH - 1 downto 0); signal write_enable : std_logic; signal read_enable : std_logic; signal mem0_read_enable_s : std_logic; signal mem1_read_enable_s : std_logic; signal write_dest_mem : std_logic; signal read_source_mem : std_logic; signal read_data_valid_reg : std_logic_vector(1 downto 0); signal fifo_full_s : std_logic; signal fifo_empty_s : std_logic; signal fifo_half_empty_s : std_logic; signal fifo_fill_level_s : integer range 0 to FIFO_SIZE; begin -- architecture RTL full <= fifo_full_s; empty <= fifo_empty_s; half_empty <= fifo_half_empty_s; fill_level <= std_logic_vector(to_unsigned(fifo_fill_level_s, fill_level'length)); in_tready <= in_tready_s; out_tvalid <= out_tvalid_reg; mem0_read_enable <= mem0_read_enable_s; mem1_read_enable <= mem1_read_enable_s; mem0_address <= write_address_s(write_address_s'high downto 1) when mem0_read_enable_s = '0' else read_address_s(read_address_s'high downto 1); mem1_address <= write_address_s(write_address_s'high downto 1) when mem1_read_enable_s = '0' else read_address_s(read_address_s'high downto 1); ------------------------------------------------------------------------------------------------------------------------------------------------- -- Writing end implementation ------------------------------------------------------------------------------------------------------------------------------------------------- write_address_s <= std_logic_vector(write_pointer_reg(write_pointer_reg'high - 1 downto 0)); -- Let LSB decide which memory to write to write_dest_mem <= write_pointer_reg(0); mem0_write_enable <= write_enable when write_dest_mem = '0' else '0'; mem1_write_enable <= write_enable when write_dest_mem = '1' else '0'; mem0_write_data <= accepted_input_reg; mem1_write_data <= accepted_input_reg; write_enable_proc : process(accepted_input_valid_reg, write_dest_mem, mem0_read_enable_s, mem1_read_enable_s, fifo_full_s) is begin write_enable <= '0'; -- Perform write if write destination does not collide with current -- read (This basically implements the arbitration between read and -- write, giving priority to the read path). if (write_dest_mem = '0' and mem0_read_enable_s = '0') or (write_dest_mem = '1' and mem1_read_enable_s = '0') then -- Write if data is available and the FIFO may take new data if accepted_input_valid_reg = '1' and fifo_full_s = '0' then write_enable <= '1'; end if; end if; end process write_enable_proc; -- Write pointer increment upon write action write_pointer_proc : process(clk, rst_n) is begin if rst_n = '0' then write_pointer_reg <= (others => '0'); elsif rising_edge(clk) then if clear = '1' then write_pointer_reg <= (others => '0'); elsif write_enable = '1' then -- Overflow expected write_pointer_reg <= write_pointer_reg + 1; end if; end if; end process write_pointer_proc; ----------------------------------------------------------------- -- AXI input ---------------------------------------------------------------- -- Generate the ready signal for the input stream axi_input_ready_proc : process(accepted_input_valid_reg, write_enable, clear) is begin in_tready_s <= '0'; if accepted_input_valid_reg = '0' then in_tready_s <= '1'; end if; if write_enable = '1' then in_tready_s <= '1'; end if; if clear = '1' then in_tready_s <= '0'; end if; end process axi_input_ready_proc; -- Accept the input datum into a FF buffer axi_input_proc : process(clk, rst_n) is begin if rst_n = '0' then accepted_input_reg <= (others => '0'); accepted_input_valid_reg <= '0'; elsif rising_edge(clk) then if write_enable = '1' or clear = '1' then -- Reset input buffer once datum is written to memory accepted_input_valid_reg <= '0'; end if; if in_tvalid = '1' and in_tready_s = '1' then -- Accept datum in buffer accepted_input_valid_reg <= '1'; accepted_input_reg <= in_tdata; end if; end if; end process axi_input_proc; ------------------------------------------------------------------------ -- FIFO status calculations ------------------------------------------------------------------------ fill_level_proc : process(read_pointer_reg, write_pointer_reg) is variable wrapped_around : boolean; variable read_addr : integer range 0 to FIFO_SIZE - 1; variable write_addr : integer range 0 to FIFO_SIZE - 1; begin wrapped_around := (read_pointer_reg(read_pointer_reg'high) /= write_pointer_reg(write_pointer_reg'high)); write_addr := to_integer(write_pointer_reg(write_pointer_reg'high - 1 downto 0)); read_addr := to_integer(read_pointer_reg(read_pointer_reg'high -1 downto 0)); if not wrapped_around then fifo_fill_level_s <= write_addr - read_addr; else fifo_fill_level_s <= FIFO_SIZE - read_addr + write_addr; end if; end process fill_level_proc; fifo_full_s <= '1' when write_address_s = read_address_s and read_pointer_reg(read_pointer_reg'high) /= write_pointer_reg(write_pointer_reg'high) else '0'; fifo_empty_s <= '1' when write_pointer_reg = read_pointer_reg else '0'; fifo_half_empty_s <= '1' when fifo_fill_level_s <= FIFO_SIZE / 2 else '0'; ----------------------------------------------------------------------------------------------------------------------------------------------- -- READ end implementation ----------------------------------------------------------------------------------------------------------------------------------------------- read_address_s <= std_logic_vector(read_pointer_reg(read_pointer_reg'high - 1 downto 0)); read_source_mem <= read_address_s(0); mem0_read_enable_s <= read_enable when read_source_mem = '0' else '0'; mem1_read_enable_s <= read_enable when read_source_mem = '1' else '0'; read_data_valid_proc : process(clk, rst_n) is begin if rst_n = '0' then read_data_valid_reg <= (others => '0'); elsif rising_edge(clk) then -- Delay read enables by one cycle, generating a valid signal read_data_valid_reg <= mem1_read_enable_s & mem0_read_enable_s; end if; end process read_data_valid_proc; -- Generate the read_enable signal -- Read from fifo if it is not empty and the output is able to accept a new -- datum. If clear is set, no read is requested. read_enable_proc : process(fifo_empty_s, out_ready_for_data_s, clear) is begin read_enable <= '0'; if fifo_empty_s = '0' and clear = '0' then if out_ready_for_data_s = '1' then read_enable <= '1'; end if; end if; end process read_enable_proc; read_pointer_proc : process(clk, rst_n) is begin if rst_n = '0' then read_pointer_reg <= (others => '0'); elsif rising_edge(clk) then if clear = '1' then read_pointer_reg <= (others => '0'); elsif read_enable = '1' then -- Overflow expected read_pointer_reg <= read_pointer_reg + 1; end if; end if; end process read_pointer_proc; -------------------- -- Output AXI stream --------------------- -- Read data mux fifo_read_out_data_s <= mem0_read_data when read_data_valid_reg(0) = '1' else mem1_read_data; -- Determine if output flops can be loaded with new data out_ready_for_data_s <= (not out_tvalid_reg) or out_tready; axi_output_proc : process(clk, rst_n) is begin if rst_n = '0' then out_tvalid_reg <= '0'; out_tdata <= (others => '0'); out_tdata_buffer_valid_reg <= '0'; out_tdata_buffer_reg <= (others => '0'); elsif rising_edge(clk) then if out_tready = '1' then out_tvalid_reg <= '0'; end if; if flush_output = '1' then -- Flush the output. This breaks the stream protocol! out_tvalid_reg <= '0'; out_tdata_buffer_valid_reg <= '0'; else -- Output is not flushed if out_ready_for_data_s = '1' then if out_tdata_buffer_valid_reg = '1' then out_tdata <= out_tdata_buffer_reg; out_tvalid_reg <= '1'; out_tdata_buffer_valid_reg <= '0'; elsif read_data_valid_reg /= "00" then out_tdata <= fifo_read_out_data_s; out_tvalid_reg <= '1'; end if; end if; -- Fill buffer register, if output is not ready for data or -- filled with old buffer data if read_data_valid_reg /= "00" and ((out_ready_for_data_s = '1' and out_tdata_buffer_valid_reg = '1') or out_ready_for_data_s = '0') then out_tdata_buffer_reg <= fifo_read_out_data_s; out_tdata_buffer_valid_reg <= '1'; end if; end if; end if; end process axi_output_proc; end architecture RTL;