-------------------------------------------------------------------------------
-- Title      : Input FIFO for FLAC data
-- Project    : Shimatta VHDL FLAC decoder
-------------------------------------------------------------------------------
-- File       : flacdec_input_fifo.vhd
-- Author     : Mario Huettel <mario.huettel@linux.com>
-- Company    : 
-- Created    : 2023-10-07
-- Last update: 2023-10-07
-- Platform   : 
-- Standard   : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: 128 byte input FIFO of FLAC core
-------------------------------------------------------------------------------
-- Copyright (c) 2023 
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity flacdec_input_fifo is

    port (
        clk          : in  std_logic;   -- CLock
        rst_n        : in  std_logic;   -- async. low-active reset
        ------------------------------------------------
        -- Input AXI stream
        ------------------------------------------------
        in_tdata     : in  std_logic_vector(7 downto 0);
        in_tvalid    : in  std_logic;
        in_tready    : out std_logic;
        ------------------------------------------------
        -- Output AXI Stream
        ------------------------------------------------
        out_tdata    : out std_logic_vector(7 downto 0);
        out_tvalid   : out std_logic;
        out_tready   : in  std_logic;
        ------------------------------------------------
        -- Control and status signals
        ------------------------------------------------
        clear        : in  std_logic;
        half_empty   : out std_logic;
        empty        : out std_logic;
        full         : out std_logic;
        flush_output : in  std_logic);

end entity flacdec_input_fifo;

architecture RTL of flacdec_input_fifo is
    constant ADDRESS_WIDTH : natural := 7;
    constant DATA_WIDTH    : natural := 8;

    signal mem0_address      : std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
    signal mem0_write_enable : std_logic;
    signal mem0_read_enable  : std_logic;
    signal mem0_write_data   : std_logic_vector(DATA_WIDTH - 1 downto 0);
    signal mem0_read_data    : std_logic_vector(DATA_WIDTH - 1 downto 0);
    signal mem1_address      : std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
    signal mem1_write_enable : std_logic;
    signal mem1_read_enable  : std_logic;
    signal mem1_write_data   : std_logic_vector(DATA_WIDTH - 1 downto 0);
    signal mem1_read_data    : std_logic_vector(DATA_WIDTH - 1 downto 0);

begin  -- architecture RTL

    -- FIFO logic core
    flacdec_double_mem_fifo_1 : entity work.flacdec_double_mem_fifo
        generic map (
            ADDRESS_WIDTH => ADDRESS_WIDTH,
            DATA_WIDTH    => DATA_WIDTH)
        port map (
            clk               => clk,
            rst_n             => rst_n,
            mem0_address      => mem0_address,
            mem0_write_enable => mem0_write_enable,
            mem0_read_enable  => mem0_read_enable,
            mem0_write_data   => mem0_write_data,
            mem0_read_data    => mem0_read_data,
            mem1_address      => mem1_address,
            mem1_write_enable => mem1_write_enable,
            mem1_read_enable  => mem1_read_enable,
            mem1_write_data   => mem1_write_data,
            mem1_read_data    => mem1_read_data,
            in_tdata          => in_tdata,
            in_tvalid         => in_tvalid,
            in_tready         => in_tready,
            out_tdata         => out_tdata,
            out_tvalid        => out_tvalid,
            out_tready        => out_tready,
            clear             => clear,
            flush_output      => flush_output,
            fill_level        => open,
            empty             => empty,
            full              => full,
            half_empty        => half_empty);

    ---------------------------------------------------------------
    -- Memory instances
    ---------------------------------------------------------------

    flacdec_64x08_memory_i0 : entity work.flacdec_64x08_memory
        port map (
            clk          => clk,
            address      => mem0_address,
            write_enable => mem0_write_enable,
            read_enable  => mem0_read_enable,
            write_data   => mem0_write_data,
            read_data    => mem0_read_data);

    flacdec_64x08_memory_i1 : entity work.flacdec_64x08_memory
        port map (
            clk          => clk,
            address      => mem1_address,
            write_enable => mem1_write_enable,
            read_enable  => mem1_read_enable,
            write_data   => mem1_write_data,
            read_data    => mem1_read_data);

end architecture RTL;