Mario Hüttel mhu
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mhu pushed to master at fpga/ws2812b-eth 2018-04-06 17:37:29 +02:00
4f4c36ffe8 init. Works on altera
mhu created repository fpga/ws2812b-eth 2018-04-06 17:37:15 +02:00
mhu pushed to master at pcb/vco 2018-03-09 11:58:04 +01:00
c0eb353cfe sma connector changed
mhu deleted tag master from fpga/avalon-dma 2018-03-06 15:11:17 +01:00
mhu pushed to master at fpga/avalon-dma 2018-03-06 15:11:17 +01:00
9d67bb6b01 init commit
mhu created repository fpga/avalon-dma 2018-03-06 15:10:09 +01:00
mhu pushed to master at pcb/vco 2018-03-04 22:51:35 +01:00
36eccec03c layout improvements
mhu pushed to master at pcb/vco 2018-03-04 02:36:44 +01:00
ee22bf02a3 release
mhu pushed to master at pcb/vco 2018-03-03 19:03:10 +01:00
c16aed923c input matching network replaced
mhu pushed to master at pcb/vco 2018-03-03 18:57:22 +01:00
7175a2b591 input matching network replaced
mhu pushed to master at pcb/vco 2018-03-03 18:26:14 +01:00
89838261c3 init
mhu deleted tag master from pcb/vco 2018-03-03 18:26:14 +01:00
mhu created repository pcb/vco 2018-03-03 18:25:36 +01:00
mhu pushed to master at pcb/shimatta-pcb-libs 2018-03-03 18:16:51 +01:00
1a30d46fb0 VFD, MAX2750
mhu pushed to master at fpga/tiny-xo2-uart-loader 2017-11-23 00:25:09 +01:00
27b97dce01 add exec state to FSM
mhu pushed to master at fpga/tiny-xo2-uart-loader 2017-11-23 00:16:53 +01:00
7dec75c52e timeout counter implemented, starting FSM that controls UART <=> Wishbone transfers
mhu pushed to master at fpga/tiny-xo2-uart-loader 2017-11-22 21:34:31 +01:00
ff25a4dabf fix parity in uart_tx, generate EFB/UFR IP for configuration
mhu deleted tag master from fpga/tiny-xo2-uart-loader 2017-11-21 22:40:41 +01:00
mhu pushed to master at fpga/tiny-xo2-uart-loader 2017-11-21 22:40:41 +01:00
a8dc43023e added synchronizer ip for UART, wrote reset detection
85a8de46f7 add uart and top vhd
mhu created repository fpga/tiny-xo2-uart-loader 2017-11-21 22:40:27 +01:00