54 lines
941 B
Plaintext
54 lines
941 B
Plaintext
EESchema Schematic File Version 4
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LIBS:adc-dac-cache
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EELAYER 26 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 1 6
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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S 650 650 1200 1600
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U 5B1CDB10
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F0 "ADAU1966-DAC" 50
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F1 "ADAU1966-DAC.sch" 50
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F2 "DAT[1..8]" I R 1850 750 50
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F3 "BCLK" I R 1850 2000 50
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F4 "LRCLK" I R 1850 1900 50
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F5 "MCLKO" O R 1850 1800 50
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F6 "~CLATCH" I R 1850 1550 50
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F7 "CCLK" I R 1850 1450 50
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F8 "COUT" I R 1850 1350 50
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F9 "CDATA" I R 1850 1250 50
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F10 "PU~RST" I R 1850 1150 50
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F11 "MCLK" I R 1850 1700 50
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$EndSheet
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Text Label 2000 750 0 50 ~ 0
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DAT[1..8]
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Wire Bus Line
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1850 750 2750 750
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$Sheet
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S 650 2550 1200 2500
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U 5B68D44E
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F0 "AD1974-ADC" 50
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F1 "AD1974-ADC.sch" 50
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$EndSheet
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$Sheet
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S 3550 650 2450 4450
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U 5B26F4A1
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F0 "fpga" 50
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F1 "fpga.sch" 50
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$EndSheet
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Wire Wire Line
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1850 1150 3500 1150
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Wire Wire Line
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1850 1250 3500 1250
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$EndSCHEMATC
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