pcb/bme680-air-meter
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Add 3d model for BME680

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This commit is contained in:
Mario Hüttel 2020-03-31 21:27:36 +02:00
parent e56ee0c5b4
commit 64129dffb0
5 changed files with 177 additions and 16 deletions
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BIN
3d/bme680.blend Normal file
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161
3d/bme680.x3d Normal file
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4
bme680-cache.lib
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@ -381,13 +381,13 @@ F1 "shimatta_connectors_10PIN_JTAG_SWD" 10 110 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -700 0 0 -1000 0 1 0 f
S -820 0 0 -1000 0 1 0 f
X VCC 1 100 -50 100 L 50 50 1 1 P
X RESET 10 100 -350 100 L 50 50 1 1 P
X TMS/SWDIO 2 100 -450 100 L 50 50 1 1 P
X GND 3 100 -250 100 L 50 50 1 1 P
X TCK/SWCLK 4 100 -550 100 L 50 50 1 1 P
X TESTMODE 5 100 -150 100 L 50 50 1 1 P
X TESTMODE/VCC/GND 5 100 -150 100 L 50 50 1 1 P
X TDO/SWO 6 100 -650 100 L 50 50 1 1 P
X RX/RTCLK 7 100 -850 100 L 50 50 1 1 P
X TDI 8 100 -750 100 L 50 50 1 1 P

6
bme680.kicad_pcb
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@ -1,4 +1,4 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.4)
(kicad_pcb (version 20171130) (host pcbnew 5.1.5)
(general
(thickness 1.6)
@ -2653,7 +2653,7 @@
(net 2 GND))
(pad 8 smd roundrect (at -1.2 1.1875) (size 0.5 0.525) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 +3V3))
(model ${KISYS3DMOD}/Package_LGA.3dshapes/Bosch_LGA-8_3x3mm_P0.8mm_ClockwisePinNumbering.wrl
(model ${KIPRJMOD}/3d/bme680.x3d
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
@ -2814,7 +2814,7 @@
(gr_text "SWD Debug" (at 60 66) (layer B.Mask)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text v1.0 (at 97 79) (layer B.Mask)
(gr_text v1.1 (at 97 79) (layer B.Mask)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text https://git.shimatta.de/pcb/bme680-air-meter (at 80 77) (layer B.Mask)

22
bme680.pro
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@ -1,4 +1,4 @@
update=Mon 26 Aug 2019 06:35:46 PM CEST
update=Tue 27 Aug 2019 09:41:23 PM CEST
version=1
last_client=kicad
[general]
@ -12,16 +12,6 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
@ -253,3 +243,13 @@ uViaDrill=0.1
dPairWidth=0.25
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1