EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:ti
LIBS:altera
LIBS:regulators
LIBS:pmic
LIBS:powersym
LIBS:osc
LIBS:con-molex
LIBS:dvi-sniffer-cache
EELAYER 26 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 1 5
Title "DVI-Sniffer -- Top"
Date ""
Rev "0.1"
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 1850 1450 1050 1250
U 5839A46D
F0 "power" 60
F1 "power.sch" 60
F2 "VIN" I L 1850 1550 60 
$EndSheet
$Comp
L BARREL_JACK CON?
U 1 1 583A22E7
P 1050 1650
F 0 "CON?" H 1031 1975 50  0000 C CNN
F 1 "BARREL_JACK" H 1031 1884 50  0000 C CNN
F 2 "" H 1050 1650 50  0000 C CNN
F 3 "" H 1050 1650 50  0000 C CNN
	1    1050 1650
	1    0    0    -1  
$EndComp
$Comp
L GND #PWR01
U 1 1 583A2391
P 1450 1850
F 0 "#PWR01" H 1450 1600 50  0001 C CNN
F 1 "GND" H 1455 1677 50  0000 C CNN
F 2 "" H 1450 1850 50  0000 C CNN
F 3 "" H 1450 1850 50  0000 C CNN
	1    1450 1850
	1    0    0    -1  
$EndComp
$Sheet
S 6600 3300 2000 2300
U 583A26B6
F0 "fpga" 60
F1 "fpga.sch" 60
F2 "DATI[0..23]" I L 6600 3500 60 
F3 "CLKIN" I L 6600 3700 60 
F4 "HSYNC_IN" I L 6600 3800 60 
F5 "VSYNC_IN" I L 6600 3900 60 
F6 "DE_IN" I L 6600 4000 60 
F7 "LINK_ACT_IN" I L 6600 4100 60 
F8 "TXCLK-" O R 8600 3800 60 
F9 "DATO[0..23]" O R 8600 3500 60 
F10 "HSYNC_OUT" O R 8600 3900 60 
F11 "VSYNC_OUT" O R 8600 4000 60 
F12 "DE_OUT" O R 8600 4100 60 
F13 "TXCLK+" O R 8600 3700 60 
F14 "DDCDAT_IN" B L 6600 4650 60 
F15 "DDCCLK_IN" I L 6600 4550 60 
F16 "DDCDAT_OUT" B R 8600 4650 60 
F17 "DDCCLK_OUT" O R 8600 4550 60 
F18 "HOTPLUG_OUT" O L 6600 4350 60 
F19 "HOTPLUG_IN" I R 8600 4350 60 
F20 "CTL_IN[1..3]" I L 6600 3400 60 
F21 "CTL_OUT[1..3]" O R 8600 3400 60 
$EndSheet
$Sheet
S 3900 3300 1550 2300
U 583B5F85
F0 "dvi_in" 60
F1 "dvi_in.sch" 60
F2 "DATI[0..23]" O R 5450 3500 60 
F3 "HOTPLUG" I R 5450 4350 60 
F4 "DDCCLK_IN" O R 5450 4550 60 
F5 "DDCDAT_IN" B R 5450 4650 60 
F6 "LINK_ACT" O R 5450 4100 60 
F7 "CTL[1..3]" O R 5450 3400 60 
F8 "DE" O R 5450 4000 60 
F9 "OCLK" O R 5450 3700 60 
F10 "HSYNC" O R 5450 3800 60 
F11 "VSYNC" O R 5450 3900 60 
$EndSheet
Text Label 5800 3500 0    60   ~ 0
DATI[0..23]
Wire Wire Line
	1350 1650 1450 1650
Wire Wire Line
	1450 1650 1450 1850
Wire Wire Line
	1450 1750 1350 1750
Connection ~ 1450 1750
Wire Wire Line
	1350 1550 1850 1550
Wire Bus Line
	5450 3500 6600 3500
Wire Wire Line
	5450 3700 6600 3700
Wire Wire Line
	5450 3800 6600 3800
Wire Wire Line
	5450 3900 6600 3900
Wire Wire Line
	5450 4000 6600 4000
Wire Wire Line
	5450 4100 6600 4100
Wire Bus Line
	5450 3400 6600 3400
Text Label 5800 3400 0    60   ~ 0
CTL_IN[1..3]
Wire Wire Line
	6600 4350 5450 4350
Wire Wire Line
	6600 4550 5450 4550
Wire Wire Line
	5450 4650 6600 4650
$Sheet
S 10200 3300 1250 2300
U 583BE4A7
F0 "dvi_out" 60
F1 "dvi_out.sch" 60
$EndSheet
$EndSCHEMATC