EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:ti
LIBS:altera
LIBS:regulators
LIBS:pmic
LIBS:powersym
LIBS:dvi-sniffer-cache
EELAYER 26 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 1 3
Title "DVI-Sniffer -- Top"
Date ""
Rev "0.1"
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 1850 1450 1050 1250
U 5839A46D
F0 "power" 60
F1 "power.sch" 60
F2 "VIN" I L 1850 1550 60 
$EndSheet
$Comp
L BARREL_JACK CON?
U 1 1 583A22E7
P 1050 1650
F 0 "CON?" H 1031 1975 50  0000 C CNN
F 1 "BARREL_JACK" H 1031 1884 50  0000 C CNN
F 2 "" H 1050 1650 50  0000 C CNN
F 3 "" H 1050 1650 50  0000 C CNN
	1    1050 1650
	1    0    0    -1  
$EndComp
Wire Wire Line
	1350 1650 1450 1650
Wire Wire Line
	1450 1650 1450 1850
Wire Wire Line
	1450 1750 1350 1750
Connection ~ 1450 1750
$Comp
L GND #PWR?
U 1 1 583A2391
P 1450 1850
F 0 "#PWR?" H 1450 1600 50  0001 C CNN
F 1 "GND" H 1455 1677 50  0000 C CNN
F 2 "" H 1450 1850 50  0000 C CNN
F 3 "" H 1450 1850 50  0000 C CNN
	1    1450 1850
	1    0    0    -1  
$EndComp
Wire Wire Line
	1350 1550 1850 1550
$Sheet
S 1850 3300 2000 2300
U 583A26B6
F0 "fpga" 60
F1 "fpga.sch" 60
$EndSheet
$EndSCHEMATC