293 lines
6.1 KiB
Plaintext
293 lines
6.1 KiB
Plaintext
EESchema Schematic File Version 4
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LIBS:dvi-sniffer-cache
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EELAYER 26 0
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EELAYER END
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$Descr A3 16535 11693
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encoding utf-8
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Sheet 1 5
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Title "DVI-Sniffer -- Top"
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Date ""
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Rev "0.1"
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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S 1850 1450 1050 1250
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U 5839A46D
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F0 "power" 60
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F1 "power.sch" 60
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F2 "VIN" I L 1850 1550 60
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$EndSheet
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$Comp
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L dvi-sniffer-rescue:BARREL_JACK CON101
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U 1 1 583A22E7
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P 1050 1650
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F 0 "CON101" H 1031 1975 50 0000 C CNN
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F 1 "PJ-002A" H 1031 1884 50 0000 C CNN
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F 2 "Connectors:BARREL_JACK" H 1050 1650 50 0001 C CNN
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F 3 "" H 1050 1650 50 0000 C CNN
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1 1050 1650
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1 0 0 -1
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$EndComp
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$Comp
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L dvi-sniffer-rescue:GND #PWR01
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U 1 1 583A2391
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P 1450 1850
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F 0 "#PWR01" H 1450 1600 50 0001 C CNN
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F 1 "GND" H 1455 1677 50 0000 C CNN
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F 2 "" H 1450 1850 50 0000 C CNN
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F 3 "" H 1450 1850 50 0000 C CNN
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1 1450 1850
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1 0 0 -1
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$EndComp
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$Sheet
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S 6100 900 2000 2300
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U 583A26B6
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F0 "fpga" 60
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F1 "fpga.sch" 60
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F2 "DATI[0..23]" I L 6100 1100 60
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F3 "CLKIN" I L 6100 1300 60
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F4 "HSYNC_IN" I L 6100 1400 60
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F5 "VSYNC_IN" I L 6100 1500 60
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F6 "DE_IN" I L 6100 1600 60
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F7 "LINK_ACT_IN" I L 6100 1700 60
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F8 "DATO[0..23]" O R 8100 1100 60
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F9 "HSYNC_OUT" O R 8100 1500 60
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F10 "VSYNC_OUT" O R 8100 1600 60
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F11 "DE_OUT" O R 8100 1700 60
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F12 "TXCLK+" O R 8100 1300 60
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F13 "DDCDAT_IN" B L 6100 2250 60
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F14 "DDCCLK_IN" I L 6100 2150 60
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F15 "DDCDAT_OUT" B R 8100 2250 60
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F16 "DDCCLK_OUT" O R 8100 2150 60
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F17 "HOTPLUG_OUT" O L 6100 1950 60
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F18 "HOTPLUG_IN" I R 8100 1950 60
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F19 "CTL_IN[1..3]" I L 6100 1000 60
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F20 "CTL_OUT[1..3]" O R 8100 1000 60
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F21 "DKEN_OUT" O R 8100 2350 60
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F22 "EDGE_OUT" O R 8100 2450 60
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F23 "POWERDOWN" O R 8100 2750 60
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F24 "GPIO[0..7]" B R 8100 3100 60
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$EndSheet
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$Sheet
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S 3400 900 1550 2300
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U 583B5F85
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F0 "dvi_in" 60
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F1 "dvi_in.sch" 60
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F2 "DATI[0..23]" O R 4950 1100 60
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F3 "HOTPLUG" I R 4950 1950 60
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F4 "DDCCLK_IN" O R 4950 2150 60
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F5 "DDCDAT_IN" B R 4950 2250 60
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F6 "LINK_ACT" O R 4950 1700 60
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F7 "CTL[1..3]" O R 4950 1000 60
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F8 "DE" O R 4950 1600 60
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F9 "OCLK" O R 4950 1300 60
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F10 "HSYNC" O R 4950 1400 60
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F11 "VSYNC" O R 4950 1500 60
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F12 "PDOWN" I R 4950 2750 60
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F13 "CEC" B R 4950 3100 60
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$EndSheet
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Text Label 5300 1100 0 60 ~ 0
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DATI[0..23]
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Wire Wire Line
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1350 1650 1450 1650
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Wire Wire Line
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1450 1650 1450 1750
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Wire Wire Line
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1450 1750 1350 1750
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Connection ~ 1450 1750
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Wire Wire Line
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1350 1550 1850 1550
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Wire Bus Line
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4950 1100 6100 1100
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Wire Wire Line
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4950 1300 6100 1300
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Wire Wire Line
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4950 1400 6100 1400
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Wire Wire Line
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4950 1500 6100 1500
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Wire Wire Line
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4950 1600 6100 1600
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Wire Wire Line
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4950 1700 6100 1700
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Wire Bus Line
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4950 1000 6100 1000
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Text Label 5300 1000 0 60 ~ 0
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CTL_IN[1..3]
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Wire Wire Line
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6100 1950 4950 1950
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Wire Wire Line
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6100 2150 4950 2150
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Wire Wire Line
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4950 2250 6100 2250
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$Sheet
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S 9700 900 1250 2300
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U 583BE4A7
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F0 "dvi_out" 60
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F1 "dvi_out.sch" 60
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F2 "TXCLK+" I L 9700 1300 60
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F3 "DATO[0..23]" I L 9700 1100 60
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F4 "VSYNC" I L 9700 1600 60
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F5 "HSYNC" I L 9700 1500 60
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F6 "DE" I L 9700 1700 60
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F7 "CTL[1..3]" I L 9700 1000 60
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F8 "MSEN" O L 9700 1800 60
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F9 "DDCCLK" I L 9700 2150 60
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F10 "DDCDAT" B L 9700 2250 60
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F11 "HOTPLUG" O L 9700 1950 60
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F12 "DKEN" I L 9700 2350 60
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F13 "EDGE" I L 9700 2450 60
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F14 "PDOWN" I L 9700 2750 60
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F15 "CEC" B L 9700 3050 60
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$EndSheet
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Wire Wire Line
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8100 1300 9700 1300
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Wire Wire Line
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9700 2150 8100 2150
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Wire Wire Line
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9700 2250 8100 2250
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Wire Wire Line
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9700 1950 8100 1950
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Wire Bus Line
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8100 1000 9700 1000
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Wire Bus Line
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9700 1100 8100 1100
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Text Label 8450 1000 0 60 ~ 0
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CTL_OUT[1..3]
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Text Label 8450 1100 0 60 ~ 0
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DATO[0..23]
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Wire Wire Line
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8100 1500 9700 1500
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Wire Wire Line
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9700 1600 8100 1600
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Wire Wire Line
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8100 1700 9700 1700
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Wire Wire Line
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8100 2350 9700 2350
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Wire Wire Line
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8100 2450 9700 2450
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Wire Wire Line
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4950 2750 5950 2750
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Wire Wire Line
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5950 2750 5950 3350
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Wire Wire Line
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5950 3350 8300 3350
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Wire Wire Line
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8300 3350 8300 2750
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Wire Wire Line
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8100 2750 8300 2750
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Connection ~ 8300 2750
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Wire Bus Line
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8100 3100 8800 3100
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Entry Wire Line
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8800 4900 8900 5000
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Entry Wire Line
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8800 4800 8900 4900
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Entry Wire Line
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8800 4700 8900 4800
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Entry Wire Line
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8800 4600 8900 4700
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Entry Wire Line
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8800 4500 8900 4600
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Entry Wire Line
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8800 4400 8900 4500
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Entry Wire Line
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8800 4300 8900 4400
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Entry Wire Line
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8800 4200 8900 4300
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Wire Wire Line
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8900 4300 9250 4300
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Wire Wire Line
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8900 4400 9250 4400
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Wire Wire Line
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8900 4500 9250 4500
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Wire Wire Line
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8900 4600 9250 4600
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Wire Wire Line
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9250 4700 8900 4700
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Wire Wire Line
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8900 4800 9250 4800
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Wire Wire Line
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9250 4900 8900 4900
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Wire Wire Line
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8900 5000 9250 5000
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Text Label 8350 3100 0 60 ~ 0
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GPIO[0..7]
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Text Label 8900 4300 0 60 ~ 0
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GPIO0
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Text Label 8900 4400 0 60 ~ 0
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GPIO1
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Text Label 8900 4500 0 60 ~ 0
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GPIO2
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Text Label 8900 4600 0 60 ~ 0
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GPIO3
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Text Label 8900 4700 0 60 ~ 0
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GPIO4
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Text Label 8900 4800 0 60 ~ 0
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GPIO5
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Text Label 8900 4900 0 60 ~ 0
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GPIO6
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Text Label 8900 5000 0 60 ~ 0
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GPIO7
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Wire Wire Line
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8900 4200 8900 3800
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$Comp
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L dvi-sniffer-rescue:GND #PWR02
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U 1 1 584D1EA7
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P 8900 3800
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F 0 "#PWR02" H 8900 3550 50 0001 C CNN
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F 1 "GND" H 8905 3627 50 0000 C CNN
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F 2 "" H 8900 3800 50 0000 C CNN
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F 3 "" H 8900 3800 50 0000 C CNN
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1 8900 3800
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-1 0 0 1
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$EndComp
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$Comp
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L dvi-sniffer-rescue:+3V3 #PWR03
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U 1 1 584D223B
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P 9100 3800
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F 0 "#PWR03" H 9100 3650 50 0001 C CNN
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F 1 "+3V3" H 9100 3950 50 0000 C CNN
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F 2 "" H 9100 3800 50 0000 C CNN
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F 3 "" H 9100 3800 50 0000 C CNN
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1 9100 3800
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1 0 0 -1
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$EndComp
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Wire Wire Line
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9100 3800 9100 4100
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Wire Wire Line
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9100 4100 9250 4100
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$Comp
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L dvi-sniffer-rescue:CONN_01X10 P101
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U 1 1 587A3F51
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P 9450 4550
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F 0 "P101" H 9528 4591 50 0000 L CNN
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F 1 "CONN_01X10" H 9528 4500 50 0000 L CNN
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F 2 "Pin_Headers:Pin_Header_Angled_1x10_Pitch2.54mm" H 9450 4550 50 0001 C CNN
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F 3 "" H 9450 4550 50 0000 C CNN
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1 9450 4550
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1 0 0 -1
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$EndComp
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Wire Wire Line
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8900 4200 9250 4200
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Wire Wire Line
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4950 3100 5400 3100
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Wire Wire Line
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5400 3100 5400 3450
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Wire Wire Line
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5400 3450 9450 3450
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Wire Wire Line
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9450 3450 9450 3050
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Wire Wire Line
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9450 3050 9700 3050
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Wire Wire Line
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1450 1750 1450 1850
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Wire Wire Line
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8300 2750 9700 2750
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Wire Bus Line
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8800 3100 8800 4900
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$EndSCHEMATC
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