pcb/headphone-amp
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abecd9411a
headphone-amp/headphone-amp.kicad_pcb

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Layouted first draft
2017-06-09 00:41:36 +02:00
(kicad_pcb (version 4) (host pcbnew 4.0.6)
(general
add balance poti
2017-08-28 22:59:34 +02:00
(links 190)
fix silkscreen
2017-08-28 23:00:45 +02:00
(no_connects 0)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(area 10.724999 13.424999 118.275001 63.575001)
Layouted first draft
2017-06-09 00:41:36 +02:00
(thickness 1.6)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(drawings 5)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(tracks 826)
Layouted first draft
2017-06-09 00:41:36 +02:00
(zones 0)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(modules 95)
(nets 69)
Layouted first draft
2017-06-09 00:41:36 +02:00
)
(page A4)
(layers
finished
2017-09-09 23:17:16 +02:00
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
Layouted first draft
2017-06-09 00:41:36 +02:00
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user hide)
(49 F.Fab user hide)
)
(setup
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(last_trace_width 0.4)
Layouted first draft
2017-06-09 00:41:36 +02:00
(user_trace_width 0.2)
(user_trace_width 0.25)
(user_trace_width 0.6)
(user_trace_width 0.8)
(user_trace_width 1.5)
(trace_clearance 0.2)
(zone_clearance 0.3)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(zone_45_only yes)
Layouted first draft
2017-06-09 00:41:36 +02:00
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(user_via 0.5 0.3)
(user_via 1.3 1)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(pad_size 1.8 3)
(pad_drill 1.1)
Layouted first draft
2017-06-09 00:41:36 +02:00
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements FFFFFFFF)
(pcbplotparams
finished
2017-09-09 23:17:16 +02:00
(layerselection 0x010f0_80000001)
(usegerberextensions true)
Layouted first draft
2017-06-09 00:41:36 +02:00
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
finished
2017-09-09 23:17:16 +02:00
(plotvalue false)
Layouted first draft
2017-06-09 00:41:36 +02:00
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
finished
2017-09-09 23:17:16 +02:00
(drillshape 0)
Layouted first draft
2017-06-09 00:41:36 +02:00
(scaleselection 1)
finished
2017-09-09 23:17:16 +02:00
(outputdirectory gerber/))
Layouted first draft
2017-06-09 00:41:36 +02:00
)
(net 0 "")
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 1 Earth)
(net 2 "Net-(C1-Pad1)")
(net 3 +5V)
(net 4 "Net-(C4-Pad2)")
(net 5 "Net-(C5-Pad1)")
(net 6 +3V3)
(net 7 "Net-(C7-Pad2)")
(net 8 "Net-(C7-Pad1)")
(net 9 "Net-(C8-Pad2)")
(net 10 "Net-(C8-Pad1)")
(net 11 /LUSB)
(net 12 "Net-(C9-Pad1)")
(net 13 "Net-(C12-Pad1)")
(net 14 "Net-(C13-Pad2)")
(net 15 "Net-(C14-Pad1)")
(net 16 /RUSB)
(net 17 "Net-(C15-Pad1)")
(net 18 GNDPWR)
(net 19 "Net-(C16-Pad1)")
(net 20 "Net-(C17-Pad2)")
(net 21 "Net-(C18-Pad2)")
(net 22 "Net-(C21-Pad1)")
(net 23 "Net-(C22-Pad2)")
(net 24 +12V)
(net 25 -12V)
(net 26 "Net-(C27-Pad1)")
(net 27 "Net-(C29-Pad1)")
(net 28 "Net-(C30-Pad1)")
(net 29 "Net-(C31-Pad1)")
(net 30 "Net-(C33-Pad2)")
(net 31 "Net-(C35-Pad2)")
(net 32 "Net-(D1-Pad1)")
(net 33 "Net-(J1-Pad4)")
(net 34 /D+)
(net 35 /D-)
(net 36 GNDA)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 37 "Net-(J4-Pad4)")
(net 38 "Net-(J4-Pad6)")
(net 39 "Net-(J4-Pad5)")
(net 40 "Net-(J4-Pad2)")
(net 41 "Net-(J4-Pad3)")
(net 42 "Net-(K1-Pad6)")
(net 43 "Net-(K1-Pad3)")
(net 44 "Net-(R2-Pad2)")
(net 45 "Net-(R3-Pad1)")
(net 46 "Net-(R7-Pad2)")
(net 47 "Net-(R11-Pad2)")
(net 48 "Net-(R10-Pad2)")
(net 49 "Net-(R12-Pad2)")
(net 50 "Net-(R13-Pad2)")
(net 51 "Net-(R14-Pad1)")
(net 52 "Net-(R15-Pad2)")
(net 53 "Net-(R16-Pad1)")
(net 54 "Net-(TP1-Pad1)")
(net 55 "Net-(TP2-Pad1)")
(net 56 "Net-(TP3-Pad1)")
(net 57 "Net-(U1-Pad5)")
(net 58 "Net-(U1-Pad3)")
(net 59 "Net-(U1-Pad2)")
(net 60 "Net-(TP4-Pad1)")
(net 61 "Net-(C37-Pad1)")
(net 62 "Net-(C38-Pad1)")
(net 63 "Net-(K1-Pad1)")
(net 64 "Net-(K2-Pad1)")
(net 65 "Net-(R23-Pad2)")
(net 66 "Net-(R23-Pad1)")
(net 67 "Net-(R24-Pad2)")
(net 68 "Net-(R24-Pad1)")
Layouted first draft
2017-06-09 00:41:36 +02:00
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.4)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +12V)
(add_net +3V3)
(add_net +5V)
(add_net -12V)
(add_net /D+)
(add_net /D-)
(add_net /LUSB)
(add_net /RUSB)
(add_net Earth)
(add_net GNDA)
(add_net GNDPWR)
(add_net "Net-(C1-Pad1)")
(add_net "Net-(C12-Pad1)")
(add_net "Net-(C13-Pad2)")
(add_net "Net-(C14-Pad1)")
(add_net "Net-(C15-Pad1)")
(add_net "Net-(C16-Pad1)")
(add_net "Net-(C17-Pad2)")
(add_net "Net-(C18-Pad2)")
(add_net "Net-(C21-Pad1)")
(add_net "Net-(C22-Pad2)")
(add_net "Net-(C27-Pad1)")
(add_net "Net-(C29-Pad1)")
(add_net "Net-(C30-Pad1)")
(add_net "Net-(C31-Pad1)")
(add_net "Net-(C33-Pad2)")
(add_net "Net-(C35-Pad2)")
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(add_net "Net-(C37-Pad1)")
(add_net "Net-(C38-Pad1)")
Layouted first draft
2017-06-09 00:41:36 +02:00
(add_net "Net-(C4-Pad2)")
(add_net "Net-(C5-Pad1)")
(add_net "Net-(C7-Pad1)")
(add_net "Net-(C7-Pad2)")
(add_net "Net-(C8-Pad1)")
(add_net "Net-(C8-Pad2)")
(add_net "Net-(C9-Pad1)")
(add_net "Net-(D1-Pad1)")
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(add_net "Net-(J1-Pad4)")
Layouted first draft
2017-06-09 00:41:36 +02:00
(add_net "Net-(J4-Pad2)")
(add_net "Net-(J4-Pad3)")
(add_net "Net-(J4-Pad4)")
(add_net "Net-(J4-Pad5)")
(add_net "Net-(J4-Pad6)")
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(add_net "Net-(K1-Pad1)")
Layouted first draft
2017-06-09 00:41:36 +02:00
(add_net "Net-(K1-Pad3)")
(add_net "Net-(K1-Pad6)")
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(add_net "Net-(K2-Pad1)")
Layouted first draft
2017-06-09 00:41:36 +02:00
(add_net "Net-(R10-Pad2)")
(add_net "Net-(R11-Pad2)")
(add_net "Net-(R12-Pad2)")
(add_net "Net-(R13-Pad2)")
(add_net "Net-(R14-Pad1)")
(add_net "Net-(R15-Pad2)")
(add_net "Net-(R16-Pad1)")
(add_net "Net-(R2-Pad2)")
add balance poti
2017-08-28 22:59:34 +02:00
(add_net "Net-(R23-Pad1)")
(add_net "Net-(R23-Pad2)")
(add_net "Net-(R24-Pad1)")
(add_net "Net-(R24-Pad2)")
Layouted first draft
2017-06-09 00:41:36 +02:00
(add_net "Net-(R3-Pad1)")
(add_net "Net-(R7-Pad2)")
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(add_net "Net-(TP1-Pad1)")
(add_net "Net-(TP2-Pad1)")
(add_net "Net-(TP3-Pad1)")
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(add_net "Net-(TP4-Pad1)")
Layouted first draft
2017-06-09 00:41:36 +02:00
(add_net "Net-(U1-Pad2)")
(add_net "Net-(U1-Pad3)")
(add_net "Net-(U1-Pad5)")
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(module Capacitors_THT:C_Radial_D8_L11.5_P3.5 (layer F.Cu) (tedit 0) (tstamp 5978A803)
(at 83 22.5 270)
(descr "Radial Electrolytic Capacitor Diameter 8mm x Length 11.5mm, Pitch 3.5mm")
(tags "Electrolytic Capacitor")
(path /593064DB)
(fp_text reference C25 (at 1.75 -5.3 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100u (at 1.75 5.3 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.75 0) (end 1.75 -4.3) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1.75 0) (end 1.75 -4.0375) (layer F.SilkS) (width 0.15))
(fp_circle (center 3.5 0) (end 3.5 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 5.745 -0.2) (end 5.745 0.2) (layer F.SilkS) (width 0.15))
(fp_line (start 5.605 -1.067) (end 5.605 1.067) (layer F.SilkS) (width 0.15))
(fp_line (start 5.465 -1.483) (end 5.465 1.483) (layer F.SilkS) (width 0.15))
(fp_line (start 5.325 -1.794) (end 5.325 1.794) (layer F.SilkS) (width 0.15))
(fp_line (start 5.185 -2.05) (end 5.185 2.05) (layer F.SilkS) (width 0.15))
(fp_line (start 5.045 -2.268) (end 5.045 2.268) (layer F.SilkS) (width 0.15))
(fp_line (start 4.905 -2.459) (end 4.905 2.459) (layer F.SilkS) (width 0.15))
(fp_line (start 4.765 -2.629) (end 4.765 2.629) (layer F.SilkS) (width 0.15))
(fp_line (start 4.625 -2.781) (end 4.625 2.781) (layer F.SilkS) (width 0.15))
(fp_line (start 4.485 0.173) (end 4.485 2.919) (layer F.SilkS) (width 0.15))
(fp_line (start 4.485 -2.919) (end 4.485 -0.173) (layer F.SilkS) (width 0.15))
(fp_line (start 4.345 0.535) (end 4.345 3.044) (layer F.SilkS) (width 0.15))
(fp_line (start 4.345 -3.044) (end 4.345 -0.535) (layer F.SilkS) (width 0.15))
(fp_line (start 4.205 0.709) (end 4.205 3.158) (layer F.SilkS) (width 0.15))
(fp_line (start 4.205 -3.158) (end 4.205 -0.709) (layer F.SilkS) (width 0.15))
(fp_line (start 4.065 0.825) (end 4.065 3.262) (layer F.SilkS) (width 0.15))
(fp_line (start 4.065 -3.262) (end 4.065 -0.825) (layer F.SilkS) (width 0.15))
(fp_line (start 3.925 0.905) (end 3.925 3.357) (layer F.SilkS) (width 0.15))
(fp_line (start 3.925 -3.357) (end 3.925 -0.905) (layer F.SilkS) (width 0.15))
(fp_line (start 3.785 0.959) (end 3.785 3.444) (layer F.SilkS) (width 0.15))
(fp_line (start 3.785 -3.444) (end 3.785 -0.959) (layer F.SilkS) (width 0.15))
(fp_line (start 3.645 0.989) (end 3.645 3.523) (layer F.SilkS) (width 0.15))
(fp_line (start 3.645 -3.523) (end 3.645 -0.989) (layer F.SilkS) (width 0.15))
(fp_line (start 3.505 1) (end 3.505 3.594) (layer F.SilkS) (width 0.15))
(fp_line (start 3.505 -3.594) (end 3.505 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 3.365 0.991) (end 3.365 3.659) (layer F.SilkS) (width 0.15))
(fp_line (start 3.365 -3.659) (end 3.365 -0.991) (layer F.SilkS) (width 0.15))
(fp_line (start 3.225 0.961) (end 3.225 3.718) (layer F.SilkS) (width 0.15))
(fp_line (start 3.225 -3.718) (end 3.225 -0.961) (layer F.SilkS) (width 0.15))
(fp_line (start 3.085 0.91) (end 3.085 3.771) (layer F.SilkS) (width 0.15))
(fp_line (start 3.085 -3.771) (end 3.085 -0.91) (layer F.SilkS) (width 0.15))
(fp_line (start 2.945 0.832) (end 2.945 3.817) (layer F.SilkS) (width 0.15))
(fp_line (start 2.945 -3.817) (end 2.945 -0.832) (layer F.SilkS) (width 0.15))
(fp_line (start 2.805 0.719) (end 2.805 3.858) (layer F.SilkS) (width 0.15))
(fp_line (start 2.805 -3.858) (end 2.805 -0.719) (layer F.SilkS) (width 0.15))
(fp_line (start 2.665 0.55) (end 2.665 3.894) (layer F.SilkS) (width 0.15))
(fp_line (start 2.665 -3.894) (end 2.665 -0.55) (layer F.SilkS) (width 0.15))
(fp_line (start 2.525 0.222) (end 2.525 3.924) (layer F.SilkS) (width 0.15))
(fp_line (start 2.525 -3.924) (end 2.525 -0.222) (layer F.SilkS) (width 0.15))
(fp_line (start 2.385 -3.949) (end 2.385 3.949) (layer F.SilkS) (width 0.15))
(fp_line (start 2.245 -3.969) (end 2.245 3.969) (layer F.SilkS) (width 0.15))
(fp_line (start 2.105 -3.984) (end 2.105 3.984) (layer F.SilkS) (width 0.15))
(fp_line (start 1.965 -3.994) (end 1.965 3.994) (layer F.SilkS) (width 0.15))
(fp_line (start 1.825 -3.999) (end 1.825 3.999) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 24 +12V))
(pad 2 thru_hole circle (at 3.5 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D8_L11.5_P3.5.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(module Connectors:USB_Mini-B (layer F.Cu) (tedit 5543E571) (tstamp 5978A85A)
(at 17 28.5)
(descr "USB Mini-B 5-pin SMD connector")
(tags "USB USB_B USB_Mini connector")
(path /5976A1B4)
(attr smd)
(fp_text reference J1 (at -1.85 6.61) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value USB_OTG (at 0 -7.0993) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 4.59994 -3.85064) (end -4.59994 -3.85064) (layer F.SilkS) (width 0.15))
(fp_line (start 4.59994 3.85064) (end 4.59994 -3.85064) (layer F.SilkS) (width 0.15))
(fp_line (start -4.59994 3.85064) (end 4.59994 3.85064) (layer F.SilkS) (width 0.15))
(fp_line (start -4.59994 -3.85064) (end -4.59994 3.85064) (layer F.SilkS) (width 0.15))
(fp_line (start -3.59918 -3.85064) (end -3.59918 3.85064) (layer F.SilkS) (width 0.15))
(fp_line (start -4.85 5.7) (end -4.85 -5.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 5.7) (end -4.85 5.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 -5.7) (end 4.85 5.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.85 -5.7) (end 4.85 -5.7) (layer F.CrtYd) (width 0.05))
(pad "" np_thru_hole circle (at 0.8509 2.19964) (size 0.89916 0.89916) (drill 0.89916) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0.8509 -2.19964) (size 0.89916 0.89916) (drill 0.89916) (layers *.Cu *.Mask))
(pad 6 smd rect (at -2.14884 4.45008) (size 2.49936 1.99898) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 6 smd rect (at 3.35026 4.45008) (size 2.49936 1.99898) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 6 smd rect (at -2.14884 -4.45008) (size 2.49936 1.99898) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 6 smd rect (at 3.35026 -4.45008) (size 2.49936 1.99898) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 5 smd rect (at 3.44932 1.6002) (size 2.30124 0.50038) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 4 smd rect (at 3.44932 0.8001) (size 2.30124 0.50038) (layers F.Cu F.Paste F.Mask)
(net 33 "Net-(J1-Pad4)"))
(pad 3 smd rect (at 3.44932 0) (size 2.30124 0.50038) (layers F.Cu F.Paste F.Mask)
(net 34 /D+))
(pad 2 smd rect (at 3.44932 -0.8001) (size 2.30124 0.50038) (layers F.Cu F.Paste F.Mask)
(net 35 /D-))
(pad 1 smd rect (at 3.44932 -1.6002) (size 2.30124 0.50038) (layers F.Cu F.Paste F.Mask)
(net 3 +5V))
)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(module Capacitors_THT:C_Radial_D5_L11_P2 (layer F.Cu) (tedit 0) (tstamp 5978A773)
(at 31.98 36.22 270)
(descr "Radial Electrolytic Capacitor 5mm x Length 11mm, Pitch 2mm")
(tags "Electrolytic Capacitor")
(path /5934B839)
(fp_text reference C1 (at 1 -3.8 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10u (at 1 3.8 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1 0) (end 1 -2.8) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1 0) (end 1 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 2 0) (end 2 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 3.455 -0.472) (end 3.455 0.472) (layer F.SilkS) (width 0.15))
(fp_line (start 3.315 -0.944) (end 3.315 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.175 -1.233) (end 3.175 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.035 -1.452) (end 3.035 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 2.895 -1.631) (end 2.895 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 0.265) (end 2.755 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 -1.78) (end 2.755 -0.265) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 0.512) (end 2.615 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 -1.908) (end 2.615 -0.512) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 0.644) (end 2.475 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 -2.019) (end 2.475 -0.644) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 0.726) (end 2.335 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 -2.114) (end 2.335 -0.726) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 0.776) (end 2.195 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 -2.196) (end 2.195 -0.776) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 0.798) (end 2.055 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 -2.266) (end 2.055 -0.798) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 0.795) (end 1.915 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 -2.327) (end 1.915 -0.795) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 0.768) (end 1.775 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 -2.377) (end 1.775 -0.768) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 0.712) (end 1.635 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 -2.418) (end 1.635 -0.712) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 0.62) (end 1.495 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 -2.451) (end 1.495 -0.62) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 0.473) (end 1.355 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 -2.475) (end 1.355 -0.473) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 0.154) (end 1.215 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 -2.491) (end 1.215 -0.154) (layer F.SilkS) (width 0.15))
(fp_line (start 1.075 -2.499) (end 1.075 2.499) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole circle (at 2 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 1 Earth))
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 2 "Net-(C1-Pad1)"))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A779)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 25.5 35.5)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934BF3E)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference C2 (at 0.51 -2.14) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 2 "Net-(C1-Pad1)"))
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A77F)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 21.5 35.5)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59305590)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C3 (at -3.5 0) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 200n (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 3 +5V))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A785)
(at 35.75 33.59 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934A4BD)
(attr smd)
(fp_text reference C4 (at 0 1.9 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1u (at 0 -1.9 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 4 "Net-(C4-Pad2)"))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A78B)
(at 37.5 17.5)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59348C90)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C5 (at 0 -1.5) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 27p (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 5 "Net-(C5-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A791)
(at 32.5 28.5 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934D473)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference C6 (at 2.5 -0.1 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 200n (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A797)
(at 18 43 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5935AC3B)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C7 (at 0 1.75 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 7 "Net-(C7-Pad2)"))
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 8 "Net-(C7-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A79D)
(at 22 48.5 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5935A9B7)
(attr smd)
(fp_text reference C8 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1u (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 9 "Net-(C8-Pad2)"))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 10 "Net-(C8-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7A3)
(at 36 41.55 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /593501B5)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C9 (at 0 1.75 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 11 /LUSB))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(C9-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_Tantalum_SMD:Tantalum_Case-D_EIA-7343-31_Hand (layer F.Cu) (tedit 57B6E980) (tstamp 5978A7A9)
(at 58 50)
(descr "Tantalum capacitor, Case D, EIA 7343-31, 7.3x4.3x2.8mm, Hand soldering footprint")
(tags "capacitor tantalum smd")
(path /593055F7)
(attr smd)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(fp_text reference C10 (at -0.08 0.01) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100u (at 0 3.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -5.95 -2.4) (end -5.95 2.4) (layer F.SilkS) (width 0.15))
(fp_line (start -5.95 2.4) (end 3.65 2.4) (layer F.SilkS) (width 0.15))
(fp_line (start -5.95 -2.4) (end 3.65 -2.4) (layer F.SilkS) (width 0.15))
(fp_line (start -2.555 -2.15) (end -2.555 2.15) (layer F.Fab) (width 0.15))
(fp_line (start -2.92 -2.15) (end -2.92 2.15) (layer F.Fab) (width 0.15))
(fp_line (start 3.65 -2.15) (end -3.65 -2.15) (layer F.Fab) (width 0.15))
(fp_line (start 3.65 2.15) (end 3.65 -2.15) (layer F.Fab) (width 0.15))
(fp_line (start -3.65 2.15) (end 3.65 2.15) (layer F.Fab) (width 0.15))
(fp_line (start -3.65 -2.15) (end -3.65 2.15) (layer F.Fab) (width 0.15))
(fp_line (start 6.05 -2.5) (end -6.05 -2.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 2.5) (end 6.05 -2.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.05 2.5) (end 6.05 2.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.05 -2.5) (end -6.05 2.5) (layer F.CrtYd) (width 0.05))
(pad 2 smd rect (at 3.775 0) (size 3.75 2.7) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -3.775 0) (size 3.75 2.7) (layers F.Cu F.Paste F.Mask)
(net 3 +5V))
(model Capacitors_Tantalum_SMD.3dshapes/Tantalum_Case-D_EIA-7343-31.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A7AF)
(at 56.5 43.05 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5930565F)
(attr smd)
(fp_text reference C11 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 3 +5V))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7B5)
(at 38.5 41.5 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934FA03)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C12 (at 2.75 0.5 540) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22n (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 13 "Net-(C12-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7BB)
(at 41 41.5 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934F029)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C13 (at -2.75 0.25 360) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22n (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 14 "Net-(C13-Pad2)"))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7C1)
(at 41.5 17.5 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59348F37)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C14 (at 0 1.5 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 27p (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 15 "Net-(C14-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7C7)
(at 43 41.5 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934F52B)
(attr smd)
(fp_text reference C15 (at 0 -1.9 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 16 /RUSB))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 17 "Net-(C15-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Radial_D5_L11_P2 (layer F.Cu) (tedit 0) (tstamp 5978A7CD)
(at 64.36 22.92 270)
(descr "Radial Electrolytic Capacitor 5mm x Length 11mm, Pitch 2mm")
(tags "Electrolytic Capacitor")
(path /59305A96)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference C16 (at -2.72 -0.04 360) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10u (at 1 3.8 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1 0) (end 1 -2.8) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1 0) (end 1 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 2 0) (end 2 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 3.455 -0.472) (end 3.455 0.472) (layer F.SilkS) (width 0.15))
(fp_line (start 3.315 -0.944) (end 3.315 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.175 -1.233) (end 3.175 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.035 -1.452) (end 3.035 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 2.895 -1.631) (end 2.895 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 0.265) (end 2.755 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 -1.78) (end 2.755 -0.265) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 0.512) (end 2.615 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 -1.908) (end 2.615 -0.512) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 0.644) (end 2.475 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 -2.019) (end 2.475 -0.644) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 0.726) (end 2.335 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 -2.114) (end 2.335 -0.726) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 0.776) (end 2.195 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 -2.196) (end 2.195 -0.776) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 0.798) (end 2.055 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 -2.266) (end 2.055 -0.798) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 0.795) (end 1.915 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 -2.327) (end 1.915 -0.795) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 0.768) (end 1.775 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 -2.377) (end 1.775 -0.768) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 0.712) (end 1.635 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 -2.418) (end 1.635 -0.712) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 0.62) (end 1.495 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 -2.451) (end 1.495 -0.62) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 0.473) (end 1.355 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 -2.475) (end 1.355 -0.473) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 0.154) (end 1.215 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 -2.491) (end 1.215 -0.154) (layer F.SilkS) (width 0.15))
(fp_line (start 1.075 -2.499) (end 1.075 2.499) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole circle (at 2 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(C16-Pad1)"))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Radial_D5_L11_P2 (layer F.Cu) (tedit 0) (tstamp 5978A7D3)
(at 64.5 29 270)
(descr "Radial Electrolytic Capacitor 5mm x Length 11mm, Pitch 2mm")
(tags "Electrolytic Capacitor")
(path /59305B29)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C17 (at 0 3.5 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10u (at 1 3.8 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1 0) (end 1 -2.8) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1 0) (end 1 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 2 0) (end 2 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 3.455 -0.472) (end 3.455 0.472) (layer F.SilkS) (width 0.15))
(fp_line (start 3.315 -0.944) (end 3.315 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.175 -1.233) (end 3.175 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.035 -1.452) (end 3.035 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 2.895 -1.631) (end 2.895 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 0.265) (end 2.755 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 -1.78) (end 2.755 -0.265) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 0.512) (end 2.615 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 -1.908) (end 2.615 -0.512) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 0.644) (end 2.475 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 -2.019) (end 2.475 -0.644) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 0.726) (end 2.335 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 -2.114) (end 2.335 -0.726) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 0.776) (end 2.195 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 -2.196) (end 2.195 -0.776) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 0.798) (end 2.055 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 -2.266) (end 2.055 -0.798) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 0.795) (end 1.915 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 -2.327) (end 1.915 -0.795) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 0.768) (end 1.775 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 -2.377) (end 1.775 -0.768) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 0.712) (end 1.635 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 -2.418) (end 1.635 -0.712) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 0.62) (end 1.495 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 -2.451) (end 1.495 -0.62) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 0.473) (end 1.355 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 -2.475) (end 1.355 -0.473) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 0.154) (end 1.215 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 -2.491) (end 1.215 -0.154) (layer F.SilkS) (width 0.15))
(fp_line (start 1.075 -2.499) (end 1.075 2.499) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole circle (at 2 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C17-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A7D9)
(at 39.5 34.5)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934A59B)
(attr smd)
(fp_text reference C18 (at 0 1.9) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1u (at 0 -1.9) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 21 "Net-(C18-Pad2)"))
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A7DF)
(at 56 32 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59305CF8)
(attr smd)
(fp_text reference C19 (at 0 1.9 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 18 GNDPWR))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 19 "Net-(C16-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A7E5)
(at 56 36.5 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59305D6F)
(attr smd)
(fp_text reference C20 (at 0 1.9 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 20 "Net-(C17-Pad2)"))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 18 GNDPWR))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7EB)
(at 46 34 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934A14D)
(attr smd)
(fp_text reference C21 (at 0 -1.9 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 22 "Net-(C21-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A7F1)
(at 42.5 32.5 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59349E35)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C22 (at 1.25 -1.75 90) (layer B.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1u (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 23 "Net-(C22-Pad2)"))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7F7)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 73 28 180)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59306354)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C23 (at -3.5 0.75 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 24 +12V))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7FD)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 73 35.25 270)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59306303)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C24 (at 3.25 -0.25 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(fp_text value 100n (at 0 1.9 270) (layer F.Fab)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 25 -12V))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 18 GNDPWR))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Radial_D8_L11.5_P3.5 (layer F.Cu) (tedit 0) (tstamp 5978A809)
(at 78.5 31 270)
(descr "Radial Electrolytic Capacitor Diameter 8mm x Length 11.5mm, Pitch 3.5mm")
(tags "Electrolytic Capacitor")
(path /59306550)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C26 (at 4.75 -4.5 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100u (at 1.75 5.3 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.75 0) (end 1.75 -4.3) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1.75 0) (end 1.75 -4.0375) (layer F.SilkS) (width 0.15))
(fp_circle (center 3.5 0) (end 3.5 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 5.745 -0.2) (end 5.745 0.2) (layer F.SilkS) (width 0.15))
(fp_line (start 5.605 -1.067) (end 5.605 1.067) (layer F.SilkS) (width 0.15))
(fp_line (start 5.465 -1.483) (end 5.465 1.483) (layer F.SilkS) (width 0.15))
(fp_line (start 5.325 -1.794) (end 5.325 1.794) (layer F.SilkS) (width 0.15))
(fp_line (start 5.185 -2.05) (end 5.185 2.05) (layer F.SilkS) (width 0.15))
(fp_line (start 5.045 -2.268) (end 5.045 2.268) (layer F.SilkS) (width 0.15))
(fp_line (start 4.905 -2.459) (end 4.905 2.459) (layer F.SilkS) (width 0.15))
(fp_line (start 4.765 -2.629) (end 4.765 2.629) (layer F.SilkS) (width 0.15))
(fp_line (start 4.625 -2.781) (end 4.625 2.781) (layer F.SilkS) (width 0.15))
(fp_line (start 4.485 0.173) (end 4.485 2.919) (layer F.SilkS) (width 0.15))
(fp_line (start 4.485 -2.919) (end 4.485 -0.173) (layer F.SilkS) (width 0.15))
(fp_line (start 4.345 0.535) (end 4.345 3.044) (layer F.SilkS) (width 0.15))
(fp_line (start 4.345 -3.044) (end 4.345 -0.535) (layer F.SilkS) (width 0.15))
(fp_line (start 4.205 0.709) (end 4.205 3.158) (layer F.SilkS) (width 0.15))
(fp_line (start 4.205 -3.158) (end 4.205 -0.709) (layer F.SilkS) (width 0.15))
(fp_line (start 4.065 0.825) (end 4.065 3.262) (layer F.SilkS) (width 0.15))
(fp_line (start 4.065 -3.262) (end 4.065 -0.825) (layer F.SilkS) (width 0.15))
(fp_line (start 3.925 0.905) (end 3.925 3.357) (layer F.SilkS) (width 0.15))
(fp_line (start 3.925 -3.357) (end 3.925 -0.905) (layer F.SilkS) (width 0.15))
(fp_line (start 3.785 0.959) (end 3.785 3.444) (layer F.SilkS) (width 0.15))
(fp_line (start 3.785 -3.444) (end 3.785 -0.959) (layer F.SilkS) (width 0.15))
(fp_line (start 3.645 0.989) (end 3.645 3.523) (layer F.SilkS) (width 0.15))
(fp_line (start 3.645 -3.523) (end 3.645 -0.989) (layer F.SilkS) (width 0.15))
(fp_line (start 3.505 1) (end 3.505 3.594) (layer F.SilkS) (width 0.15))
(fp_line (start 3.505 -3.594) (end 3.505 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 3.365 0.991) (end 3.365 3.659) (layer F.SilkS) (width 0.15))
(fp_line (start 3.365 -3.659) (end 3.365 -0.991) (layer F.SilkS) (width 0.15))
(fp_line (start 3.225 0.961) (end 3.225 3.718) (layer F.SilkS) (width 0.15))
(fp_line (start 3.225 -3.718) (end 3.225 -0.961) (layer F.SilkS) (width 0.15))
(fp_line (start 3.085 0.91) (end 3.085 3.771) (layer F.SilkS) (width 0.15))
(fp_line (start 3.085 -3.771) (end 3.085 -0.91) (layer F.SilkS) (width 0.15))
(fp_line (start 2.945 0.832) (end 2.945 3.817) (layer F.SilkS) (width 0.15))
(fp_line (start 2.945 -3.817) (end 2.945 -0.832) (layer F.SilkS) (width 0.15))
(fp_line (start 2.805 0.719) (end 2.805 3.858) (layer F.SilkS) (width 0.15))
(fp_line (start 2.805 -3.858) (end 2.805 -0.719) (layer F.SilkS) (width 0.15))
(fp_line (start 2.665 0.55) (end 2.665 3.894) (layer F.SilkS) (width 0.15))
(fp_line (start 2.665 -3.894) (end 2.665 -0.55) (layer F.SilkS) (width 0.15))
(fp_line (start 2.525 0.222) (end 2.525 3.924) (layer F.SilkS) (width 0.15))
(fp_line (start 2.525 -3.924) (end 2.525 -0.222) (layer F.SilkS) (width 0.15))
(fp_line (start 2.385 -3.949) (end 2.385 3.949) (layer F.SilkS) (width 0.15))
(fp_line (start 2.245 -3.969) (end 2.245 3.969) (layer F.SilkS) (width 0.15))
(fp_line (start 2.105 -3.984) (end 2.105 3.984) (layer F.SilkS) (width 0.15))
(fp_line (start 1.965 -3.994) (end 1.965 3.994) (layer F.SilkS) (width 0.15))
(fp_line (start 1.825 -3.999) (end 1.825 3.999) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(pad 2 thru_hole circle (at 3.5 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 25 -12V))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D8_L11.5_P3.5.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A80F)
(at 94 48.5)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59361C5D)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference C27 (at 0 -1.5) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 26 "Net-(C27-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A815)
(at 92 51.5 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59361F8D)
(attr smd)
Layout: fix silkscreen position
2017-07-27 20:14:20 +02:00
(fp_text reference C28 (at -3.47 0.45 450) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 26 "Net-(C27-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A81B)
(at 75.5 55 90)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /593775B9)
(attr smd)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(fp_text reference C29 (at 0 -1.9 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(fp_text value 10n (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 18 GNDPWR))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 27 "Net-(C29-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A821)
(at 85.95 56.5)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /593773D6)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference C30 (at -3.5 0) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10n (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 28 "Net-(C30-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Radial_D5_L11_P2.5 (layer F.Cu) (tedit 0) (tstamp 5978A827)
(at 96 42.5 270)
(descr "Radial Electrolytic Capacitor Diameter 5mm x Length 11mm, Pitch 2.5mm")
(tags "Electrolytic Capacitor")
(path /5936D506)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C31 (at 1 -4.25 540) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22u (at 1.25 3.8 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.25 0) (end 1.25 -2.8) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1.25 0) (end 1.25 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 2.5 0) (end 2.5 -0.9) (layer F.SilkS) (width 0.15))
(fp_line (start 3.705 -0.472) (end 3.705 0.472) (layer F.SilkS) (width 0.15))
(fp_line (start 3.565 -0.944) (end 3.565 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.425 -1.233) (end 3.425 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 0.44) (end 3.285 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 -1.452) (end 3.285 -0.44) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 0.628) (end 3.145 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 -1.631) (end 3.145 -0.628) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 0.745) (end 3.005 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 -1.78) (end 3.005 -0.745) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 0.823) (end 2.865 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 -1.908) (end 2.865 -0.823) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 0.871) (end 2.725 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 -2.019) (end 2.725 -0.871) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 0.896) (end 2.585 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 -2.114) (end 2.585 -0.896) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 0.898) (end 2.445 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 -2.196) (end 2.445 -0.898) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 0.879) (end 2.305 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 -2.266) (end 2.305 -0.879) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 0.835) (end 2.165 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 -2.327) (end 2.165 -0.835) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 0.764) (end 2.025 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 -2.377) (end 2.025 -0.764) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 0.657) (end 1.885 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 -2.418) (end 1.885 -0.657) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 0.49) (end 1.745 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 -2.451) (end 1.745 -0.49) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 0.095) (end 1.605 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 -2.475) (end 1.605 -0.095) (layer F.SilkS) (width 0.15))
(fp_line (start 1.465 -2.491) (end 1.465 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.325 -2.499) (end 1.325 2.499) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 29 "Net-(C31-Pad1)"))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.5.wrl
(at (xyz 0.049213 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A82D)
(at 85 43.05 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5936ED37)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C32 (at -1.55 -2.25 270) (layer B.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 29 "Net-(C31-Pad1)"))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 18 GNDPWR))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A833)
(at 101.97 56.18 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /593620C9)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C33 (at -0.03 -1.82 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 30 "Net-(C33-Pad2)"))
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A839)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(at 99.05 59.5)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59361D2F)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C34 (at 3.7 0) (layer B.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_text value 100n (at 0 -1.9) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 18 GNDPWR))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 30 "Net-(C33-Pad2)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A83F)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 79.71 44.23 90)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5936EFE5)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C35 (at -0.02 -1.96 90) (layer B.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 31 "Net-(C35-Pad2)"))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 18 GNDPWR))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Radial_D5_L11_P2.5 (layer F.Cu) (tedit 0) (tstamp 5978A845)
(at 71.5 43.5 90)
(descr "Radial Electrolytic Capacitor Diameter 5mm x Length 11mm, Pitch 2.5mm")
(tags "Electrolytic Capacitor")
(path /5936E4FB)
(fp_text reference C36 (at 1.25 -3.8 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22u (at 1.25 3.8 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.25 0) (end 1.25 -2.8) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1.25 0) (end 1.25 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 2.5 0) (end 2.5 -0.9) (layer F.SilkS) (width 0.15))
(fp_line (start 3.705 -0.472) (end 3.705 0.472) (layer F.SilkS) (width 0.15))
(fp_line (start 3.565 -0.944) (end 3.565 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.425 -1.233) (end 3.425 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 0.44) (end 3.285 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 -1.452) (end 3.285 -0.44) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 0.628) (end 3.145 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 -1.631) (end 3.145 -0.628) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 0.745) (end 3.005 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 -1.78) (end 3.005 -0.745) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 0.823) (end 2.865 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 -1.908) (end 2.865 -0.823) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 0.871) (end 2.725 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 -2.019) (end 2.725 -0.871) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 0.896) (end 2.585 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 -2.114) (end 2.585 -0.896) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 0.898) (end 2.445 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 -2.196) (end 2.445 -0.898) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 0.879) (end 2.305 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 -2.266) (end 2.305 -0.879) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 0.835) (end 2.165 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 -2.327) (end 2.165 -0.835) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 0.764) (end 2.025 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 -2.377) (end 2.025 -0.764) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 0.657) (end 1.885 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 -2.418) (end 1.885 -0.657) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 0.49) (end 1.745 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 -2.451) (end 1.745 -0.49) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 0.095) (end 1.605 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 -2.475) (end 1.605 -0.095) (layer F.SilkS) (width 0.15))
(fp_line (start 1.465 -2.491) (end 1.465 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.325 -2.499) (end 1.325 2.499) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole circle (at 2.5 0 90) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 31 "Net-(C35-Pad2)"))
(pad 1 thru_hole rect (at 0 0 90) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.5.wrl
(at (xyz 0.049213 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(module Diodes_SMD:SOD-123 (layer F.Cu) (tedit 58645DC7) (tstamp 5978A84B)
(at 32.71 54.71 90)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr SOD-123)
(tags SOD-123)
(path /5935E5FB)
(attr smd)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(fp_text reference D1 (at 0 -2 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SK15-DIO (at 0 2.1 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.25 -1) (end 1.65 -1) (layer F.SilkS) (width 0.12))
(fp_line (start -2.25 1) (end 1.65 1) (layer F.SilkS) (width 0.12))
(fp_line (start -2.35 -1.15) (end -2.35 1.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.35 1.15) (end -2.35 1.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.35 -1.15) (end 2.35 1.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.35 -1.15) (end 2.35 -1.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.4 -0.9) (end 1.4 -0.9) (layer F.Fab) (width 0.1))
(fp_line (start 1.4 -0.9) (end 1.4 0.9) (layer F.Fab) (width 0.1))
(fp_line (start 1.4 0.9) (end -1.4 0.9) (layer F.Fab) (width 0.1))
(fp_line (start -1.4 0.9) (end -1.4 -0.9) (layer F.Fab) (width 0.1))
(fp_line (start -0.75 0) (end -0.35 0) (layer F.Fab) (width 0.1))
(fp_line (start -0.35 0) (end -0.35 -0.55) (layer F.Fab) (width 0.1))
(fp_line (start -0.35 0) (end -0.35 0.55) (layer F.Fab) (width 0.1))
(fp_line (start -0.35 0) (end 0.25 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.25 -0.4) (end 0.25 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.25 0.4) (end -0.35 0) (layer F.Fab) (width 0.1))
(fp_line (start 0.25 0) (end 0.75 0) (layer F.Fab) (width 0.1))
(fp_line (start -2.25 -1) (end -2.25 1) (layer F.SilkS) (width 0.12))
(pad 2 smd rect (at 1.65 0 90) (size 0.9 1.2) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 1 Earth))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -1.65 0 90) (size 0.9 1.2) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 32 "Net-(D1-Pad1)"))
(model ${KISYS3DMOD}/Diodes_SMD.3dshapes/SOD-123.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module tht:AMPHENOL-ACJS-HHDR (layer F.Cu) (tedit 59397A20) (tstamp 5978A88B)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(at 102.15 27)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(path /593770B0)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference J4 (at 6.85 8.8) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value JACK_TRS_6PINS (at -0.5 1.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -13.8 -8) (end 10.6 -8) (layer F.SilkS) (width 0.15))
(fp_line (start -13.8 8) (end -13.8 -8) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 8) (end -13.8 8) (layer F.SilkS) (width 0.15))
(fp_line (start 14 -5.7) (end 14 5.7) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 5.7) (end 14 5.7) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 -8) (end 10.6 8) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 -5.7) (end 14 -5.7) (layer F.SilkS) (width 0.15))
(pad 4 thru_hole circle (at 6.35 5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 37 "Net-(J4-Pad4)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 6 thru_hole circle (at 0 5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 38 "Net-(J4-Pad6)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 5 thru_hole circle (at -6.35 5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 39 "Net-(J4-Pad5)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 2 thru_hole circle (at -6.35 -5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 40 "Net-(J4-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 3 thru_hole circle (at 0 -5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 41 "Net-(J4-Pad3)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 thru_hole circle (at 6.35 -5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
(net 18 GNDPWR))
)
(module "Relays_THT:Relay_DPDT_IM0(3,6,7)NS" (layer F.Cu) (tedit 55FAC2CB) (tstamp 5978A897)
(at 47.1 47 270)
(descr "IM Signal Relay, DPDT, IM0(3,6,7)NS, narrow footprint")
(tags "Relay DPDT IM-relay")
(path /59346B99)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(fp_text reference K1 (at 1.5 -1.9 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Relais-2 (at 1.95 10.25 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 4.597 -1.2065) (end -1.372 -1.2065) (layer F.SilkS) (width 0.15))
(fp_line (start -1.4 -1.2) (end -1.4 8.8) (layer F.SilkS) (width 0.15))
(fp_line (start 4.597 8.8265) (end -1.372 8.8265) (layer F.SilkS) (width 0.15))
(fp_line (start 4.6 -1.2) (end 4.6 8.8) (layer F.SilkS) (width 0.15))
(fp_line (start -1.65 -1.45) (end 4.85 -1.45) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 9.05) (end -1.65 -1.45) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 9.05) (end -1.65 9.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 -1.45) (end 4.85 9.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.565 1.016) (end 2.565 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 0.66 2.032) (end 2.565 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 0.66 1.016) (end 0.66 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 2.565 1.016) (end 0.66 1.016) (layer F.SilkS) (width 0.15))
(fp_line (start 3.2 1.524) (end 2.565 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 3.2 0.889) (end 3.2 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 0 1.524) (end 0.66 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 0 0.889) (end 0 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 2.184 1.016) (end 1.549 2.032) (layer F.SilkS) (width 0.15))
(pad 5 thru_hole circle (at 3.2 7.6 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 10 "Net-(C8-Pad1)"))
(pad 6 thru_hole circle (at 3.2 5.4 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 42 "Net-(K1-Pad6)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 7 thru_hole circle (at 3.2 3.2 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 16 /RUSB))
(pad 4 thru_hole circle (at 0 7.6 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 8 "Net-(C7-Pad1)"))
(pad 3 thru_hole circle (at 0 5.4 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 43 "Net-(K1-Pad3)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 2 thru_hole circle (at 0 3.2 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 11 /LUSB))
(pad 1 thru_hole circle (at 0 0 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 63 "Net-(K1-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 8 thru_hole circle (at 3.2 0 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 32 "Net-(D1-Pad1)"))
(model "Relays_ThroughHole.3dshapes/Relay_DPDT_IM0(3,6,7)NS.wrl"
(at (xyz 0.0625 -0.15 -0.128))
(scale (xyz 0.39 0.39 0.39))
(rotate (xyz 180 0 90))
)
)
(module "Relays_THT:Relay_DPDT_IM0(3,6,7)NS" (layer F.Cu) (tedit 55FAC2CB) (tstamp 5978A8A3)
(at 35.9 47 270)
(descr "IM Signal Relay, DPDT, IM0(3,6,7)NS, narrow footprint")
(tags "Relay DPDT IM-relay")
(path /5934743F)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(fp_text reference K2 (at 1.5 9.65 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Relais-2 (at 1.95 10.25 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 4.597 -1.2065) (end -1.372 -1.2065) (layer F.SilkS) (width 0.15))
(fp_line (start -1.4 -1.2) (end -1.4 8.8) (layer F.SilkS) (width 0.15))
(fp_line (start 4.597 8.8265) (end -1.372 8.8265) (layer F.SilkS) (width 0.15))
(fp_line (start 4.6 -1.2) (end 4.6 8.8) (layer F.SilkS) (width 0.15))
(fp_line (start -1.65 -1.45) (end 4.85 -1.45) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 9.05) (end -1.65 -1.45) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 9.05) (end -1.65 9.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 -1.45) (end 4.85 9.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.565 1.016) (end 2.565 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 0.66 2.032) (end 2.565 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 0.66 1.016) (end 0.66 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 2.565 1.016) (end 0.66 1.016) (layer F.SilkS) (width 0.15))
(fp_line (start 3.2 1.524) (end 2.565 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 3.2 0.889) (end 3.2 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 0 1.524) (end 0.66 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 0 0.889) (end 0 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 2.184 1.016) (end 1.549 2.032) (layer F.SilkS) (width 0.15))
(pad 5 thru_hole circle (at 3.2 7.6 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 36 GNDA))
(pad 6 thru_hole circle (at 3.2 5.4 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(pad 7 thru_hole circle (at 3.2 3.2 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 1 Earth))
(pad 4 thru_hole circle (at 0 7.6 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 36 GNDA))
(pad 3 thru_hole circle (at 0 5.4 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(pad 2 thru_hole circle (at 0 3.2 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 1 Earth))
(pad 1 thru_hole circle (at 0 0 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 64 "Net-(K2-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 8 thru_hole circle (at 3.2 0 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 32 "Net-(D1-Pad1)"))
(model "Relays_ThroughHole.3dshapes/Relay_DPDT_IM0(3,6,7)NS.wrl"
(at (xyz 0.0625 -0.15 -0.128))
(scale (xyz 0.39 0.39 0.39))
(rotate (xyz 180 0 90))
)
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(module Resistors_SMD:R_1812_HandSoldering (layer F.Cu) (tedit 58307D36) (tstamp 5978A8A9)
(at 23.5 38.5)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 1812, hand soldering, Panasonic (see ERJ12)")
(tags "resistor 1812")
(path /5934B57E)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference L1 (at 0 2.75) (layer F.SilkS)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(fp_text value 47u (at 0 3.175) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(fp_line (start -1.7272 -1.8796) (end 1.7272 -1.8796) (layer F.SilkS) (width 0.15))
(fp_line (start -1.7272 1.8796) (end 1.7272 1.8796) (layer F.SilkS) (width 0.15))
(fp_line (start -5.4356 2.2352) (end -5.4356 -2.2352) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.4356 2.2352) (end -5.4356 2.2352) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.4356 -2.2352) (end 5.4356 2.2352) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4356 -2.2352) (end 5.4356 -2.2352) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.25 -1.6) (end 2.25 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start 2.25 -1.6) (end 2.25 1.6) (layer F.Fab) (width 0.1))
(fp_line (start 2.25 1.6) (end -2.25 1.6) (layer F.Fab) (width 0.1))
(fp_line (start -2.25 1.6) (end -2.25 -1.6) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 3.4036 0) (size 3.5 3.5) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 2 "Net-(C1-Pad1)"))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(pad 1 smd rect (at -3.4036 0) (size 3.5 3.5) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 3 +5V))
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5978A8C1)
(at 90.86 37.62 270)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59360759)
(attr smd)
(fp_text reference L5 (at 0 1.9 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10u (at 0 -1.9 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 26 "Net-(C27-Pad1)"))
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 24 +12V))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_1210_HandSoldering (layer F.Cu) (tedit 58307C8D) (tstamp 5978A8C7)
(at 86 36.5 270)
(descr "Resistor SMD 1210, hand soldering")
(tags "resistor 1210")
(path /5936CC12)
(attr smd)
(fp_text reference L6 (at 0 -2.7 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 2.7 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1 -1.475) (end 1 -1.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.475) (end -1 1.475) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.6) (end 3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.6) (end -3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.6) (end 3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.6) (end 3.3 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.25) (end 1.6 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -1.25) (end 1.6 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 1.25) (end -1.6 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 1.25) (end -1.6 -1.25) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 2 0 270) (size 2 2.5) (layers F.Cu F.Paste F.Mask)
(net 29 "Net-(C31-Pad1)"))
(pad 1 smd rect (at -2 0 270) (size 2 2.5) (layers F.Cu F.Paste F.Mask)
(net 24 +12V))
(model Resistors_SMD.3dshapes/R_1210_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5978A8CD)
(at 98.044 55.88 90)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59360894)
(attr smd)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_text reference L7 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_text value 10u (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 25 -12V))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 30 "Net-(C33-Pad2)"))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_1210_HandSoldering (layer F.Cu) (tedit 58307C8D) (tstamp 5978A8D3)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(at 77.41 38.95 180)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 1210, hand soldering")
(tags "resistor 1210")
(path /5936CF7D)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference L8 (at -4.09 0.95 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_text value 1u (at 0 2.7 180) (layer F.Fab)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1 -1.475) (end 1 -1.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.475) (end -1 1.475) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.6) (end 3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.6) (end -3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.6) (end 3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.6) (end 3.3 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.25) (end 1.6 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -1.25) (end 1.6 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 1.25) (end -1.6 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 1.25) (end -1.6 -1.25) (layer F.Fab) (width 0.1))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 2 smd rect (at 2 0 180) (size 2 2.5) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 25 -12V))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 1 smd rect (at -2 0 180) (size 2 2.5) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 31 "Net-(C35-Pad2)"))
(model Resistors_SMD.3dshapes/R_1210_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5978A8D9)
(at 25 29.5 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5934E5F3)
(attr smd)
(fp_text reference R1 (at 0 1.9 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1k5 (at 0 -1.9 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 34 /D+))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 6 +3V3))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8DF)
(at 25 28.5)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5934E1D2)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R2 (at 0 1.75) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22 (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 44 "Net-(R2-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 34 /D+))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8E5)
(at 25 26.5 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5934E099)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R3 (at 0 1.75 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22 (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 35 /D-))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 45 "Net-(R3-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8EB)
(at 37 38 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5934FAAF)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R4 (at 5 -2.75 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 16 (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(C9-Pad1)"))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 13 "Net-(C12-Pad1)"))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8F1)
(at 39.5 24.5)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /593487DE)
(attr smd)
(fp_text reference R5 (at 0 -1.9) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1M (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 15 "Net-(C14-Pad1)"))
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 5 "Net-(C5-Pad1)"))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8F7)
(at 42 38 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5934ED7E)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R6 (at -3.25 0 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 16 (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 14 "Net-(C13-Pad2)"))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 17 "Net-(C15-Pad1)"))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8FD)
(at 94.5 58.5)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938A1C1)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference R7 (at 0 1.7) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 2k (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 46 "Net-(R7-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 47 "Net-(R11-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5978A903)
(at 94.24 56.44 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938AA58)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R8 (at 0.24 1.69 180) (layer B.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1k (at 0 -1.9 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 18 GNDPWR))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 46 "Net-(R7-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A909)
(at 98.5 48)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59389142)
(attr smd)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(fp_text reference R9 (at 0.46 -1.6) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 2k (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 48 "Net-(R10-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 49 "Net-(R12-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5978A90F)
(at 98.5 48.5)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /593893F1)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R10 (at 0 -2) (layer B.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1k (at 0 -1.9) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 48 "Net-(R10-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 18 GNDPWR))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_1206_HandSoldering (layer F.Cu) (tedit 58307C0D) (tstamp 5978A915)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 78.47 58.42)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 1206, hand soldering")
(tags "resistor 1206")
(path /5937135E)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference R11 (at -0.1 2) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 50 (at 0 2.3) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1 -1.075) (end 1 -1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.075) (end -1 1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end -3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end 3.3 -1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 2 0) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 47 "Net-(R11-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -2 0) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
(net 27 "Net-(C29-Pad1)"))
(model Resistors_SMD.3dshapes/R_1206_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_1206_HandSoldering (layer F.Cu) (tedit 58307C0D) (tstamp 5978A91B)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 86.96 58.78)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 1206, hand soldering")
(tags "resistor 1206")
(path /593721CE)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference R12 (at 0 2) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 50 (at 0 2.3) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1 -1.075) (end 1 -1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.075) (end -1 1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end -3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end 3.3 -1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 2 0) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 49 "Net-(R12-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -2 0) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
(net 28 "Net-(C30-Pad1)"))
(model Resistors_SMD.3dshapes/R_1206_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A921)
(at 90 49 90)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938E18E)
(attr smd)
Layout: fix silkscreen position
2017-07-27 20:14:20 +02:00
(fp_text reference R13 (at -4.09 -0.03 90) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 50 "Net-(R13-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A927)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(at 72.25 51.75 270)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938D7A2)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R14 (at -0.5 2 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text value 1k (at 0 1.9 270) (layer F.Fab)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 18 GNDPWR))
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 51 "Net-(R14-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A92D)
(at 74 47.5 90)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938C14D)
(attr smd)
(fp_text reference R15 (at 0 -1.9 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 52 "Net-(R15-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 51 "Net-(R14-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A933)
(at 91 44.5 270)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938BE81)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R16 (at 0.25 -1.75 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 50 "Net-(R13-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 53 "Net-(R16-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(module Resistors_SMD:R_1206_HandSoldering (layer F.Cu) (tedit 58307C0D) (tstamp 5978A939)
(at 90.75 38.5 270)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 1206, hand soldering")
(tags "resistor 1206")
(path /59377722)
(attr smd)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(fp_text reference R17 (at 0 -2.3 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(fp_text value 5 (at 0 2.3 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(fp_line (start -1 -1.075) (end 1 -1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.075) (end -1 1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end -3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end 3.3 -1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 2 0 270) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 52 "Net-(R15-Pad2)"))
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(pad 1 smd rect (at -2 0 270) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 40 "Net-(J4-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_1206_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_1206_HandSoldering (layer F.Cu) (tedit 58307C0D) (tstamp 5978A93F)
(at 98.19 37.09 180)
(descr "Resistor SMD 1206, hand soldering")
(tags "resistor 1206")
(path /59377880)
(attr smd)
fix silkscreen
2017-08-28 23:00:45 +02:00
(fp_text reference R18 (at 4.69 0.84 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 5 (at 0 2.3 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1 -1.075) (end 1 -1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.075) (end -1 1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end -3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end 3.3 -1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 2 0 180) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 53 "Net-(R16-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -2 0 180) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 41 "Net-(J4-Pad3)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_1206_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module tht:ALPS-RK09L12B0 (layer F.Cu) (tedit 5978937F) (tstamp 5978A978)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(at 105.5 48)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(path /5935E896)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference RV1 (at 1.5 -6 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "ALPS 50k" (at 4.75 -6) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 7.5 -5.35) (end -2.25 -5.35) (layer F.SilkS) (width 0.15))
(fp_line (start 12.25 4.5) (end 12.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12 4.25) (end 12.25 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 11.75 4.5) (end 12 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 11.5 4.25) (end 11.75 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 11.25 4.5) (end 11.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 11 4.25) (end 11.25 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 10.75 4.5) (end 11 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10.5 4.25) (end 10.75 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 10.25 4.5) (end 10.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10 4.25) (end 10.25 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.75 4.5) (end 10 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 9.5 4.25) (end 9.75 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.25 4.5) (end 9.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 9 4.25) (end 9.25 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 8.75 4.5) (end 9 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 8.5 4.25) (end 8.75 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 8.25 4.5) (end 8.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 8 4.25) (end 8.25 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 7.75 4.5) (end 8 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 7.5 4.25) (end 7.75 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 7.75 -4.5) (end 7.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.25 -4.5) (end 12.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12 -4.25) (end 12.25 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 11.75 -4.5) (end 12 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 11.5 -4.25) (end 11.75 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 11.25 -4.5) (end 11.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 11 -4.25) (end 11.25 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 10.75 -4.5) (end 11 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10.5 -4.25) (end 10.75 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 10.25 -4.5) (end 10.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10 -4.25) (end 10.25 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.75 -4.5) (end 10 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 9.5 -4.25) (end 9.75 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.25 -4.5) (end 9.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 9 -4.25) (end 9.25 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 8.75 -4.5) (end 9 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 8.5 -4.25) (end 8.75 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 8.25 -4.5) (end 8.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 8 -4.25) (end 8.25 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 8.25 -4.5) (end 8 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 7.75 -4.5) (end 8 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.5 -4.25) (end 12.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 7.5 -5.35) (end 7.5 5.35) (layer F.SilkS) (width 0.15))
(fp_line (start 7.5 5.35) (end -2.25 5.35) (layer F.SilkS) (width 0.15))
(pad 12 thru_hole circle (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 67 "Net-(R24-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 11 thru_hole circle (at 0 2.5) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(pad 13 thru_hole circle (at 0 -2.5) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 42 "Net-(K1-Pad6)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 21 thru_hole circle (at 2.5 2.5) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(pad 22 thru_hole circle (at 2.5 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 65 "Net-(R23-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 23 thru_hole circle (at 2.5 -2.5) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 43 "Net-(K1-Pad3)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 30 thru_hole rect (at -3.3 -4.75) (size 1.8 2.5) (drill oval 1.1 1.8) (layers *.Cu *.Mask))
(pad 30 thru_hole rect (at -3.3 4.75) (size 1.8 2.5) (drill oval 1.1 1.8) (layers *.Cu *.Mask))
)
(module Housings_SSOP:SSOP-28_5.3x10.2mm_Pitch0.65mm (layer F.Cu) (tedit 54130A77) (tstamp 5978A9A7)
(at 39.5 31)
(descr "28-Lead Plastic Shrink Small Outline (SS)-5.30 mm Body [SSOP] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SSOP 0.65")
(path /59348397)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference U1 (at 4.5 -6.25) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PCM2704 (at 0 6.25) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.875 -4.75) (end -4.475 -4.75) (layer F.SilkS) (width 0.15))
(fp_line (start -2.875 5.325) (end 2.875 5.325) (layer F.SilkS) (width 0.15))
(fp_line (start -2.875 -5.325) (end 2.875 -5.325) (layer F.SilkS) (width 0.15))
(fp_line (start -2.875 5.325) (end -2.875 4.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2.875 5.325) (end 2.875 4.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2.875 -5.325) (end 2.875 -4.675) (layer F.SilkS) (width 0.15))
(fp_line (start -2.875 -5.325) (end -2.875 -4.75) (layer F.SilkS) (width 0.15))
(fp_line (start -4.75 5.5) (end 4.75 5.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.75 -5.5) (end 4.75 -5.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.75 -5.5) (end 4.75 5.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.75 -5.5) (end -4.75 5.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.65 -4.1) (end -1.65 -5.1) (layer F.Fab) (width 0.15))
(fp_line (start -2.65 5.1) (end -2.65 -4.1) (layer F.Fab) (width 0.15))
(fp_line (start 2.65 5.1) (end -2.65 5.1) (layer F.Fab) (width 0.15))
(fp_line (start 2.65 -5.1) (end 2.65 5.1) (layer F.Fab) (width 0.15))
(fp_line (start -1.65 -5.1) (end 2.65 -5.1) (layer F.Fab) (width 0.15))
(pad 28 smd rect (at 3.6 -4.225) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 15 "Net-(C14-Pad1)"))
(pad 27 smd rect (at 3.6 -3.575) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 60 "Net-(TP4-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 26 smd rect (at 3.6 -2.925) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 25 smd rect (at 3.6 -2.275) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 24 smd rect (at 3.6 -1.625) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 54 "Net-(TP1-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 23 smd rect (at 3.6 -0.975) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 55 "Net-(TP2-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 22 smd rect (at 3.6 -0.325) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 56 "Net-(TP3-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 21 smd rect (at 3.6 0.325) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 20 smd rect (at 3.6 0.975) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 23 "Net-(C22-Pad2)"))
(pad 19 smd rect (at 3.6 1.625) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 18 smd rect (at 3.6 2.275) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 22 "Net-(C21-Pad1)"))
(pad 17 smd rect (at 3.6 2.925) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 16 smd rect (at 3.6 3.575) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 21 "Net-(C18-Pad2)"))
(pad 15 smd rect (at 3.6 4.225) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 17 "Net-(C15-Pad1)"))
(pad 14 smd rect (at -3.6 4.225) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(C9-Pad1)"))
(pad 13 smd rect (at -3.6 3.575) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 4 "Net-(C4-Pad2)"))
(pad 12 smd rect (at -3.6 2.925) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 11 smd rect (at -3.6 2.275) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 10 smd rect (at -3.6 1.625) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 2 "Net-(C1-Pad1)"))
(pad 9 smd rect (at -3.6 0.975) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 44 "Net-(R2-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 8 smd rect (at -3.6 0.325) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 45 "Net-(R3-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 7 smd rect (at -3.6 -0.325) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 6 smd rect (at -3.6 -0.975) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 5 smd rect (at -3.6 -1.625) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 57 "Net-(U1-Pad5)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 4 smd rect (at -3.6 -2.275) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 3 smd rect (at -3.6 -2.925) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 58 "Net-(U1-Pad3)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 2 smd rect (at -3.6 -3.575) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 59 "Net-(U1-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -3.6 -4.225) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 5 "Net-(C5-Pad1)"))
(model Housings_SSOP.3dshapes/SSOP-28_5.3x10.2mm_Pitch0.65mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm (layer F.Cu) (tedit 54130A77) (tstamp 5978A9C0)
(at 96 53.5 90)
(descr "8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5935FD14)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference U3 (at 0 3.6 90) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value OPA2134 (at 0 3.5 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.075 -2.525) (end -3.475 -2.525) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 2.575) (end 2.075 2.575) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 -2.575) (end 2.075 -2.575) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 2.575) (end -2.075 2.43) (layer F.SilkS) (width 0.15))
(fp_line (start 2.075 2.575) (end 2.075 2.43) (layer F.SilkS) (width 0.15))
(fp_line (start 2.075 -2.575) (end 2.075 -2.43) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 -2.575) (end -2.075 -2.525) (layer F.SilkS) (width 0.15))
(fp_line (start -3.75 2.75) (end 3.75 2.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.75 -2.75) (end 3.75 -2.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.75 -2.75) (end 3.75 2.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.75 -2.75) (end -3.75 2.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 -1.45) (end -0.95 -2.45) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 2.45) (end -1.95 -1.45) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 2.45) (end -1.95 2.45) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 -2.45) (end 1.95 2.45) (layer F.Fab) (width 0.15))
(fp_line (start -0.95 -2.45) (end 1.95 -2.45) (layer F.Fab) (width 0.15))
(pad 8 smd rect (at 2.7 -1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
(net 26 "Net-(C27-Pad1)"))
(pad 7 smd rect (at 2.7 -0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 49 "Net-(R12-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 6 smd rect (at 2.7 0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 48 "Net-(R10-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 5 smd rect (at 2.7 1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 68 "Net-(R24-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 4 smd rect (at -2.7 1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
(net 30 "Net-(C33-Pad2)"))
(pad 3 smd rect (at -2.7 0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 66 "Net-(R23-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 2 smd rect (at -2.7 -0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 46 "Net-(R7-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -2.7 -1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 47 "Net-(R11-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Housings_SOIC.3dshapes/SOIC-8_3.9x4.9mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module smd:SOIC-20W_ThermalPad (layer F.Cu) (tedit 59762C02) (tstamp 5978A9E9)
(at 82.8 47.555)
(descr "20-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5936C2F8)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference U4 (at 0 7.445) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TPA6120 (at 0 7.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.875 -6.325) (end -5.675 -6.325) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 6.575) (end 3.875 6.575) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -6.575) (end 3.875 -6.575) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 6.575) (end -3.875 6.24) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 6.575) (end 3.875 6.24) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 -6.575) (end 3.875 -6.24) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -6.575) (end -3.875 -6.325) (layer F.SilkS) (width 0.15))
(fp_line (start -5.95 6.75) (end 5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 -6.75) (end 5.95 -6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.95 -6.75) (end 5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 -6.75) (end -5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.75 -5.4) (end -2.75 -6.4) (layer F.Fab) (width 0.15))
(fp_line (start -3.75 6.4) (end -3.75 -5.4) (layer F.Fab) (width 0.15))
(fp_line (start 3.75 6.4) (end -3.75 6.4) (layer F.Fab) (width 0.15))
(fp_line (start 3.75 -6.4) (end 3.75 6.4) (layer F.Fab) (width 0.15))
(fp_line (start -2.75 -6.4) (end 3.75 -6.4) (layer F.Fab) (width 0.15))
(pad 20 smd rect (at 4.7 -5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 31 "Net-(C35-Pad2)"))
(pad 19 smd rect (at 4.7 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 53 "Net-(R16-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 18 smd rect (at 4.7 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 29 "Net-(C31-Pad1)"))
(pad 17 smd rect (at 4.7 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 28 "Net-(C30-Pad1)"))
(pad 16 smd rect (at 4.7 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 50 "Net-(R13-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 15 smd rect (at 4.7 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at 4.7 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at 4.7 3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at 4.7 4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at 4.7 5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at -4.7 5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at -4.7 4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at -4.7 3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at -4.7 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at -4.7 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at -4.7 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 51 "Net-(R14-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 4 smd rect (at -4.7 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 27 "Net-(C29-Pad1)"))
(pad 3 smd rect (at -4.7 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 29 "Net-(C31-Pad1)"))
(pad 2 smd rect (at -4.7 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 52 "Net-(R15-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -4.7 -5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 31 "Net-(C35-Pad2)"))
(pad 21 smd rect (at 0 0) (size 3 4) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(model Housings_SOIC.3dshapes/SOIC-20_7.5x12.8mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Crystals:Crystal_HC49-SD_SMD (layer F.Cu) (tedit 0) (tstamp 5978A9EF)
(at 39.5 21)
(descr "Crystal Quarz HC49-SD SMD")
(tags "Crystal Quarz HC49-SD SMD")
(path /59348602)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference Y1 (at -0.05 -1) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 12MHz (at 2.54 5.08) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -5.84962 -2.49936) (end -5.84962 -1.651) (layer F.SilkS) (width 0.15))
(fp_line (start -5.84962 2.49936) (end -5.84962 1.651) (layer F.SilkS) (width 0.15))
(fp_line (start 5.84962 -2.49936) (end 5.84962 -1.651) (layer F.SilkS) (width 0.15))
(fp_line (start 5.84962 2.49936) (end 5.84962 1.651) (layer F.SilkS) (width 0.15))
(fp_line (start 5.84962 -2.49936) (end -5.84962 -2.49936) (layer F.SilkS) (width 0.15))
(fp_line (start -5.84962 2.49936) (end 5.84962 2.49936) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 0) (end 0.14986 0.0508) (layer F.Adhes) (width 0.381))
(fp_circle (center 0 0) (end 0.50038 0) (layer F.Adhes) (width 0.381))
(fp_circle (center 0 0) (end 0.8509 0) (layer F.Adhes) (width 0.381))
(pad 2 smd rect (at 4.84886 0) (size 5.6007 2.10058) (layers F.Cu F.Paste F.Mask)
(net 15 "Net-(C14-Pad1)"))
(pad 1 smd rect (at -4.84886 0) (size 5.6007 2.10058) (layers F.Cu F.Paste F.Mask)
(net 5 "Net-(C5-Pad1)"))
)
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 5978B3F5)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 50.5 25)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5976273D)
(fp_text reference TP1 (at 0 -2.39) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 54 "Net-(TP1-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 5978B3F9)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 50.5 30)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /59762630)
(fp_text reference TP2 (at 0 -2.39) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 55 "Net-(TP2-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 5978B3FD)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 50.5 35)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /597624B7)
(fp_text reference TP3 (at 0 -2.39) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 56 "Net-(TP3-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 597A1D40)
(at 50.5 20)
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /597A3040)
(fp_text reference TP4 (at 0 -2.39) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 60 "Net-(TP4-Pad1)"))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
Layout: Audio-in jack: plated mounting holes => unplated
2017-07-27 20:08:06 +02:00
(module tht:Lumberg-1503 (layer F.Cu) (tedit 597A2BAE) (tstamp 5978A873)
(at 20.75 48.5 180)
(path /59763E9A)
(fp_text reference J2 (at 0.88 -4.46 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Jack_3.5mm_3pin (at 0 4.75 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 9.75 2.5) (end 9.75 0) (layer F.SilkS) (width 0.15))
(fp_line (start -0.75 3) (end -2.5 3) (layer F.SilkS) (width 0.15))
(fp_line (start -0.75 3) (end -0.5 3) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 3) (end 1 3) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -3) (end 2.5 -3) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -3) (end -2.5 -3) (layer F.SilkS) (width 0.15))
(fp_line (start -4.25 0.25) (end -4.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -4.25 0.25) (end -4.25 -1.25) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 -3) (end 5 -3) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 0.75) (end 7.25 -3) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 3) (end 5 3) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 3) (end 7.25 0.75) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 2.5) (end 9.75 2.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.75 0) (end 9.75 -2.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.75 -2.5) (end 7.25 -2.5) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole rect (at 3.75 -3 180) (size 2 2) (drill oval 1.3 1) (layers *.Cu *.Mask)
(net 7 "Net-(C7-Pad2)"))
(pad 2 thru_hole rect (at 3.75 3 180) (size 2 2) (drill oval 1.3 1) (layers *.Cu *.Mask)
(net 7 "Net-(C7-Pad2)"))
(pad 1 thru_hole rect (at -3.75 -2.2 180) (size 2 1.5) (drill oval 1.3 0.8) (layers *.Cu *.Mask)
(net 36 GNDA))
(pad 3 thru_hole rect (at -3.75 2.2 180) (size 2 1.5) (drill oval 1.3 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(C8-Pad2)"))
(pad "" np_thru_hole circle (at 0.25 -2.5 180) (size 1.05 1.05) (drill 1.05) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0.25 2.5 180) (size 1.05 1.05) (drill 1.05) (layers *.Cu *.Mask))
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 597B6AB6)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 74 19.5)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /597BF3DD)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C37 (at 0 -1.75) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 61 "Net-(C37-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 597B6ABC)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 71.85 31.62)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /597BF53A)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C38 (at 0.65 -1.62) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(fp_text value 1u (at 0 1.9) (layer F.Fab)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(net 18 GNDPWR))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 62 "Net-(C38-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module TO_SOT_Packages_THT:TO-92_Molded_Wide_Oval (layer F.Cu) (tedit 58610977) (tstamp 597B6AC3)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 70.17 24.5)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(descr "TO-92 leads molded, wide, oval pads, drill 0.8mm (see NXP sot054_po.pdf)")
(tags "to-92 sc-43 sc-43a sot54 PA33 transistor")
(path /597BB5E7)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference Q1 (at 2.58 0) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_NPN_CBE (at 2.54 3.048) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.35 2.2) (end 6.35 -3.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 -3.8) (end 6.35 -3.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 2.2) (end 6.35 2.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 2.2) (end -1.25 -3.8) (layer F.CrtYd) (width 0.05))
(fp_arc (start 2.54 0) (end 4.34 1.85) (angle -20) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 2.54 -2.48) (angle -135) (layer F.Fab) (width 0.1))
(fp_arc (start 2.54 0) (end 2.54 -2.48) (angle 135) (layer F.Fab) (width 0.1))
(fp_arc (start 2.54 0) (end 2.54 -2.6) (angle 65) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 2.54 -2.6) (angle -65) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 0.74 1.85) (angle 20) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 1.75) (end 4.3 1.75) (layer F.Fab) (width 0.1))
(fp_line (start 0.74 1.85) (end 4.34 1.85) (layer F.SilkS) (width 0.12))
(pad 3 thru_hole oval (at 5.08 0 90) (size 1.50114 1.99898) (drill 0.8) (layers *.Cu *.Mask)
(net 24 +12V))
(pad 1 thru_hole rect (at 0 0 90) (size 1.50114 1.99898) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(C16-Pad1)"))
(pad 2 thru_hole oval (at 2.54 -2.54 90) (size 1.99898 1.50114) (drill 0.8) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 61 "Net-(C37-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(model TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Wide_Oval.wrl
(at (xyz 0.1 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 -90))
)
)
(module TO_SOT_Packages_THT:TO-92_Molded_Wide_Oval (layer F.Cu) (tedit 58610977) (tstamp 597B6ACA)
(at 62.05 36.97)
(descr "TO-92 leads molded, wide, oval pads, drill 0.8mm (see NXP sot054_po.pdf)")
(tags "to-92 sc-43 sc-43a sot54 PA33 transistor")
(path /597BCDB0)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference Q2 (at 2.45 0.03) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_CBE (at 2.54 3.048) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.35 2.2) (end 6.35 -3.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 -3.8) (end 6.35 -3.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 2.2) (end 6.35 2.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 2.2) (end -1.25 -3.8) (layer F.CrtYd) (width 0.05))
(fp_arc (start 2.54 0) (end 4.34 1.85) (angle -20) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 2.54 -2.48) (angle -135) (layer F.Fab) (width 0.1))
(fp_arc (start 2.54 0) (end 2.54 -2.48) (angle 135) (layer F.Fab) (width 0.1))
(fp_arc (start 2.54 0) (end 2.54 -2.6) (angle 65) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 2.54 -2.6) (angle -65) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 0.74 1.85) (angle 20) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 1.75) (end 4.3 1.75) (layer F.Fab) (width 0.1))
(fp_line (start 0.74 1.85) (end 4.34 1.85) (layer F.SilkS) (width 0.12))
(pad 3 thru_hole oval (at 5.08 0 90) (size 1.50114 1.99898) (drill 0.8) (layers *.Cu *.Mask)
(net 25 -12V))
(pad 1 thru_hole rect (at 0 0 90) (size 1.50114 1.99898) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C17-Pad2)"))
(pad 2 thru_hole oval (at 2.54 -2.54 90) (size 1.99898 1.50114) (drill 0.8) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 62 "Net-(C38-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(model TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Wide_Oval.wrl
(at (xyz 0.1 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 -90))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 597B6AD0)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 68.25 19.5)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /597BC448)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R19 (at 0 -1.75) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 61 "Net-(C37-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 19 "Net-(C16-Pad1)"))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 597B6AD6)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 68.75 30.5 90)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /597BE8B7)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R20 (at 1.25 1.5 90) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
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2017-07-28 19:00:41 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 59918DD0)
(at 85 29.75 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59919857)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C39 (at -3.5 0 180) (layer F.SilkS)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 24 +12V))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 59918DD6)
(at 71.25 35.25 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5991A29D)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C40 (at 3 0.25 540) (layer F.SilkS)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 25 -12V))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 59918DDC)
(at 77.5 21 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59919D29)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C41 (at 1.75 2 90) (layer F.SilkS)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 24 +12V))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 59918DE2)
(at 69.5 35.25 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5991A2A3)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C42 (at -1 1.75 270) (layer F.SilkS)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 25 -12V))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 59918DE8)
(at 85 31.5 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59919E53)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C43 (at -3.5 0 180) (layer F.SilkS)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 18 GNDPWR))
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 24 +12V))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 59918DEE)
(at 98.5 52.75 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5991A2A9)
(attr smd)
(fp_text reference C44 (at 0 1.9 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 25 -12V))
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 18 GNDPWR))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5991AFDC)
(at 43.5 42 90)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5991F1EB)
(attr smd)
(fp_text reference R21 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10 (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 63 "Net-(K1-Pad1)"))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5991AFE2)
(at 35.5 43 90)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5991F691)
(attr smd)
(fp_text reference R22 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10 (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 64 "Net-(K2-Pad1)"))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add balance poti
2017-08-28 22:59:34 +02:00
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 59A483D6)
(at 108.4 53.75)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59A4CCD3)
(attr smd)
(fp_text reference R23 (at 0 1.9) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 330 (at 0 -1.9) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 65 "Net-(R23-Pad2)"))
add balance poti
2017-08-28 22:59:34 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 66 "Net-(R23-Pad1)"))
add balance poti
2017-08-28 22:59:34 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 59A483DC)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(at 101.75 49.75)
add balance poti
2017-08-28 22:59:34 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59A4D380)
(attr smd)
(fp_text reference R24 (at 0 -1.9) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 330 (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 67 "Net-(R24-Pad2)"))
add balance poti
2017-08-28 22:59:34 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 68 "Net-(R24-Pad1)"))
add balance poti
2017-08-28 22:59:34 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Potentiometers:Potentiometer_Bourns_3296Y_3-8Zoll_Angular_ScrewUp (layer F.Cu) (tedit 54130BC5) (tstamp 59A483E3)
(at 109.08 37.5 90)
(descr "3296, 3/8, Square, Trimpot, Trimming, Potentiometer, Bourns")
(tags "3296, 3/8, Square, Trimpot, Trimming, Potentiometer, Bourns")
(path /59A4C01D)
fix silkscreen
2017-08-28 23:00:45 +02:00
(fp_text reference RV2 (at 1.25 -2.58 180) (layer F.SilkS)
add balance poti
2017-08-28 22:59:34 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 5.08 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.27 2.286) (end -2.54 2.286) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 2.286) (end -1.27 2.286) (layer F.SilkS) (width 0.15))
(fp_line (start -3.81 -7.366) (end 1.27 -7.366) (layer F.SilkS) (width 0.15))
(fp_line (start -3.81 2.286) (end -3.81 -7.366) (layer F.SilkS) (width 0.15))
(fp_line (start -2.54 2.286) (end -3.81 2.286) (layer F.SilkS) (width 0.15))
(fp_line (start -1.8415 1.3462) (end -1.7526 1.1684) (layer F.SilkS) (width 0.15))
(fp_line (start -2.0955 1.6891) (end -1.8415 1.3462) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5019 1.7907) (end -2.0955 1.6891) (layer F.SilkS) (width 0.15))
(fp_line (start -2.8194 1.7399) (end -2.5019 1.7907) (layer F.SilkS) (width 0.15))
(fp_line (start -3.1115 1.5621) (end -2.8194 1.7399) (layer F.SilkS) (width 0.15))
(fp_line (start -3.3147 1.2065) (end -3.1115 1.5621) (layer F.SilkS) (width 0.15))
(fp_line (start -3.302 0.762) (end -3.3147 1.2065) (layer F.SilkS) (width 0.15))
(fp_line (start -3.0861 0.4445) (end -3.302 0.762) (layer F.SilkS) (width 0.15))
(fp_line (start -2.8067 0.2667) (end -3.0861 0.4445) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5527 0.2286) (end -2.8067 0.2667) (layer F.SilkS) (width 0.15))
(fp_line (start -3.302 1.016) (end -2.032 1.016) (layer F.SilkS) (width 0.15))
(fp_line (start 0.635 -7.366) (end 0.635 -6.35) (layer F.SilkS) (width 0.15))
(fp_line (start 0.635 -3.81) (end 0.635 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 0.635 1.27) (end 0.635 2.286) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at 0 0 90) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 66 "Net-(R23-Pad1)"))
add balance poti
2017-08-28 22:59:34 +02:00
(pad 3 thru_hole circle (at 0 -5.08 90) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(net 68 "Net-(R24-Pad1)"))
add balance poti
2017-08-28 22:59:34 +02:00
(pad 2 thru_hole circle (at -2.54 -2.54 90) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(model Potentiometers.3dshapes/Potentiometer_Bourns_3296Y_3-8Zoll_Angular_ScrewUp.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 59B450DD)
(at 38.5 56.5)
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /59B48619)
(fp_text reference TP5 (at -0.5 -2.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 32 "Net-(D1-Pad1)"))
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 59B450E2)
(at 41.04 56.5)
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /59B47D65)
(fp_text reference TP6 (at 0.46 -2.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 3 +5V))
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(module tht:SIL7-reduced (layer F.Cu) (tedit 59B578F8) (tstamp 5978A9B4)
(at 54.5 38 90)
(path /5930537C)
(fp_text reference U2 (at -1.27 -3.81 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SIM2-XXXXD (at 3.81 -5.08 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 10.8 -1.4) (end 10.8 5.7) (layer F.SilkS) (width 0.15))
(fp_line (start -8.7 -1.4) (end 10.8 -1.4) (layer F.SilkS) (width 0.15))
(fp_line (start -8.7 5.7) (end 10.8 5.7) (layer F.SilkS) (width 0.15))
(fp_line (start -8.7 5.7) (end -8.7 -1.4) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at -6.35 0 90) (size 1.4 1.4) (drill 0.6) (layers *.Cu *.Mask)
(net 3 +5V))
(pad 2 thru_hole circle (at -3.81 0 90) (size 1.4 1.4) (drill 0.6) (layers *.Cu *.Mask)
(net 1 Earth))
(pad 4 thru_hole circle (at 1.27 0 90) (size 1.4 1.4) (drill 0.6) (layers *.Cu *.Mask)
(net 20 "Net-(C17-Pad2)"))
(pad 5 thru_hole circle (at 3.81 0 90) (size 1.4 1.4) (drill 0.6) (layers *.Cu *.Mask)
(net 18 GNDPWR))
(pad 6 thru_hole circle (at 6.35 0 90) (size 1.4 1.4) (drill 0.6) (layers *.Cu *.Mask)
(net 19 "Net-(C16-Pad1)"))
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(gr_text "High Fidelitity Headphone Amplifier\nMario Hüttel Aug. 2017" (at 73.25 18.25) (layer B.Mask)
(effects (font (size 1 1) (thickness 0.1875)) (justify mirror))
)
(gr_line (start 13 63.5) (end 13 13.5) (layer Edge.Cuts) (width 0.15))
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(gr_line (start 113 63.5) (end 13 63.5) (layer Edge.Cuts) (width 0.15))
(gr_line (start 113 13.5) (end 113 63.5) (layer Edge.Cuts) (width 0.15))
(gr_line (start 13 13.5) (end 113 13.5) (layer Edge.Cuts) (width 0.15))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(segment (start 56.5 42.1) (end 54.79 42.1) (width 0.8) (layer B.Cu) (net 1))
(segment (start 54.79 42.1) (end 54.5 41.81) (width 0.8) (layer B.Cu) (net 1))
(segment (start 48.89 42.11) (end 49.19 41.81) (width 0.4) (layer B.Cu) (net 1))
(segment (start 49.19 41.81) (end 54.5 41.81) (width 0.4) (layer B.Cu) (net 1))
(segment (start 54.5 41.81) (end 58.5 41.81) (width 0.4) (layer F.Cu) (net 1))
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(segment (start 61.775 50) (end 61.75 49.975) (width 0.6) (layer F.Cu) (net 1))
(segment (start 61.75 49.975) (end 61.75 43.25) (width 0.6) (layer F.Cu) (net 1))
(segment (start 61.75 43.25) (end 60.31 41.81) (width 0.6) (layer F.Cu) (net 1))
(segment (start 60.31 41.81) (end 58.5 41.81) (width 0.6) (layer F.Cu) (net 1))
(segment (start 22.5 34.5) (end 20.25 34.5) (width 0.4) (layer F.Cu) (net 1))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 14.749999 30.749999) (end 14.5 30.5) (width 0.25) (layer F.Cu) (net 1))
(segment (start 14.85116 30.85116) (end 14.749999 30.749999) (width 0.25) (layer F.Cu) (net 1))
(segment (start 14.85116 32.95008) (end 14.85116 30.85116) (width 0.25) (layer F.Cu) (net 1))
(segment (start 14.749999 30.749999) (end 14.5 30.5) (width 0.25) (layer B.Cu) (net 1))
(segment (start 15.609999 31.609999) (end 14.749999 30.749999) (width 0.25) (layer B.Cu) (net 1))
(segment (start 18.720001 31.609999) (end 15.609999 31.609999) (width 0.25) (layer B.Cu) (net 1))
(via (at 14.5 30.5) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 17.396443 24.25) (end 17.749996 24.25) (width 0.25) (layer B.Cu) (net 1))
(segment (start 16.750004 24.25) (end 17.396443 24.25) (width 0.25) (layer B.Cu) (net 1))
(segment (start 14.75 26.250004) (end 16.750004 24.25) (width 0.25) (layer B.Cu) (net 1))
(segment (start 20.35026 24.04992) (end 17.950076 24.04992) (width 0.25) (layer F.Cu) (net 1))
(segment (start 17.950076 24.04992) (end 17.749996 24.25) (width 0.25) (layer F.Cu) (net 1))
(via (at 17.749996 24.25) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 14.85116 26.148844) (end 14.75 26.250004) (width 0.25) (layer F.Cu) (net 1))
(segment (start 14.85116 24.04992) (end 14.85116 26.148844) (width 0.25) (layer F.Cu) (net 1))
(via (at 14.75 26.250004) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 20.35026 32.95008) (end 20.35026 31.60026) (width 0.4) (layer B.Cu) (net 1))
(segment (start 20.35026 31.60026) (end 20 31.25) (width 0.4) (layer B.Cu) (net 1))
(segment (start 18.720001 31.609999) (end 18.890001 31.609999) (width 0.4) (layer B.Cu) (net 1))
(segment (start 18.890001 31.609999) (end 19.25 31.25) (width 0.4) (layer B.Cu) (net 1))
(segment (start 20 31.25) (end 19.25 31.25) (width 0.8) (layer F.Cu) (net 1))
(via (at 19.25 31.25) (size 0.7) (drill 0.4) (layers F.Cu B.Cu) (net 1))
(segment (start 20.75 31.25) (end 21.5 31.25) (width 0.8) (layer F.Cu) (net 1))
(via (at 21.5 31.25) (size 0.7) (drill 0.4) (layers F.Cu B.Cu) (net 1))
(via (at 20.75 31.25) (size 0.7) (drill 0.4) (layers F.Cu B.Cu) (net 1))
(segment (start 20.44932 31.25) (end 20.75 31.25) (width 0.8) (layer F.Cu) (net 1))
(segment (start 20.44932 31.25) (end 20.44932 32.85102) (width 0.4) (layer F.Cu) (net 1))
(segment (start 20.44932 31.25) (end 20 31.25) (width 0.8) (layer F.Cu) (net 1))
(segment (start 20.44932 30.1002) (end 20.44932 31.25) (width 0.4) (layer F.Cu) (net 1))
(via (at 20 31.25) (size 0.7) (drill 0.4) (layers F.Cu B.Cu) (net 1))
(segment (start 20.44932 32.85102) (end 20.35026 32.95008) (width 0.4) (layer F.Cu) (net 1))
(segment (start 37.96 33.12) (end 37.710001 32.870001) (width 0.4) (layer B.Cu) (net 1))
(segment (start 37.710001 32.870001) (end 37.630001 32.870001) (width 0.4) (layer B.Cu) (net 1))
(segment (start 37.630001 32.870001) (end 37.4 32.64) (width 0.4) (layer B.Cu) (net 1))
(segment (start 38.55 34.5) (end 38.55 33.24) (width 0.4) (layer B.Cu) (net 1))
(segment (start 38.55 33.24) (end 38.43 33.12) (width 0.4) (layer B.Cu) (net 1))
(segment (start 38.43 33.12) (end 37.96 33.12) (width 0.4) (layer B.Cu) (net 1))
(segment (start 37.4 32.64) (end 37.4 30.58) (width 0.25) (layer B.Cu) (net 1))
(segment (start 35.75 32.64) (end 36.525 32.64) (width 0.4) (layer B.Cu) (net 1))
(segment (start 36.525 32.64) (end 37.4 32.64) (width 0.4) (layer B.Cu) (net 1))
(segment (start 37.990001 29.989999) (end 38.24 29.74) (width 0.25) (layer B.Cu) (net 1))
(segment (start 37.4 30.58) (end 37.990001 29.989999) (width 0.25) (layer B.Cu) (net 1))
(segment (start 38.489999 29.490001) (end 38.24 29.74) (width 0.25) (layer B.Cu) (net 1))
(segment (start 39.26 28.72) (end 38.489999 29.490001) (width 0.25) (layer B.Cu) (net 1))
(segment (start 37.955 30.025) (end 37.990001 29.989999) (width 0.25) (layer F.Cu) (net 1))
(segment (start 35.9 30.025) (end 37.955 30.025) (width 0.25) (layer F.Cu) (net 1))
(segment (start 37.990001 29.989999) (end 38.24 29.74) (width 0.25) (layer F.Cu) (net 1))
(segment (start 39.26 18.54) (end 39.26 28.72) (width 0.25) (layer B.Cu) (net 1))
(via (at 38.24 29.74) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 32.7 50.2) (end 32.7 53.05) (width 0.4) (layer F.Cu) (net 1))
(segment (start 32.7 53.05) (end 32.71 53.06) (width 0.4) (layer F.Cu) (net 1))
(segment (start 37.61 38.27) (end 35.5 38.27) (width 1.5) (layer B.Cu) (net 1))
(segment (start 35.5 41.9) (end 35.5 38.27) (width 0.4) (layer B.Cu) (net 1))
(segment (start 35.5 38.27) (end 28.58 38.27) (width 1.5) (layer B.Cu) (net 1))
(segment (start 44.43 37.65) (end 43.5 37.65) (width 1.5) (layer B.Cu) (net 1))
(segment (start 43.5 37.65) (end 38.23 37.65) (width 1.5) (layer B.Cu) (net 1))
(segment (start 43.5 40.9) (end 43.5 37.65) (width 0.4) (layer B.Cu) (net 1))
(segment (start 48.89 42.11) (end 44.43 37.65) (width 0.4) (layer B.Cu) (net 1))
(segment (start 35.9 33.925) (end 33.575 33.925) (width 0.4) (layer F.Cu) (net 1))
(segment (start 33.575 33.925) (end 33.5 33.85) (width 0.4) (layer F.Cu) (net 1))
(via (at 33.5 33.85) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 33.5 33.5) (end 33.5 33.85) (width 0.4) (layer F.Cu) (net 1))
(segment (start 34.4 33.5) (end 33.5 33.5) (width 0.4) (layer F.Cu) (net 1))
(segment (start 35.9 33.275) (end 34.625 33.275) (width 0.4) (layer F.Cu) (net 1))
(segment (start 34.625 33.275) (end 34.4 33.5) (width 0.4) (layer F.Cu) (net 1))
(segment (start 20.35026 35.62026) (end 20.35026 34.5) (width 1.5) (layer B.Cu) (net 1))
(segment (start 20.35026 34.5) (end 20.35026 32.95008) (width 1.5) (layer B.Cu) (net 1))
(segment (start 22.5 34.5) (end 20.35026 34.5) (width 0.6) (layer B.Cu) (net 1))
(segment (start 22.5 34.5) (end 24.5 34.5) (width 0.6) (layer B.Cu) (net 1))
(segment (start 24.55 35.5) (end 24.55 34.55) (width 0.6) (layer F.Cu) (net 1))
(segment (start 24.55 34.55) (end 24.5 34.5) (width 0.6) (layer F.Cu) (net 1))
(via (at 24.5 34.5) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 22.45 35.5) (end 22.45 34.55) (width 0.6) (layer F.Cu) (net 1))
(segment (start 22.45 34.55) (end 22.5 34.5) (width 0.6) (layer F.Cu) (net 1))
(via (at 22.5 34.5) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 31.98 38.22) (end 31.060762 38.22) (width 0.4) (layer B.Cu) (net 1))
(segment (start 31.060762 38.22) (end 31.010762 38.27) (width 0.4) (layer B.Cu) (net 1))
(segment (start 31.010762 38.27) (end 28.58 38.27) (width 0.4) (layer B.Cu) (net 1))
(segment (start 35.9 33.275) (end 37.805 33.275) (width 0.25) (layer F.Cu) (net 1))
(via (at 37.96 33.12) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 37.805 33.275) (end 37.96 33.12) (width 0.25) (layer F.Cu) (net 1))
(segment (start 20.60045 32.95008) (end 20.35026 32.95008) (width 0.25) (layer B.Cu) (net 1))
(segment (start 28.49 38.18) (end 22.91 38.18) (width 1.5) (layer B.Cu) (net 1))
(segment (start 22.91 38.18) (end 20.35026 35.62026) (width 1.5) (layer B.Cu) (net 1))
(segment (start 38.23 37.65) (end 37.61 38.27) (width 1.5) (layer B.Cu) (net 1))
(segment (start 43.1 32.625) (end 41.095 32.625) (width 0.25) (layer F.Cu) (net 1))
(segment (start 40.879999 33.339999) (end 40.63 33.09) (width 0.25) (layer B.Cu) (net 1))
(segment (start 40.99 33.45) (end 40.879999 33.339999) (width 0.25) (layer B.Cu) (net 1))
(segment (start 38.775 34.5) (end 40.185 33.09) (width 0.25) (layer B.Cu) (net 1))
(segment (start 40.879999 32.840001) (end 40.63 33.09) (width 0.25) (layer F.Cu) (net 1))
(segment (start 40.185 33.09) (end 40.276447 33.09) (width 0.25) (layer B.Cu) (net 1))
(segment (start 41.465 33.925) (end 40.879999 33.339999) (width 0.25) (layer F.Cu) (net 1))
(segment (start 41.095 32.625) (end 40.879999 32.840001) (width 0.25) (layer F.Cu) (net 1))
(segment (start 40.879999 33.339999) (end 40.63 33.09) (width 0.25) (layer F.Cu) (net 1))
(segment (start 42.5 33.45) (end 40.99 33.45) (width 0.25) (layer B.Cu) (net 1))
(segment (start 43.1 33.925) (end 41.465 33.925) (width 0.25) (layer F.Cu) (net 1))
(segment (start 38.55 34.5) (end 38.775 34.5) (width 0.25) (layer B.Cu) (net 1))
(segment (start 40.276447 33.09) (end 40.63 33.09) (width 0.25) (layer B.Cu) (net 1))
(via (at 40.63 33.09) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 46 34.95) (end 45.375 34.95) (width 0.25) (layer F.Cu) (net 1))
(segment (start 45.375 34.95) (end 44.35 33.925) (width 0.25) (layer F.Cu) (net 1))
(segment (start 44.35 33.925) (end 44.225 33.925) (width 0.25) (layer F.Cu) (net 1))
(segment (start 44.225 33.925) (end 43.1 33.925) (width 0.25) (layer F.Cu) (net 1))
(segment (start 39.26 18.54) (end 38.7 18.54) (width 0.25) (layer B.Cu) (net 1))
(segment (start 39.78 18.54) (end 39.26 18.54) (width 0.25) (layer B.Cu) (net 1))
(segment (start 38.7 18.54) (end 38.67 18.57) (width 0.25) (layer B.Cu) (net 1))
(segment (start 40.55 17.5) (end 40.55 17.77) (width 0.25) (layer F.Cu) (net 1))
(segment (start 40.55 17.77) (end 39.78 18.54) (width 0.25) (layer F.Cu) (net 1))
(via (at 39.78 18.54) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 38.45 17.5) (end 38.45 18.35) (width 0.25) (layer F.Cu) (net 1))
(segment (start 38.45 18.35) (end 38.67 18.57) (width 0.25) (layer F.Cu) (net 1))
(via (at 38.67 18.57) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 38.23 35.445) (end 38.23 37.65) (width 0.25) (layer B.Cu) (net 1))
(segment (start 38.23 37.65) (end 38.23 40.5) (width 0.25) (layer B.Cu) (net 1))
(segment (start 35.9 30.025) (end 33.075 30.025) (width 0.25) (layer F.Cu) (net 1))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 33.075 30.025) (end 32.5 29.45) (width 0.25) (layer F.Cu) (net 1))
(segment (start 38.55 34.5) (end 38.55 35.125) (width 0.25) (layer B.Cu) (net 1))
(segment (start 38.55 35.125) (end 38.23 35.445) (width 0.25) (layer B.Cu) (net 1))
(segment (start 39.74 42.01) (end 38.23 40.5) (width 0.25) (layer B.Cu) (net 1))
(segment (start 39.71 42.45) (end 41 42.45) (width 0.25) (layer F.Cu) (net 1))
(segment (start 39.125 42.45) (end 39.71 42.45) (width 0.25) (layer F.Cu) (net 1))
(segment (start 39.71 42.45) (end 39.71 42.04) (width 0.25) (layer F.Cu) (net 1))
(segment (start 39.71 42.04) (end 39.74 42.01) (width 0.25) (layer F.Cu) (net 1))
(via (at 39.74 42.01) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 38.5 42.45) (end 39.125 42.45) (width 0.25) (layer F.Cu) (net 1))
(segment (start 28.49 38.18) (end 28.58 38.27) (width 0.6) (layer B.Cu) (net 1))
(segment (start 20.35026 35.62026) (end 23 38.27) (width 0.6) (layer B.Cu) (net 1))
(segment (start 23 38.27) (end 28.58 38.27) (width 0.6) (layer B.Cu) (net 1))
(segment (start 28.58 38.27) (end 32.7 42.39) (width 0.6) (layer B.Cu) (net 1))
(segment (start 32.7 42.39) (end 32.7 47) (width 0.6) (layer B.Cu) (net 1))
(segment (start 32.7 50.2) (end 32.7 47) (width 0.6) (layer B.Cu) (net 1))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(segment (start 31.98 36.22) (end 31.98 33.32) (width 0.4) (layer F.Cu) (net 2))
(segment (start 31.98 33.32) (end 32.675 32.625) (width 0.4) (layer F.Cu) (net 2))
(segment (start 26.9036 38.5) (end 26.9036 35.9536) (width 0.6) (layer F.Cu) (net 2))
(segment (start 26.9036 35.9536) (end 26.45 35.5) (width 0.6) (layer F.Cu) (net 2))
(segment (start 26.9036 38.5) (end 29.7 38.5) (width 0.6) (layer F.Cu) (net 2))
(segment (start 29.7 38.5) (end 31.98 36.22) (width 0.6) (layer F.Cu) (net 2))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 35.9 32.625) (end 32.675 32.625) (width 0.25) (layer F.Cu) (net 2))
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(segment (start 54.5 44.35) (end 56.15 44.35) (width 0.8) (layer B.Cu) (net 3))
(segment (start 56.15 44.35) (end 56.5 44) (width 0.8) (layer B.Cu) (net 3))
(segment (start 54.225 48.625) (end 54.5 48.35) (width 0.4) (layer F.Cu) (net 3))
(segment (start 54.5 48.35) (end 54.5 44.35) (width 0.4) (layer F.Cu) (net 3))
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(segment (start 39.61 59.03) (end 45.21 59.03) (width 0.8) (layer F.Cu) (net 3))
(segment (start 45.21 59.03) (end 44.34 58.16) (width 0.8) (layer F.Cu) (net 3))
(segment (start 44.34 58.16) (end 52.5 50) (width 0.8) (layer F.Cu) (net 3))
(segment (start 52.5 50) (end 54.225 50) (width 0.8) (layer F.Cu) (net 3))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 20.44932 26.8998) (end 18.8502 26.8998) (width 0.6) (layer F.Cu) (net 3))
(segment (start 18.8502 26.8998) (end 16.53 29.22) (width 0.6) (layer F.Cu) (net 3))
(segment (start 16.53 29.22) (end 16.53 31.27) (width 0.6) (layer F.Cu) (net 3))
(segment (start 16.53 31.27) (end 17.51 32.25) (width 0.6) (layer F.Cu) (net 3))
(segment (start 17.51 32.25) (end 17.51 33.258992) (width 0.6) (layer F.Cu) (net 3))
(segment (start 20.56 59.03) (end 39.61 59.03) (width 0.8) (layer F.Cu) (net 3))
(segment (start 39.66 58.98) (end 39.61 59.03) (width 0.8) (layer F.Cu) (net 3))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(segment (start 20.0964 38.5) (end 17.5464 38.5) (width 0.8) (layer F.Cu) (net 3))
(segment (start 17.5464 38.5) (end 17.51 38.4636) (width 0.8) (layer F.Cu) (net 3))
(segment (start 17.51 38.4636) (end 17.51 36.47) (width 0.8) (layer F.Cu) (net 3))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(segment (start 17.51 36.47) (end 14.93 39.05) (width 0.8) (layer F.Cu) (net 3))
(segment (start 14.93 39.05) (end 14.93 53.4) (width 0.8) (layer F.Cu) (net 3))
(segment (start 14.93 53.4) (end 20.56 59.03) (width 0.8) (layer F.Cu) (net 3))
(segment (start 20.0964 38.5) (end 20.0964 35.9536) (width 0.6) (layer F.Cu) (net 3))
(segment (start 20.0964 35.9536) (end 20.55 35.5) (width 0.6) (layer F.Cu) (net 3))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 54.225 50) (end 54.225 48.625) (width 0.8) (layer F.Cu) (net 3))
(segment (start 17.51 33.258992) (end 17.51 36.47) (width 0.8) (layer F.Cu) (net 3))
(segment (start 37.3 36.18) (end 37.3 34.7) (width 0.4) (layer F.Cu) (net 4))
(segment (start 37.3 34.7) (end 37.175 34.575) (width 0.4) (layer F.Cu) (net 4))
(segment (start 37.175 34.575) (end 35.9 34.575) (width 0.4) (layer F.Cu) (net 4))
(segment (start 35.75 34.54) (end 35.75 34.63) (width 0.4) (layer B.Cu) (net 4))
(via (at 37.3 36.18) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 4))
(segment (start 35.75 34.63) (end 37.3 36.18) (width 0.4) (layer B.Cu) (net 4))
(segment (start 35.9 26.775) (end 35.9 26.3) (width 0.25) (layer F.Cu) (net 5))
(segment (start 35.9 26.3) (end 36.85085 25.34915) (width 0.25) (layer F.Cu) (net 5))
(segment (start 36.85085 25.34915) (end 36.85085 24.5) (width 0.25) (layer F.Cu) (net 5))
(segment (start 34.65114 21) (end 34.65114 22.30029) (width 0.25) (layer F.Cu) (net 5))
(segment (start 34.65114 22.30029) (end 36.85085 24.5) (width 0.25) (layer F.Cu) (net 5))
(segment (start 36.85085 24.5) (end 37.55 24.5) (width 0.25) (layer F.Cu) (net 5))
(segment (start 37.55 24.5) (end 38.4 24.5) (width 0.25) (layer F.Cu) (net 5))
(segment (start 34.65114 21) (end 34.65114 19.17386) (width 0.25) (layer F.Cu) (net 5))
(segment (start 34.65114 19.17386) (end 36.325 17.5) (width 0.25) (layer F.Cu) (net 5))
(segment (start 36.325 17.5) (end 36.55 17.5) (width 0.25) (layer F.Cu) (net 5))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 41.4 28.075) (end 43.1 28.075) (width 0.25) (layer F.Cu) (net 6))
(segment (start 40.315 28.075) (end 41.4 28.075) (width 0.4) (layer F.Cu) (net 6))
(segment (start 41.42 28.725) (end 39.835 28.725) (width 0.4) (layer F.Cu) (net 6))
(segment (start 43.1 28.725) (end 41.42 28.725) (width 0.25) (layer F.Cu) (net 6))
(segment (start 39.835 28.725) (end 39.75 28.64) (width 0.4) (layer F.Cu) (net 6))
(segment (start 38.685 31.325) (end 38.035 30.675) (width 0.4) (layer F.Cu) (net 6))
(segment (start 39.75 31.325) (end 38.685 31.325) (width 0.4) (layer F.Cu) (net 6))
(segment (start 39.75 31.325) (end 40.97 31.325) (width 0.4) (layer F.Cu) (net 6))
(segment (start 39.75 30.96) (end 39.75 31.325) (width 0.4) (layer F.Cu) (net 6))
(segment (start 39.75 30.96) (end 39.75 28.79) (width 0.25) (layer F.Cu) (net 6))
(segment (start 39.75 28.64) (end 39.75 30.96) (width 0.4) (layer F.Cu) (net 6))
(segment (start 40.315 28.075) (end 39.75 28.64) (width 0.4) (layer F.Cu) (net 6))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(segment (start 38.035 30.675) (end 35.9 30.675) (width 0.25) (layer F.Cu) (net 6))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 39.815 28.725) (end 39.75 28.79) (width 0.25) (layer F.Cu) (net 6))
(segment (start 39.75 28.79) (end 39.75 28.64) (width 0.25) (layer F.Cu) (net 6))
(segment (start 43.1 31.325) (end 40.97 31.325) (width 0.25) (layer F.Cu) (net 6))
(segment (start 28.570001 28.079999) (end 28.82 27.83) (width 0.25) (layer B.Cu) (net 6))
(segment (start 27.15 29.5) (end 28.570001 28.079999) (width 0.25) (layer B.Cu) (net 6))
(segment (start 26.1 29.5) (end 27.15 29.5) (width 0.25) (layer B.Cu) (net 6))
(segment (start 29.1 27.55) (end 29.069999 27.580001) (width 0.25) (layer F.Cu) (net 6))
(segment (start 29.069999 27.580001) (end 28.82 27.83) (width 0.25) (layer F.Cu) (net 6))
(segment (start 32.5 27.55) (end 29.1 27.55) (width 0.25) (layer F.Cu) (net 6))
(via (at 28.82 27.83) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 6))
(segment (start 32.5 27.775) (end 33.535 27.775) (width 0.25) (layer F.Cu) (net 6))
(segment (start 33.535 27.775) (end 34.485 28.725) (width 0.25) (layer F.Cu) (net 6))
(segment (start 34.485 28.725) (end 34.775 28.725) (width 0.25) (layer F.Cu) (net 6))
(segment (start 34.775 28.725) (end 35.9 28.725) (width 0.25) (layer F.Cu) (net 6))
(segment (start 35.9 30.675) (end 31.465 30.675) (width 0.25) (layer F.Cu) (net 6))
(segment (start 31.705 27.775) (end 32.5 27.775) (width 0.25) (layer F.Cu) (net 6))
(segment (start 31.465 30.675) (end 31.26 30.47) (width 0.25) (layer F.Cu) (net 6))
(segment (start 31.26 30.47) (end 31.26 28.22) (width 0.25) (layer F.Cu) (net 6))
(segment (start 31.26 28.22) (end 31.705 27.775) (width 0.25) (layer F.Cu) (net 6))
(segment (start 32.5 27.55) (end 32.5 27.775) (width 0.25) (layer F.Cu) (net 6))
(segment (start 17 45.5) (end 17 43.05) (width 0.6) (layer F.Cu) (net 7))
(segment (start 17 43.05) (end 17.05 43) (width 0.6) (layer F.Cu) (net 7))
(segment (start 17 51.5) (end 17 49.9) (width 0.6) (layer F.Cu) (net 7))
(segment (start 17 49.9) (end 17 45.5) (width 0.6) (layer F.Cu) (net 7))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 18.95 43) (end 19.7 43.75) (width 0.4) (layer F.Cu) (net 8))
(segment (start 19.7 43.75) (end 35.18934 43.75) (width 0.4) (layer F.Cu) (net 8))
(segment (start 35.18934 43.75) (end 38.43934 47) (width 0.4) (layer F.Cu) (net 8))
(segment (start 38.43934 47) (end 39.5 47) (width 0.4) (layer F.Cu) (net 8))
(segment (start 22 47.55) (end 23.25 47.55) (width 0.4) (layer B.Cu) (net 9))
(segment (start 23.25 47.55) (end 24.5 46.3) (width 0.4) (layer B.Cu) (net 9))
(segment (start 25.75 48.72) (end 25.37 49.1) (width 0.4) (layer B.Cu) (net 10))
(segment (start 25.37 49.1) (end 22.35 49.1) (width 0.4) (layer B.Cu) (net 10))
(segment (start 22.35 49.1) (end 22 49.45) (width 0.4) (layer B.Cu) (net 10))
(segment (start 38.01 48.69) (end 38.01 48.71) (width 0.4) (layer F.Cu) (net 10))
(segment (start 38.01 48.71) (end 39.5 50.2) (width 0.4) (layer F.Cu) (net 10))
(segment (start 25.75 48.72) (end 26.103553 48.72) (width 0.4) (layer F.Cu) (net 10))
(segment (start 26.103553 48.72) (end 26.133553 48.69) (width 0.4) (layer F.Cu) (net 10))
(segment (start 26.133553 48.69) (end 38.01 48.69) (width 0.4) (layer F.Cu) (net 10))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(via (at 25.75 48.72) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 10))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 43.9 47) (end 43.9 45.17) (width 0.4) (layer F.Cu) (net 11))
(segment (start 43.07 44.34) (end 37.1 44.34) (width 0.4) (layer F.Cu) (net 11))
(segment (start 43.9 45.17) (end 43.07 44.34) (width 0.4) (layer F.Cu) (net 11))
(segment (start 37.1 44.34) (end 36 43.24) (width 0.4) (layer F.Cu) (net 11))
(segment (start 36 43.24) (end 36 42.5) (width 0.4) (layer F.Cu) (net 11))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 35.9 38) (end 35.9 40.5) (width 0.25) (layer F.Cu) (net 12))
(segment (start 35.9 40.5) (end 36 40.6) (width 0.25) (layer F.Cu) (net 12))
(segment (start 35.9 35.225) (end 35.9 35.7) (width 0.25) (layer F.Cu) (net 12))
(segment (start 35.9 35.7) (end 35.9 38) (width 0.25) (layer F.Cu) (net 12))
(segment (start 38.1 38) (end 38.1 40.15) (width 0.25) (layer F.Cu) (net 13))
(segment (start 38.1 40.15) (end 38.5 40.55) (width 0.25) (layer F.Cu) (net 13))
(segment (start 40.9 38) (end 40.9 40.45) (width 0.25) (layer F.Cu) (net 14))
(segment (start 40.9 40.45) (end 41 40.55) (width 0.25) (layer F.Cu) (net 14))
(segment (start 44.34886 21) (end 44.34886 19.17386) (width 0.25) (layer F.Cu) (net 15))
(segment (start 44.34886 19.17386) (end 42.675 17.5) (width 0.25) (layer F.Cu) (net 15))
(segment (start 42.675 17.5) (end 42.45 17.5) (width 0.25) (layer F.Cu) (net 15))
(segment (start 43.1 26.775) (end 43.1 26.3) (width 0.25) (layer F.Cu) (net 15))
(segment (start 43.1 26.3) (end 42.14915 25.34915) (width 0.25) (layer F.Cu) (net 15))
(segment (start 42.14915 25.34915) (end 42.14915 24.5) (width 0.25) (layer F.Cu) (net 15))
(segment (start 44.34886 21) (end 44.34886 22.30029) (width 0.25) (layer F.Cu) (net 15))
(segment (start 44.34886 22.30029) (end 42.14915 24.5) (width 0.25) (layer F.Cu) (net 15))
(segment (start 42.14915 24.5) (end 41.45 24.5) (width 0.25) (layer F.Cu) (net 15))
(segment (start 41.45 24.5) (end 40.6 24.5) (width 0.25) (layer F.Cu) (net 15))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 44.01 42.45) (end 43 42.45) (width 0.4) (layer F.Cu) (net 16))
(segment (start 45.63 44.07) (end 45.63 48.47) (width 0.4) (layer F.Cu) (net 16))
(segment (start 45.63 48.47) (end 43.9 50.2) (width 0.4) (layer F.Cu) (net 16))
(segment (start 44.01 42.45) (end 45.63 44.07) (width 0.4) (layer F.Cu) (net 16))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 43.9 50.2) (end 45.39 48.71) (width 0.25) (layer F.Cu) (net 16))
(segment (start 43.1 38) (end 43.1 40.45) (width 0.25) (layer F.Cu) (net 17))
(segment (start 43.1 40.45) (end 43 40.55) (width 0.25) (layer F.Cu) (net 17))
(segment (start 43.1 35.225) (end 43.1 35.7) (width 0.25) (layer F.Cu) (net 17))
(segment (start 43.1 35.7) (end 43.1 38) (width 0.25) (layer F.Cu) (net 17))
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(segment (start 54.5 34.19) (end 54.64 34.19) (width 0.8) (layer B.Cu) (net 18))
(segment (start 54.64 34.19) (end 56 35.55) (width 0.8) (layer B.Cu) (net 18))
(segment (start 54.5 34.19) (end 54.76 34.19) (width 0.8) (layer B.Cu) (net 18))
(segment (start 54.76 34.19) (end 56 32.95) (width 0.8) (layer B.Cu) (net 18))
(segment (start 54.5 34.19) (end 57.28 34.19) (width 0.8) (layer F.Cu) (net 18))
(segment (start 57.28 34.19) (end 57.29 34.18) (width 0.8) (layer F.Cu) (net 18))
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(segment (start 101 55) (end 100.925 55) (width 0.4) (layer B.Cu) (net 18))
(segment (start 100.925 55) (end 99.45 53.525) (width 0.4) (layer B.Cu) (net 18))
(segment (start 99.45 53.525) (end 99.45 52.75) (width 0.4) (layer B.Cu) (net 18))
(segment (start 102.7 55.1) (end 101.1 55.1) (width 0.6) (layer B.Cu) (net 18))
(segment (start 101.1 55.1) (end 101 55) (width 0.6) (layer B.Cu) (net 18))
(segment (start 101.08 50.5) (end 99.5 50.5) (width 0.25) (layer B.Cu) (net 18))
(segment (start 99.5 50.5) (end 98.7 50.5) (width 0.25) (layer B.Cu) (net 18))
(segment (start 99.45 52.75) (end 99.45 50.55) (width 0.4) (layer B.Cu) (net 18))
(segment (start 99.45 50.55) (end 99.5 50.5) (width 0.4) (layer B.Cu) (net 18))
(segment (start 101.760002 39.75) (end 101.760002 37.239998) (width 1.5) (layer B.Cu) (net 18))
(segment (start 101.760002 37.239998) (end 105.25 33.75) (width 1.5) (layer B.Cu) (net 18))
(segment (start 105.25 33.75) (end 105.25 31.75) (width 1.5) (layer B.Cu) (net 18))
(segment (start 105.25 31.75) (end 106.450001 30.549999) (width 1.5) (layer B.Cu) (net 18))
(segment (start 106.450001 30.549999) (end 106.450001 24.349999) (width 1.5) (layer B.Cu) (net 18))
(segment (start 105.5 50.5) (end 108 50.5) (width 0.4) (layer B.Cu) (net 18))
(segment (start 101.08 50.5) (end 105.5 50.5) (width 0.4) (layer B.Cu) (net 18))
(segment (start 108.5 21.3) (end 107.250001 22.549999) (width 0.6) (layer B.Cu) (net 18))
(segment (start 107.250001 23.549999) (end 106.450001 24.349999) (width 0.6) (layer B.Cu) (net 18))
(segment (start 107.250001 22.549999) (end 107.250001 23.549999) (width 0.6) (layer B.Cu) (net 18))
add balance poti
2017-08-28 22:59:34 +02:00
(segment (start 99.700001 45.200001) (end 100 45.5) (width 0.4) (layer B.Cu) (net 18))
(segment (start 99.5 45) (end 99.700001 45.200001) (width 0.4) (layer B.Cu) (net 18))
(segment (start 96 45) (end 99.5 45) (width 0.4) (layer B.Cu) (net 18))
(via (at 100 45.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 97.160001 44.350001) (end 101.760002 39.75) (width 1.5) (layer B.Cu) (net 18))
(segment (start 106.54 40.04) (end 102.050002 40.04) (width 0.4) (layer B.Cu) (net 18))
(segment (start 102.050002 40.04) (end 101.760002 39.75) (width 0.4) (layer B.Cu) (net 18))
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(segment (start 72.25 52.85) (end 75.65 52.85) (width 0.4) (layer F.Cu) (net 18))
(segment (start 75.65 52.85) (end 75.75 52.75) (width 0.4) (layer F.Cu) (net 18))
(segment (start 75.75 52.674264) (end 75.75 52.75) (width 0.4) (layer B.Cu) (net 18))
(segment (start 75.82 52.604264) (end 75.75 52.674264) (width 0.4) (layer B.Cu) (net 18))
(segment (start 75.82 52.6) (end 75.82 52.604264) (width 0.4) (layer B.Cu) (net 18))
(segment (start 75.5 53) (end 75.75 52.75) (width 0.4) (layer F.Cu) (net 18))
(segment (start 75.5 54.05) (end 75.5 53) (width 0.4) (layer F.Cu) (net 18))
(via (at 75.75 52.75) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 94.95 47.3) (end 95 47.25) (width 0.4) (layer F.Cu) (net 18))
(segment (start 94.95 48.5) (end 94.95 47.3) (width 0.4) (layer F.Cu) (net 18))
(segment (start 93.75 47.25) (end 95 47.25) (width 0.4) (layer B.Cu) (net 18))
(via (at 95 47.25) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 18))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 96 45) (end 96.46 45.46) (width 0.4) (layer B.Cu) (net 18))
(segment (start 102.7 56.93) (end 108.020002 56.93) (width 0.4) (layer B.Cu) (net 18))
(segment (start 108.020002 56.93) (end 108.680001 56.270001) (width 0.4) (layer B.Cu) (net 18))
(segment (start 109.5 59.5) (end 108.98 58.98) (width 0.4) (layer B.Cu) (net 18))
(segment (start 108.680001 56.270001) (end 108.98 55.970002) (width 0.4) (layer B.Cu) (net 18))
(segment (start 108.98 56.394266) (end 108.98 55.970002) (width 0.4) (layer B.Cu) (net 18))
(segment (start 108.98 58.98) (end 108.98 56.394266) (width 0.4) (layer B.Cu) (net 18))
(segment (start 108.680001 56.270001) (end 108.98 55.970002) (width 0.4) (layer F.Cu) (net 18))
(segment (start 53.980002 56.03) (end 59.370002 61.42) (width 0.4) (layer F.Cu) (net 18))
(segment (start 59.370002 61.42) (end 103.530002 61.42) (width 0.4) (layer F.Cu) (net 18))
(via (at 108.98 55.970002) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 103.530002 61.42) (end 108.680001 56.270001) (width 0.4) (layer F.Cu) (net 18))
(segment (start 85 42.1) (end 85 42.325) (width 0.4) (layer B.Cu) (net 18))
(segment (start 85 42.325) (end 84.225 43.1) (width 0.4) (layer B.Cu) (net 18))
(segment (start 84.225 43.1) (end 83.66 43.1) (width 0.4) (layer B.Cu) (net 18))
(segment (start 83.66 43.1) (end 82.8 43.96) (width 0.4) (layer B.Cu) (net 18))
(segment (start 82.8 43.96) (end 82.8 44.193998) (width 0.4) (layer B.Cu) (net 18))
(segment (start 53.680003 56.329999) (end 53.980002 56.03) (width 0.4) (layer B.Cu) (net 18))
(segment (start 53.79 56.48) (end 53.680003 56.370003) (width 0.4) (layer B.Cu) (net 18))
(segment (start 53.680003 56.370003) (end 53.680003 56.329999) (width 0.4) (layer B.Cu) (net 18))
(via (at 53.980002 56.03) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 53.79 56.48) (end 53.880004 56.48) (width 1.5) (layer B.Cu) (net 18))
(segment (start 53.880004 56.48) (end 56.350004 54.01) (width 1.5) (layer B.Cu) (net 18))
(segment (start 56.350004 54.01) (end 73 54.01) (width 1.5) (layer B.Cu) (net 18))
(segment (start 93.14 56.44) (end 91.44 56.44) (width 0.4) (layer B.Cu) (net 18))
(segment (start 91.44 56.44) (end 91 56) (width 0.4) (layer B.Cu) (net 18))
(via (at 91 56) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(via (at 109.5 59.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 82.8 47.555) (end 82.8 55.2) (width 0.4) (layer B.Cu) (net 18))
(segment (start 82.8 55.2) (end 81.5 56.5) (width 0.4) (layer B.Cu) (net 18))
(via (at 81.5 56.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 73 54.01) (end 74.41 54.01) (width 1.5) (layer B.Cu) (net 18))
(segment (start 73 56.5) (end 74 57.5) (width 0.4) (layer B.Cu) (net 18))
(segment (start 73 54.01) (end 73 56.5) (width 0.4) (layer B.Cu) (net 18))
(via (at 74 57.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 59.36 35.37) (end 59.55 35.18) (width 0.4) (layer F.Cu) (net 18))
(segment (start 58.054264 35.37) (end 59.36 35.37) (width 0.4) (layer F.Cu) (net 18))
(segment (start 57.41 35.15) (end 57.834264 35.15) (width 0.4) (layer F.Cu) (net 18))
(segment (start 57.834264 35.15) (end 58.054264 35.37) (width 0.4) (layer F.Cu) (net 18))
(segment (start 102.7 57.42) (end 102.7 56.93) (width 0.4) (layer B.Cu) (net 18))
(segment (start 102.7 56.93) (end 102.7 55.1) (width 0.4) (layer B.Cu) (net 18))
(segment (start 50.22 60.05) (end 53.79 56.48) (width 1.5) (layer B.Cu) (net 18))
(segment (start 30.5 50.2) (end 30.5 56.38) (width 1.5) (layer B.Cu) (net 18))
(segment (start 30.5 56.38) (end 34.17 60.05) (width 1.5) (layer B.Cu) (net 18))
(segment (start 34.17 60.05) (end 50.22 60.05) (width 1.5) (layer B.Cu) (net 18))
(segment (start 57.28 34.19) (end 57.29 34.18) (width 0.25) (layer B.Cu) (net 18))
(segment (start 57.135 34.19) (end 57.28 34.19) (width 0.25) (layer B.Cu) (net 18))
(segment (start 57.3 34.19) (end 57.29 34.18) (width 0.4) (layer F.Cu) (net 18))
(segment (start 58.5 34.19) (end 57.3 34.19) (width 0.4) (layer F.Cu) (net 18))
(segment (start 57.3 34.19) (end 57.29 34.18) (width 0.25) (layer B.Cu) (net 18))
(segment (start 58.5 34.19) (end 57.3 34.19) (width 0.25) (layer B.Cu) (net 18))
(via (at 57.29 34.18) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 56 35.55) (end 56 35.325) (width 0.25) (layer B.Cu) (net 18))
(segment (start 56 35.325) (end 57.135 34.19) (width 0.25) (layer B.Cu) (net 18))
(segment (start 58.5 34.19) (end 58.37 34.19) (width 0.4) (layer F.Cu) (net 18))
(segment (start 58.37 34.19) (end 57.41 35.15) (width 0.4) (layer F.Cu) (net 18))
(via (at 57.41 35.15) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 58.5 34.19) (end 57.26 32.95) (width 0.4) (layer F.Cu) (net 18))
(via (at 57.26 32.95) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 74.95 22.26) (end 72.05 25.16) (width 0.4) (layer F.Cu) (net 18))
(segment (start 72.05 25.16) (end 72.05 28) (width 0.4) (layer F.Cu) (net 18))
(segment (start 74.95 19.5) (end 74.95 22.26) (width 0.4) (layer F.Cu) (net 18))
(segment (start 64.5 29) (end 65.55 29) (width 0.4) (layer F.Cu) (net 18))
(segment (start 65.55 29) (end 66.55 28) (width 0.4) (layer F.Cu) (net 18))
(segment (start 66.55 28) (end 71.05 28) (width 0.4) (layer F.Cu) (net 18))
(segment (start 71.05 28) (end 72.05 28) (width 0.4) (layer F.Cu) (net 18))
(segment (start 58.5 34.19) (end 63.69 29) (width 0.4) (layer F.Cu) (net 18))
(segment (start 63.69 29) (end 64.5 29) (width 0.4) (layer F.Cu) (net 18))
(segment (start 71.25 34.3) (end 69.5 34.3) (width 0.4) (layer F.Cu) (net 18))
(segment (start 73 34.3) (end 71.25 34.3) (width 0.4) (layer F.Cu) (net 18))
(segment (start 76.196 33.086) (end 74.39 31.28) (width 0.4) (layer F.Cu) (net 18))
(segment (start 74.39 31.28) (end 72.05 28.94) (width 0.4) (layer F.Cu) (net 18))
(segment (start 72.8 31.62) (end 73.8 31.62) (width 0.4) (layer F.Cu) (net 18))
(segment (start 73.8 31.62) (end 74.14 31.28) (width 0.4) (layer F.Cu) (net 18))
(segment (start 74.14 31.28) (end 74.39 31.28) (width 0.4) (layer F.Cu) (net 18))
(segment (start 78.5 31) (end 78.5 32.05) (width 0.4) (layer F.Cu) (net 18))
(segment (start 78.5 32.05) (end 77.464 33.086) (width 0.4) (layer F.Cu) (net 18))
(segment (start 72.05 28.94) (end 72.05 28) (width 0.4) (layer F.Cu) (net 18))
(segment (start 77.464 33.086) (end 76.196 33.086) (width 0.4) (layer F.Cu) (net 18))
(segment (start 93.445 47.555) (end 93.75 47.25) (width 1.5) (layer B.Cu) (net 18))
(segment (start 93.75 47.25) (end 96 45) (width 1.5) (layer B.Cu) (net 18))
(segment (start 76.25 31.75) (end 77 31.75) (width 0.4) (layer F.Cu) (net 18))
(via (at 77 31.75) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 76.25 31) (end 76.25 31.75) (width 0.4) (layer B.Cu) (net 18))
(via (at 76.25 31.75) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 76.25 30.25) (end 76.25 31) (width 0.4) (layer F.Cu) (net 18))
(via (at 76.25 31) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 77 30.25) (end 76.25 30.25) (width 0.4) (layer B.Cu) (net 18))
(via (at 76.25 30.25) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 78.5 31) (end 77.75 31) (width 0.4) (layer F.Cu) (net 18))
(segment (start 77.75 31) (end 77 30.25) (width 0.4) (layer F.Cu) (net 18))
(via (at 77 30.25) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 78.5 31) (end 77 31) (width 0.4) (layer F.Cu) (net 18))
(via (at 77 31) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 83 26.5) (end 79.75 29.75) (width 0.8) (layer F.Cu) (net 18))
(segment (start 79.75 29.75) (end 78.5 31) (width 0.8) (layer F.Cu) (net 18))
(segment (start 84.05 29.75) (end 79.75 29.75) (width 0.4) (layer F.Cu) (net 18))
(segment (start 83 26) (end 83 26.5) (width 0.8) (layer F.Cu) (net 18))
(segment (start 74.95 19.5) (end 76.95 19.5) (width 0.4) (layer F.Cu) (net 18))
(segment (start 76.95 19.5) (end 77.5 20.05) (width 0.4) (layer F.Cu) (net 18))
(segment (start 84.05 31.5) (end 79 31.5) (width 0.4) (layer F.Cu) (net 18))
(segment (start 79 31.5) (end 78.5 31) (width 0.4) (layer F.Cu) (net 18))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(segment (start 101.31 58.81) (end 101.31 59.39) (width 0.6) (layer B.Cu) (net 18))
(segment (start 101.31 59.39) (end 101.2 59.5) (width 0.6) (layer B.Cu) (net 18))
(segment (start 101.2 59.5) (end 100 59.5) (width 0.6) (layer B.Cu) (net 18))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(segment (start 79.71 45.18) (end 81.813998 45.18) (width 0.4) (layer B.Cu) (net 18))
(segment (start 81.813998 45.18) (end 82.8 44.193998) (width 0.4) (layer B.Cu) (net 18))
(segment (start 71.5 43.5) (end 72.55 43.5) (width 0.4) (layer B.Cu) (net 18))
(segment (start 72.55 43.5) (end 76.605 47.555) (width 0.4) (layer B.Cu) (net 18))
(segment (start 76.605 47.555) (end 80.865 47.555) (width 0.4) (layer B.Cu) (net 18))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 82.8 44.193998) (end 82.8 45.155) (width 0.4) (layer B.Cu) (net 18))
(segment (start 82.8 45.155) (end 82.8 47.555) (width 0.4) (layer B.Cu) (net 18))
(segment (start 93.14 56.44) (end 93.14 55.39) (width 0.4) (layer B.Cu) (net 18))
(segment (start 93.14 55.39) (end 90.84 53.09) (width 0.4) (layer B.Cu) (net 18))
(segment (start 90.84 53.09) (end 90.415736 53.09) (width 0.4) (layer B.Cu) (net 18))
(segment (start 90.415736 53.09) (end 89.915736 52.59) (width 0.4) (layer B.Cu) (net 18))
(segment (start 89.915736 52.59) (end 89.91 52.59) (width 0.4) (layer B.Cu) (net 18))
(segment (start 92 52.45) (end 91.48 52.45) (width 0.4) (layer F.Cu) (net 18))
(segment (start 91.48 52.45) (end 90.84 53.09) (width 0.4) (layer F.Cu) (net 18))
(via (at 90.84 53.09) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 101.31 58.81) (end 102.7 57.42) (width 0.4) (layer B.Cu) (net 18))
(segment (start 86.99 55.51) (end 89.91 52.59) (width 0.4) (layer B.Cu) (net 18))
(segment (start 89.91 52.59) (end 89.91 51.41) (width 0.4) (layer B.Cu) (net 18))
(segment (start 86.9 56.5) (end 86.9 55.6) (width 0.4) (layer F.Cu) (net 18))
(segment (start 86.9 55.6) (end 86.99 55.51) (width 0.4) (layer F.Cu) (net 18))
(via (at 86.99 55.51) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 75.155 54.01) (end 74.41 54.01) (width 0.4) (layer B.Cu) (net 18))
(segment (start 74.41 54.01) (end 75.82 52.6) (width 1.5) (layer B.Cu) (net 18))
(segment (start 75.82 52.6) (end 80.865 47.555) (width 1.5) (layer B.Cu) (net 18))
(segment (start 102.92 56.18) (end 102.92 55.32) (width 0.6) (layer F.Cu) (net 18))
(segment (start 102.92 55.32) (end 102.7 55.1) (width 0.6) (layer F.Cu) (net 18))
(via (at 102.7 55.1) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 97.4 48.5) (end 97.4 46.4) (width 0.25) (layer B.Cu) (net 18))
(segment (start 97.4 46.4) (end 96 45) (width 0.25) (layer B.Cu) (net 18))
(segment (start 98.7 50.5) (end 97.4 49.2) (width 0.25) (layer B.Cu) (net 18))
(segment (start 97.4 49.2) (end 97.4 48.5) (width 0.25) (layer B.Cu) (net 18))
(segment (start 80.865 47.555) (end 82.8 47.555) (width 1.5) (layer B.Cu) (net 18))
(segment (start 82.8 47.555) (end 90.07 47.555) (width 1.5) (layer B.Cu) (net 18))
(segment (start 90.07 47.555) (end 93.445 47.555) (width 1.5) (layer B.Cu) (net 18))
(segment (start 90.07 50.825736) (end 90.07 47.555) (width 0.4) (layer B.Cu) (net 18))
(segment (start 89.91 51.41) (end 89.91 50.985736) (width 0.4) (layer B.Cu) (net 18))
(segment (start 89.91 50.985736) (end 90.07 50.825736) (width 0.4) (layer B.Cu) (net 18))
(segment (start 90 50.1) (end 90 51.32) (width 0.4) (layer F.Cu) (net 18))
(segment (start 90 51.32) (end 89.91 51.41) (width 0.4) (layer F.Cu) (net 18))
(via (at 89.91 51.41) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 64.5 29) (end 64.5 25.06) (width 0.8) (layer F.Cu) (net 18))
(segment (start 64.5 25.06) (end 64.36 24.92) (width 0.8) (layer F.Cu) (net 18))
(segment (start 96 45) (end 96.649999 44.350001) (width 1.5) (layer B.Cu) (net 18))
(segment (start 96.649999 44.350001) (end 97.160001 44.350001) (width 1.5) (layer B.Cu) (net 18))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(via (at 82.8 47.555) (size 2.5) (drill 2) (layers F.Cu B.Cu) (net 18))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 58.5 34.19) (end 57.26 32.95) (width 0.25) (layer B.Cu) (net 18))
(segment (start 57.26 32.95) (end 56 32.95) (width 0.25) (layer B.Cu) (net 18))
(segment (start 30.5 50.2) (end 30.5 47) (width 0.6) (layer B.Cu) (net 18))
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(segment (start 54.5 31.65) (end 63.23 22.92) (width 0.8) (layer F.Cu) (net 19))
(segment (start 63.23 22.92) (end 64.36 22.92) (width 0.8) (layer F.Cu) (net 19))
(segment (start 56 31.05) (end 55.1 31.05) (width 0.4) (layer B.Cu) (net 19))
(segment (start 55.1 31.05) (end 54.5 31.65) (width 0.4) (layer B.Cu) (net 19))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 66.71 22.92) (end 68.29 24.5) (width 0.8) (layer F.Cu) (net 19))
(segment (start 68.29 24.5) (end 70.17 24.5) (width 0.8) (layer F.Cu) (net 19))
(segment (start 67.15 19.5) (end 67.15 20.35) (width 0.4) (layer F.Cu) (net 19))
(segment (start 67.15 20.35) (end 67.22 20.42) (width 0.4) (layer F.Cu) (net 19))
(segment (start 67.22 20.42) (end 67.22 22.41) (width 0.4) (layer F.Cu) (net 19))
(segment (start 66.71 22.92) (end 67.22 22.41) (width 0.4) (layer F.Cu) (net 19))
(segment (start 67.22 22.41) (end 67.22 19.81) (width 0.4) (layer F.Cu) (net 19))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(segment (start 64.36 22.92) (end 66.71 22.92) (width 0.8) (layer F.Cu) (net 19))
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(segment (start 58.5 36.73) (end 54.5 36.73) (width 0.8) (layer F.Cu) (net 20))
(segment (start 56 37.45) (end 55.22 37.45) (width 0.4) (layer B.Cu) (net 20))
(segment (start 55.22 37.45) (end 54.5 36.73) (width 0.4) (layer B.Cu) (net 20))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 68.75 29.4) (end 67.1 29.4) (width 0.4) (layer F.Cu) (net 20))
(segment (start 67.1 29.4) (end 65.5 31) (width 0.4) (layer F.Cu) (net 20))
(segment (start 65.5 31) (end 64.5 31) (width 0.4) (layer F.Cu) (net 20))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(segment (start 62.05 36.97) (end 62.05 33.45) (width 0.8) (layer F.Cu) (net 20))
(segment (start 62.05 33.45) (end 64.5 31) (width 0.8) (layer F.Cu) (net 20))
(segment (start 58.5 36.73) (end 61.81 36.73) (width 0.8) (layer F.Cu) (net 20))
(segment (start 61.81 36.73) (end 62.05 36.97) (width 0.8) (layer F.Cu) (net 20))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 41.56 34.62) (end 40.57 34.62) (width 0.25) (layer B.Cu) (net 21))
(segment (start 40.57 34.62) (end 40.45 34.5) (width 0.25) (layer B.Cu) (net 21))
(segment (start 43.1 34.575) (end 41.605 34.575) (width 0.25) (layer F.Cu) (net 21))
(segment (start 41.605 34.575) (end 41.56 34.62) (width 0.25) (layer F.Cu) (net 21))
(via (at 41.56 34.62) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 21))
(segment (start 46 33.05) (end 45.375 33.05) (width 0.25) (layer F.Cu) (net 22))
(segment (start 45.375 33.05) (end 45.15 33.275) (width 0.25) (layer F.Cu) (net 22))
(segment (start 45.15 33.275) (end 44.225 33.275) (width 0.25) (layer F.Cu) (net 22))
(segment (start 44.225 33.275) (end 43.1 33.275) (width 0.25) (layer F.Cu) (net 22))
(segment (start 44.88 31.64) (end 44.545 31.975) (width 0.25) (layer F.Cu) (net 23))
(segment (start 44.545 31.975) (end 43.1 31.975) (width 0.25) (layer F.Cu) (net 23))
(segment (start 42.5 31.55) (end 44.79 31.55) (width 0.25) (layer B.Cu) (net 23))
(segment (start 44.79 31.55) (end 44.88 31.64) (width 0.25) (layer B.Cu) (net 23))
(via (at 44.88 31.64) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 23))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 83 22.5) (end 81.55 22.5) (width 0.8) (layer F.Cu) (net 24))
(segment (start 81.55 22.5) (end 79.55 24.5) (width 0.8) (layer F.Cu) (net 24))
(segment (start 79.55 24.5) (end 77.5 24.5) (width 0.8) (layer F.Cu) (net 24))
(segment (start 75.25 24.5) (end 77.5 24.5) (width 0.8) (layer F.Cu) (net 24))
(segment (start 77.5 21.95) (end 77.5 23.35) (width 0.8) (layer F.Cu) (net 24))
(segment (start 77.5 23.35) (end 77.5 24.5) (width 0.8) (layer F.Cu) (net 24))
(segment (start 73.95 28) (end 73.95 25.8) (width 0.8) (layer F.Cu) (net 24))
(segment (start 73.95 25.8) (end 75.25 24.5) (width 0.8) (layer F.Cu) (net 24))
(segment (start 85.95 31.5) (end 85.95 30.3) (width 0.4) (layer F.Cu) (net 24))
(segment (start 85.95 30.3) (end 86 30.25) (width 0.4) (layer F.Cu) (net 24))
(segment (start 86 34.5) (end 86 30.25) (width 0.8) (layer F.Cu) (net 24))
(segment (start 85.95 29.75) (end 85.95 30.2) (width 0.4) (layer F.Cu) (net 24))
(segment (start 86 30.25) (end 86 24.05) (width 0.8) (layer F.Cu) (net 24))
(segment (start 85.95 30.2) (end 86 30.25) (width 0.4) (layer F.Cu) (net 24))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 88.09 34.54) (end 86.04 34.54) (width 0.4) (layer F.Cu) (net 24))
(segment (start 86.04 34.54) (end 86 34.5) (width 0.4) (layer F.Cu) (net 24))
(segment (start 90.86 36.52) (end 90.07 36.52) (width 0.4) (layer B.Cu) (net 24))
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(via (at 88.09 34.54) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 24))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 90.07 36.52) (end 88.09 34.54) (width 0.4) (layer B.Cu) (net 24))
(segment (start 86 24.05) (end 84.45 22.5) (width 0.8) (layer F.Cu) (net 24))
(segment (start 84.45 22.5) (end 83 22.5) (width 0.8) (layer F.Cu) (net 24))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(segment (start 98.044 54.78) (end 96.994 54.78) (width 0.6) (layer B.Cu) (net 25))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 96.994 54.78) (end 96.78 54.994) (width 0.6) (layer B.Cu) (net 25))
(segment (start 96.78 54.994) (end 96.78 57.398) (width 0.6) (layer B.Cu) (net 25))
(segment (start 96.78 57.398) (end 96.318 57.86) (width 0.6) (layer B.Cu) (net 25))
(segment (start 96.318 57.86) (end 80.062 57.86) (width 0.6) (layer B.Cu) (net 25))
(segment (start 80.062 57.86) (end 78.74 59.182) (width 0.6) (layer B.Cu) (net 25))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(segment (start 78.74 59.182) (end 72.39 59.182) (width 0.6) (layer B.Cu) (net 25))
(segment (start 72.39 59.182) (end 69.342 56.134) (width 0.6) (layer B.Cu) (net 25))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 73 36.2) (end 72.924 36.2) (width 0.4) (layer F.Cu) (net 25))
(segment (start 72.924 36.2) (end 72.644 36.48) (width 0.4) (layer F.Cu) (net 25))
(segment (start 72.644 36.48) (end 71.25 36.48) (width 0.8) (layer F.Cu) (net 25))
(segment (start 71.25 36.48) (end 70.4236 36.48) (width 0.8) (layer F.Cu) (net 25))
(segment (start 71.25 36.2) (end 71.25 36.48) (width 0.4) (layer F.Cu) (net 25))
(segment (start 69.5 36.2) (end 69.5 36.5364) (width 0.4) (layer F.Cu) (net 25))
(segment (start 69.5 36.5364) (end 69.9336 36.97) (width 0.4) (layer F.Cu) (net 25))
(segment (start 98.044 54.78) (end 98.044 53.244) (width 0.4) (layer B.Cu) (net 25))
(segment (start 98.044 53.244) (end 97.55 52.75) (width 0.4) (layer B.Cu) (net 25))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(segment (start 78 36.48) (end 75.946 36.48) (width 0.8) (layer F.Cu) (net 25))
(segment (start 75.946 36.48) (end 72.644 36.48) (width 0.8) (layer F.Cu) (net 25))
(segment (start 75.41 38.95) (end 75.41 37.1) (width 0.6) (layer F.Cu) (net 25))
(segment (start 75.41 37.1) (end 75.946 36.564) (width 0.6) (layer F.Cu) (net 25))
(segment (start 75.946 36.564) (end 75.946 36.48) (width 0.6) (layer F.Cu) (net 25))
(segment (start 69.342 56.134) (end 67.13 53.922) (width 0.6) (layer F.Cu) (net 25))
(segment (start 67.13 53.922) (end 67.13 36.97) (width 0.6) (layer F.Cu) (net 25))
(via (at 69.342 56.134) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 25))
(segment (start 70.4236 36.48) (end 69.9336 36.97) (width 0.8) (layer F.Cu) (net 25))
(segment (start 69.9336 36.97) (end 67.13 36.97) (width 0.8) (layer F.Cu) (net 25))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(segment (start 78.5 34.5) (end 78.5 35.98) (width 0.8) (layer F.Cu) (net 25))
(segment (start 78.5 35.98) (end 78 36.48) (width 0.8) (layer F.Cu) (net 25))
(segment (start 70.4236 36.48) (end 70.4036 36.5) (width 0.8) (layer F.Cu) (net 25))
(segment (start 70.5 36.4036) (end 70.4036 36.5) (width 0.4) (layer F.Cu) (net 25))
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(segment (start 90.86 38.87) (end 94 42.01) (width 0.4) (layer B.Cu) (net 26))
(segment (start 94 42.01) (end 94 42.25) (width 0.4) (layer B.Cu) (net 26))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 90.86 38.72) (end 90.86 38.87) (width 0.4) (layer B.Cu) (net 26))
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(segment (start 93.700001 42.549999) (end 94 42.25) (width 0.4) (layer F.Cu) (net 26))
(segment (start 93.05 48.5) (end 93.05 43.2) (width 0.4) (layer F.Cu) (net 26))
(segment (start 93.05 43.2) (end 93.700001 42.549999) (width 0.4) (layer F.Cu) (net 26))
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(via (at 94 42.25) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 26))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 94.095 50.8) (end 94.095 49.545) (width 0.4) (layer F.Cu) (net 26))
(segment (start 94.095 49.545) (end 93.05 48.5) (width 0.4) (layer F.Cu) (net 26))
(segment (start 92 50.55) (end 93.845 50.55) (width 0.4) (layer F.Cu) (net 26))
(segment (start 93.845 50.55) (end 94.095 50.8) (width 0.4) (layer F.Cu) (net 26))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 77.39 56.86) (end 76.48 55.95) (width 0.4) (layer F.Cu) (net 27))
(segment (start 76.48 55.95) (end 75.5 55.95) (width 0.4) (layer F.Cu) (net 27))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 79.82 54.43) (end 77.39 56.86) (width 0.4) (layer F.Cu) (net 27))
(segment (start 76.5 59) (end 76.5 57.75) (width 0.4) (layer F.Cu) (net 27))
(segment (start 76.5 57.75) (end 77.39 56.86) (width 0.4) (layer F.Cu) (net 27))
(segment (start 78.1 45.65) (end 79.475 45.65) (width 0.4) (layer F.Cu) (net 27))
(segment (start 79.475 45.65) (end 79.82 45.995) (width 0.4) (layer F.Cu) (net 27))
(segment (start 79.82 45.995) (end 79.82 54.43) (width 0.4) (layer F.Cu) (net 27))
(segment (start 85 59) (end 85 56.5) (width 0.4) (layer F.Cu) (net 28))
(segment (start 87.5 45.65) (end 86.125 45.65) (width 0.4) (layer F.Cu) (net 28))
(segment (start 85.92 52.66) (end 85.46 53.12) (width 0.4) (layer F.Cu) (net 28))
(segment (start 86.125 45.65) (end 85.92 45.855) (width 0.4) (layer F.Cu) (net 28))
(segment (start 85.46 53.12) (end 85.46 56.04) (width 0.4) (layer F.Cu) (net 28))
(segment (start 85.92 45.855) (end 85.92 52.66) (width 0.4) (layer F.Cu) (net 28))
(segment (start 85.46 56.04) (end 85 56.5) (width 0.4) (layer F.Cu) (net 28))
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(segment (start 84.435685 44.16) (end 83.87 44.16) (width 0.4) (layer B.Cu) (net 29))
(segment (start 94.34 44.16) (end 84.435685 44.16) (width 0.4) (layer B.Cu) (net 29))
(segment (start 96 42.5) (end 94.34 44.16) (width 0.4) (layer B.Cu) (net 29))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 83.75 39.25) (end 85.25 39.25) (width 0.8) (layer F.Cu) (net 29))
(segment (start 85.25 39.25) (end 86 38.5) (width 0.8) (layer F.Cu) (net 29))
(segment (start 83.75 39.25) (end 83.75 41.654998) (width 0.8) (layer B.Cu) (net 29))
(segment (start 83.75 38.5) (end 83.75 39.25) (width 0.8) (layer B.Cu) (net 29))
(via (at 83.75 39.25) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 29))
(segment (start 83.75 37.75) (end 85.25 37.75) (width 0.8) (layer F.Cu) (net 29))
(segment (start 85.25 37.75) (end 86 38.5) (width 0.8) (layer F.Cu) (net 29))
(segment (start 83.75 38.5) (end 83.75 37.75) (width 0.8) (layer B.Cu) (net 29))
(via (at 83.75 37.75) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 29))
(segment (start 82.47 42.934998) (end 83.684998 42.934998) (width 0.4) (layer F.Cu) (net 29))
(segment (start 83.684998 42.934998) (end 83.87 43.12) (width 0.4) (layer F.Cu) (net 29))
(segment (start 83.87 43.12) (end 83.87 44.16) (width 0.4) (layer F.Cu) (net 29))
(segment (start 78.1 44.38) (end 80.37 44.38) (width 0.4) (layer F.Cu) (net 29))
(segment (start 80.37 44.38) (end 81.815002 42.934998) (width 0.4) (layer F.Cu) (net 29))
(segment (start 81.815002 42.934998) (end 82.47 42.934998) (width 0.4) (layer F.Cu) (net 29))
(segment (start 83.75 41.654998) (end 82.47 42.934998) (width 0.8) (layer B.Cu) (net 29))
(segment (start 86 38.5) (end 83.75 38.5) (width 0.8) (layer F.Cu) (net 29))
(via (at 83.75 38.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 29))
(via (at 82.47 42.934998) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 29))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(segment (start 87.5 44.38) (end 87.38 44.26) (width 0.4) (layer F.Cu) (net 29))
(segment (start 87.38 44.26) (end 83.97 44.26) (width 0.4) (layer F.Cu) (net 29))
(segment (start 83.97 44.26) (end 83.87 44.16) (width 0.4) (layer F.Cu) (net 29))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 85 44) (end 84.03 44) (width 0.4) (layer B.Cu) (net 29))
(segment (start 84.03 44) (end 83.87 44.16) (width 0.4) (layer B.Cu) (net 29))
(segment (start 83.86 44.16) (end 83.87 44.16) (width 0.4) (layer B.Cu) (net 29))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(via (at 83.87 44.16) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 29))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(segment (start 98.044 56.98) (end 98.98 56.98) (width 0.6) (layer B.Cu) (net 30))
(segment (start 98.98 56.98) (end 99.75 56.21) (width 0.6) (layer B.Cu) (net 30))
(segment (start 98.044 56.98) (end 98.044 59.444) (width 0.6) (layer B.Cu) (net 30))
(segment (start 98.044 59.444) (end 98.1 59.5) (width 0.6) (layer B.Cu) (net 30))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 99.75 56.21) (end 100.99 56.21) (width 0.6) (layer F.Cu) (net 30))
(segment (start 100.99 56.21) (end 101.02 56.18) (width 0.6) (layer F.Cu) (net 30))
(segment (start 99.75 56.21) (end 97.915 56.21) (width 0.6) (layer F.Cu) (net 30))
(segment (start 97.915 56.21) (end 97.905 56.2) (width 0.6) (layer F.Cu) (net 30))
(via (at 99.75 56.21) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 30))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 72.33 41.83) (end 75.25 41.83) (width 0.4) (layer B.Cu) (net 31))
(segment (start 75.25 41.83) (end 81.235738 41.83) (width 0.4) (layer B.Cu) (net 31))
(segment (start 75.5 42.25) (end 75.200001 41.950001) (width 0.4) (layer B.Cu) (net 31))
(segment (start 75.200001 41.950001) (end 75.200001 41.879999) (width 0.4) (layer B.Cu) (net 31))
(segment (start 75.200001 41.879999) (end 75.25 41.83) (width 0.4) (layer B.Cu) (net 31))
(segment (start 75 41.84) (end 78.1 41.84) (width 0.4) (layer F.Cu) (net 31))
(segment (start 72.34 41.84) (end 75 41.84) (width 0.4) (layer F.Cu) (net 31))
(segment (start 75 41.84) (end 75.09 41.84) (width 0.4) (layer F.Cu) (net 31))
(segment (start 75.09 41.84) (end 75.5 42.25) (width 0.4) (layer F.Cu) (net 31))
(via (at 75.5 42.25) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 31))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(segment (start 79.41 38.95) (end 79.41 40.53) (width 0.6) (layer F.Cu) (net 31))
(segment (start 79.41 40.53) (end 78.1 41.84) (width 0.6) (layer F.Cu) (net 31))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(segment (start 81.245738 41.84) (end 81.3 41.84) (width 0.4) (layer B.Cu) (net 31))
(segment (start 81.235738 41.83) (end 81.245738 41.84) (width 0.4) (layer B.Cu) (net 31))
(segment (start 87.5 41.84) (end 81.3 41.84) (width 0.4) (layer F.Cu) (net 31))
(via (at 81.3 41.84) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 31))
(segment (start 80.935 41.83) (end 81.235738 41.83) (width 0.4) (layer B.Cu) (net 31))
(segment (start 79.71 43.055) (end 80.935 41.83) (width 0.4) (layer B.Cu) (net 31))
(segment (start 71.5 41) (end 72.33 41.83) (width 0.4) (layer B.Cu) (net 31))
(segment (start 79.71 43.28) (end 79.71 43.055) (width 0.4) (layer B.Cu) (net 31))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 72.34 41.84) (end 71.5 41) (width 0.4) (layer F.Cu) (net 31))
last changes. Stream out
2017-09-09 23:11:00 +02:00
(segment (start 38.5 56.5) (end 32.85 56.5) (width 0.6) (layer F.Cu) (net 32))
(segment (start 32.85 56.5) (end 32.71 56.36) (width 0.6) (layer F.Cu) (net 32))
(segment (start 36 56.5) (end 38.5 56.5) (width 0.6) (layer F.Cu) (net 32))
(segment (start 35.9 53.55) (end 38.5 53.55) (width 0.6) (layer F.Cu) (net 32))
(segment (start 38.5 53.55) (end 43.75 53.55) (width 0.6) (layer F.Cu) (net 32))
(segment (start 38.5 56.5) (end 38.5 55.05) (width 0.6) (layer F.Cu) (net 32))
(segment (start 38.5 55.05) (end 38.5 53.55) (width 0.6) (layer F.Cu) (net 32))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 35.9 53.55) (end 35.9 51.26066) (width 0.6) (layer F.Cu) (net 32))
(segment (start 43.75 53.55) (end 47.1 50.2) (width 0.6) (layer F.Cu) (net 32))
(segment (start 35.9 51.26066) (end 35.9 50.2) (width 0.6) (layer F.Cu) (net 32))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 22.52 29.04) (end 22.52 28.54) (width 0.25) (layer F.Cu) (net 34))
(segment (start 22.52 28.54) (end 22.56 28.5) (width 0.25) (layer F.Cu) (net 34))
(segment (start 22.56 28.5) (end 22.58 28.5) (width 0.25) (layer F.Cu) (net 34))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 20.44932 28.5) (end 22.58 28.5) (width 0.25) (layer F.Cu) (net 34))
(segment (start 22.58 28.5) (end 23.9 28.5) (width 0.25) (layer F.Cu) (net 34))
(segment (start 23.9 29.5) (end 22.98 29.5) (width 0.25) (layer B.Cu) (net 34))
(segment (start 22.98 29.5) (end 22.52 29.04) (width 0.25) (layer B.Cu) (net 34))
(via (at 22.52 29.04) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 34))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 20.44932 27.6999) (end 22.5501 27.6999) (width 0.25) (layer F.Cu) (net 35))
(segment (start 22.5501 27.6999) (end 23.75 26.5) (width 0.25) (layer F.Cu) (net 35))
(segment (start 23.75 26.5) (end 23.9 26.5) (width 0.25) (layer F.Cu) (net 35))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 28.3 50.2) (end 25 50.2) (width 0.6) (layer B.Cu) (net 36))
(segment (start 25 50.2) (end 24.5 50.7) (width 0.6) (layer B.Cu) (net 36))
(segment (start 28.3 50.2) (end 28.3 47) (width 0.6) (layer B.Cu) (net 36))
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(segment (start 90.75 36.5) (end 90.75 26.35) (width 0.6) (layer F.Cu) (net 40))
(segment (start 90.75 26.35) (end 95.8 21.3) (width 0.6) (layer F.Cu) (net 40))
(segment (start 100.19 37.09) (end 100.19 23.26) (width 0.6) (layer F.Cu) (net 41))
(segment (start 100.19 23.26) (end 102.15 21.3) (width 0.6) (layer F.Cu) (net 41))
last changes. Stream out
2017-09-09 23:11:00 +02:00
(segment (start 52.17 55.92) (end 58.320011 62.070011) (width 0.4) (layer F.Cu) (net 42))
(segment (start 58.320011 62.070011) (end 104.249989 62.070011) (width 0.4) (layer F.Cu) (net 42))
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(segment (start 104.249989 62.070011) (end 111.25 55.07) (width 0.4) (layer F.Cu) (net 42))
(segment (start 111.25 55.07) (end 111.25 45.75) (width 0.4) (layer F.Cu) (net 42))
(segment (start 111.25 45.75) (end 109.3 43.8) (width 0.4) (layer F.Cu) (net 42))
(segment (start 107.2 43.8) (end 105.5 45.5) (width 0.4) (layer F.Cu) (net 42))
(segment (start 109.3 43.8) (end 107.2 43.8) (width 0.4) (layer F.Cu) (net 42))
last changes. Stream out
2017-09-09 23:11:00 +02:00
(segment (start 52.17 55.92) (end 48.45 52.2) (width 0.4) (layer B.Cu) (net 42))
(segment (start 48.45 52.2) (end 42.63934 52.2) (width 0.4) (layer B.Cu) (net 42))
(segment (start 42.63934 52.2) (end 41.7 51.26066) (width 0.4) (layer B.Cu) (net 42))
(segment (start 41.7 51.26066) (end 41.7 50.2) (width 0.4) (layer B.Cu) (net 42))
(segment (start 52.1 55.92) (end 52.17 55.92) (width 0.4) (layer B.Cu) (net 42))
(via (at 52.17 55.92) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 42))
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(segment (start 53.58 53.91) (end 60.489989 60.819989) (width 0.4) (layer F.Cu) (net 43))
(segment (start 60.489989 60.819989) (end 102.870011 60.819989) (width 0.4) (layer F.Cu) (net 43))
(segment (start 102.870011 60.819989) (end 110.25 53.44) (width 0.4) (layer F.Cu) (net 43))
(segment (start 110.25 53.44) (end 110.25 46.75) (width 0.4) (layer F.Cu) (net 43))
(segment (start 110.25 46.75) (end 109 45.5) (width 0.4) (layer F.Cu) (net 43))
(segment (start 109 45.5) (end 108 45.5) (width 0.4) (layer F.Cu) (net 43))
last changes. Stream out
2017-09-09 23:11:00 +02:00
(segment (start 48.38 48.71) (end 53.280001 53.610001) (width 0.4) (layer B.Cu) (net 43))
(segment (start 53.280001 53.610001) (end 53.58 53.91) (width 0.4) (layer B.Cu) (net 43))
(segment (start 43.41 48.71) (end 48.38 48.71) (width 0.4) (layer B.Cu) (net 43))
(segment (start 41.7 47) (end 43.41 48.71) (width 0.4) (layer B.Cu) (net 43))
(via (at 53.58 53.91) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 43))
(segment (start 26.1 28.5) (end 27.37 28.5) (width 0.25) (layer F.Cu) (net 44))
(segment (start 27.37 28.5) (end 30.81 31.94) (width 0.25) (layer F.Cu) (net 44))
(segment (start 30.81 31.94) (end 35.865 31.94) (width 0.25) (layer F.Cu) (net 44))
(segment (start 35.865 31.94) (end 35.9 31.975) (width 0.25) (layer F.Cu) (net 44))
(segment (start 26.1 26.5) (end 26.25 26.5) (width 0.25) (layer F.Cu) (net 45))
(segment (start 26.25 26.5) (end 31.075 31.325) (width 0.25) (layer F.Cu) (net 45))
(segment (start 31.075 31.325) (end 35.9 31.325) (width 0.25) (layer F.Cu) (net 45))
(segment (start 95.55 54.54) (end 95.37 54.72) (width 0.4) (layer F.Cu) (net 46))
(segment (start 95.37 54.72) (end 95.37 56.195) (width 0.4) (layer F.Cu) (net 46))
(segment (start 95.37 56.195) (end 95.365 56.2) (width 0.4) (layer F.Cu) (net 46))
(segment (start 95.34 56.44) (end 95.34 54.75) (width 0.4) (layer B.Cu) (net 46))
(segment (start 95.34 54.75) (end 95.55 54.54) (width 0.4) (layer B.Cu) (net 46))
(via (at 95.55 54.54) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 46))
(segment (start 95.365 56.2) (end 95.365 58.265) (width 0.4) (layer F.Cu) (net 46))
(segment (start 95.365 58.265) (end 95.6 58.5) (width 0.4) (layer F.Cu) (net 46))
(segment (start 92.264262 59.38) (end 91.839998 59.38) (width 0.4) (layer F.Cu) (net 47))
(segment (start 92.37 59.38) (end 92.264262 59.38) (width 0.4) (layer F.Cu) (net 47))
(segment (start 93.25 58.5) (end 92.37 59.38) (width 0.4) (layer F.Cu) (net 47))
(segment (start 93.4 58.5) (end 93.25 58.5) (width 0.4) (layer F.Cu) (net 47))
(segment (start 91.809998 59.35) (end 91.839998 59.38) (width 0.4) (layer B.Cu) (net 47))
(segment (start 82.31 59.35) (end 91.809998 59.35) (width 0.4) (layer B.Cu) (net 47))
(via (at 91.839998 59.38) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 47))
(segment (start 81.885736 59.35) (end 82.31 59.35) (width 0.4) (layer F.Cu) (net 47))
(segment (start 80.85 59.35) (end 81.885736 59.35) (width 0.4) (layer F.Cu) (net 47))
(segment (start 80.5 59) (end 80.85 59.35) (width 0.4) (layer F.Cu) (net 47))
(via (at 82.31 59.35) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 47))
(segment (start 94.095 56.2) (end 94.095 57.805) (width 0.4) (layer F.Cu) (net 47))
(segment (start 94.095 57.805) (end 93.4 58.5) (width 0.4) (layer F.Cu) (net 47))
(segment (start 99.6 48.5) (end 99.6 46.65) (width 0.4) (layer B.Cu) (net 48))
(segment (start 99.6 46.65) (end 99.75 46.5) (width 0.4) (layer F.Cu) (net 48))
(segment (start 99.6 46.65) (end 99.75 46.5) (width 0.4) (layer B.Cu) (net 48))
(segment (start 99.6 48) (end 99.6 46.65) (width 0.4) (layer F.Cu) (net 48))
(via (at 99.75 46.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 48))
(segment (start 96.635 50.8) (end 96.635 49.895) (width 0.4) (layer F.Cu) (net 48))
(segment (start 96.635 49.895) (end 97.27 49.26) (width 0.4) (layer F.Cu) (net 48))
(segment (start 97.27 49.26) (end 99.02 49.26) (width 0.4) (layer F.Cu) (net 48))
(segment (start 99.02 49.26) (end 99.6 48.68) (width 0.4) (layer F.Cu) (net 48))
(segment (start 99.6 48.68) (end 99.6 48) (width 0.4) (layer F.Cu) (net 48))
(segment (start 95.365 50.8) (end 95.365 52.595) (width 0.4) (layer F.Cu) (net 49))
(segment (start 95.365 52.595) (end 93.91 54.05) (width 0.4) (layer F.Cu) (net 49))
(segment (start 93.91 54.05) (end 90.61 54.05) (width 0.4) (layer F.Cu) (net 49))
(segment (start 90.61 54.05) (end 88.96 55.7) (width 0.4) (layer F.Cu) (net 49))
(segment (start 88.96 55.7) (end 88.96 58.78) (width 0.4) (layer F.Cu) (net 49))
(segment (start 97.4 48) (end 95.365 50.035) (width 0.4) (layer F.Cu) (net 49))
(segment (start 95.365 50.035) (end 95.365 50.8) (width 0.4) (layer F.Cu) (net 49))
(segment (start 91 45.6) (end 91 46.9) (width 0.4) (layer F.Cu) (net 50))
(segment (start 91 46.9) (end 90 47.9) (width 0.4) (layer F.Cu) (net 50))
(segment (start 90 47.9) (end 89.02 46.92) (width 0.4) (layer F.Cu) (net 50))
(segment (start 89.02 46.92) (end 87.5 46.92) (width 0.4) (layer F.Cu) (net 50))
(segment (start 72.65 48.6) (end 72.25 49) (width 0.4) (layer F.Cu) (net 51))
(segment (start 72.25 49) (end 72.25 50.65) (width 0.4) (layer F.Cu) (net 51))
(segment (start 74 48.6) (end 72.65 48.6) (width 0.4) (layer F.Cu) (net 51))
(segment (start 78.1 46.92) (end 76.62 46.92) (width 0.4) (layer F.Cu) (net 51))
(segment (start 76.62 46.92) (end 74.94 48.6) (width 0.4) (layer F.Cu) (net 51))
(segment (start 74.94 48.6) (end 74 48.6) (width 0.4) (layer F.Cu) (net 51))
(segment (start 74.05 48.65) (end 74 48.6) (width 0.4) (layer F.Cu) (net 51))
(segment (start 78.1 43.11) (end 79.675 43.11) (width 0.6) (layer F.Cu) (net 52))
(segment (start 79.675 43.11) (end 79.97 42.815) (width 0.6) (layer F.Cu) (net 52))
(segment (start 79.97 42.815) (end 79.97 41.78) (width 0.6) (layer F.Cu) (net 52))
(segment (start 79.97 41.78) (end 81.25 40.5) (width 0.6) (layer F.Cu) (net 52))
(segment (start 81.25 40.5) (end 90.75 40.5) (width 0.6) (layer F.Cu) (net 52))
(segment (start 78.1 43.11) (end 75.49 43.11) (width 0.4) (layer F.Cu) (net 52))
(segment (start 75.49 43.11) (end 74 44.6) (width 0.4) (layer F.Cu) (net 52))
(segment (start 74 44.6) (end 74 46.4) (width 0.4) (layer F.Cu) (net 52))
(segment (start 96.19 37.09) (end 96.19 38.31) (width 0.6) (layer F.Cu) (net 53))
(segment (start 96.19 38.31) (end 91.1 43.4) (width 0.6) (layer F.Cu) (net 53))
(segment (start 91.1 43.4) (end 91 43.4) (width 0.6) (layer F.Cu) (net 53))
(segment (start 87.5 43.11) (end 90.71 43.11) (width 0.6) (layer F.Cu) (net 53))
(segment (start 90.71 43.11) (end 91 43.4) (width 0.6) (layer F.Cu) (net 53))
(segment (start 50.5 25) (end 50.5 25.51) (width 0.25) (layer F.Cu) (net 54))
(segment (start 50.5 25.51) (end 46.635 29.375) (width 0.25) (layer F.Cu) (net 54))
(segment (start 46.635 29.375) (end 44.225 29.375) (width 0.25) (layer F.Cu) (net 54))
(segment (start 44.225 29.375) (end 43.1 29.375) (width 0.25) (layer F.Cu) (net 54))
(segment (start 43.1 30.025) (end 50.475 30.025) (width 0.25) (layer F.Cu) (net 55))
(segment (start 50.475 30.025) (end 50.5 30) (width 0.25) (layer F.Cu) (net 55))
(segment (start 43.1 30.675) (end 47.275 30.675) (width 0.25) (layer F.Cu) (net 56))
(segment (start 50.5 33.9) (end 50.5 35) (width 0.25) (layer F.Cu) (net 56))
(segment (start 47.275 30.675) (end 50.5 33.9) (width 0.25) (layer F.Cu) (net 56))
(segment (start 50.5 20) (end 50.5 21.22) (width 0.25) (layer F.Cu) (net 60))
(segment (start 50.5 21.22) (end 44.295 27.425) (width 0.25) (layer F.Cu) (net 60))
(segment (start 44.295 27.425) (end 43.1 27.425) (width 0.25) (layer F.Cu) (net 60))
(segment (start 71.06892 19.5) (end 69.35 19.5) (width 0.4) (layer F.Cu) (net 61))
(segment (start 72.71 21.96) (end 72.71 19.84) (width 0.4) (layer F.Cu) (net 61))
(segment (start 72.71 19.84) (end 73.05 19.5) (width 0.4) (layer F.Cu) (net 61))
(segment (start 71.06892 19.5) (end 73.05 19.5) (width 0.4) (layer F.Cu) (net 61))
(segment (start 70.9 31.62) (end 68.77 31.62) (width 0.4) (layer F.Cu) (net 62))
(segment (start 68.77 31.62) (end 68.75 31.6) (width 0.4) (layer F.Cu) (net 62))
(segment (start 68.9 31.45) (end 68.75 31.6) (width 0.4) (layer F.Cu) (net 62))
(segment (start 64.59 34.43) (end 64.59 34.18108) (width 0.4) (layer F.Cu) (net 62))
(segment (start 64.59 34.18108) (end 67.17108 31.6) (width 0.4) (layer F.Cu) (net 62))
(segment (start 67.17108 31.6) (end 67.9 31.6) (width 0.4) (layer F.Cu) (net 62))
(segment (start 67.9 31.6) (end 68.75 31.6) (width 0.4) (layer F.Cu) (net 62))
(segment (start 47.1 47) (end 43.5 43.4) (width 0.4) (layer B.Cu) (net 63))
(segment (start 43.5 43.4) (end 43.5 43.1) (width 0.4) (layer B.Cu) (net 63))
(segment (start 35.9 47) (end 35.9 44.5) (width 0.4) (layer B.Cu) (net 64))
(segment (start 35.9 44.5) (end 35.5 44.1) (width 0.4) (layer B.Cu) (net 64))
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(segment (start 109 48) (end 108 48) (width 0.4) (layer B.Cu) (net 65))
last changes. Stream out
2017-09-09 23:11:00 +02:00
(segment (start 111 48.727208) (end 111 51.4) (width 0.4) (layer B.Cu) (net 65))
(segment (start 111 51.4) (end 109.5 52.9) (width 0.4) (layer B.Cu) (net 65))
(segment (start 109.5 52.9) (end 109.5 53.75) (width 0.4) (layer B.Cu) (net 65))
(segment (start 109 48) (end 110.272792 48) (width 0.4) (layer B.Cu) (net 65))
(segment (start 110.272792 48) (end 111 48.727208) (width 0.4) (layer B.Cu) (net 65))
(segment (start 96.635 56.2) (end 96.635 57.135) (width 0.4) (layer F.Cu) (net 66))
(segment (start 96.635 57.135) (end 97.25 57.75) (width 0.4) (layer F.Cu) (net 66))
(segment (start 97.25 57.75) (end 103.325736 57.75) (width 0.4) (layer F.Cu) (net 66))
(segment (start 103.325736 57.75) (end 105.575736 55.5) (width 0.4) (layer F.Cu) (net 66))
(segment (start 105.575736 55.5) (end 106 55.5) (width 0.4) (layer F.Cu) (net 66))
(segment (start 106 54.9) (end 106 55.5) (width 0.4) (layer B.Cu) (net 66))
(segment (start 107.15 53.75) (end 106 54.9) (width 0.4) (layer B.Cu) (net 66))
(segment (start 107.3 53.75) (end 107.15 53.75) (width 0.4) (layer B.Cu) (net 66))
(via (at 106 55.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 66))
(segment (start 109.08 37.5) (end 109.08 41.33) (width 0.4) (layer B.Cu) (net 66))
(segment (start 111.75 53.75) (end 110.5 55) (width 0.4) (layer B.Cu) (net 66))
(segment (start 109.08 41.33) (end 111.75 44) (width 0.4) (layer B.Cu) (net 66))
(segment (start 111.75 44) (end 111.75 53.75) (width 0.4) (layer B.Cu) (net 66))
(segment (start 110.5 55) (end 108 55) (width 0.4) (layer B.Cu) (net 66))
(segment (start 108 55) (end 107.3 54.3) (width 0.4) (layer B.Cu) (net 66))
(segment (start 107.3 54.3) (end 107.3 53.75) (width 0.4) (layer B.Cu) (net 66))
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(segment (start 102.85 49.75) (end 103.85 49.75) (width 0.4) (layer F.Cu) (net 67))
last changes. Stream out
2017-09-09 23:11:00 +02:00
(segment (start 103.85 49.75) (end 103.85 48.4) (width 0.4) (layer F.Cu) (net 67))
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(segment (start 103.85 48.4) (end 104.25 48) (width 0.4) (layer F.Cu) (net 67))
(segment (start 104.25 48) (end 105.5 48) (width 0.4) (layer F.Cu) (net 67))
(segment (start 100.65 49.75) (end 101 49.75) (width 0.4) (layer F.Cu) (net 68))
(segment (start 99.75 44.25) (end 99.75 41.75) (width 0.4) (layer F.Cu) (net 68))
(segment (start 101 49.75) (end 101 45.5) (width 0.4) (layer F.Cu) (net 68))
(segment (start 101 45.5) (end 99.75 44.25) (width 0.4) (layer F.Cu) (net 68))
(segment (start 99.75 41.75) (end 103.238001 38.261999) (width 0.4) (layer F.Cu) (net 68))
last changes. Stream out
2017-09-09 23:11:00 +02:00
(segment (start 103.238001 38.261999) (end 104 37.5) (width 0.4) (layer F.Cu) (net 68))
(segment (start 100.65 49.75) (end 99.6 50.8) (width 0.4) (layer F.Cu) (net 68))
(segment (start 99.6 50.8) (end 98.605 50.8) (width 0.4) (layer F.Cu) (net 68))
(segment (start 98.605 50.8) (end 97.905 50.8) (width 0.4) (layer F.Cu) (net 68))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(zone (net 1) (net_name Earth) (layer B.Cu) (tstamp 0) (hatch edge 0.508)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(connect_pads (clearance 0.3))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(min_thickness 0.25)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 13 13.5) (xy 51.75 13.5) (xy 51.75 40.4) (xy 60 40.4) (xy 60 46)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(xy 50.5 46) (xy 50.5 48.5) (xy 13 48.5)
)
)
(filled_polygon
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 13.5 26.473561) (xy 13.5 14) (xy 51.625 14)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
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(zone (net 18) (net_name GNDPWR) (layer B.Cu) (tstamp 0) (hatch edge 0.508)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(connect_pads (clearance 0.3))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(min_thickness 0.25)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 112 61.5) (xy 112 16) (xy 53 16) (xy 53 39.5) (xy 61.5 39.5)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
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add balance poti
2017-08-28 22:59:34 +02:00
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shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
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add balance poti
2017-08-28 22:59:34 +02:00
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last changes. Stream out
2017-09-09 23:11:00 +02:00
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shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
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last changes. Stream out
2017-09-09 23:11:00 +02:00
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shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 61.048632 29.134848) (xy 61 29.125) (xy 53.125 29.125) (xy 53.125 27.75) (xy 63.125 27.75)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 63.125 27.75) (xy 53.125 27.75) (xy 53.125 24.741547) (xy 63.064095 24.741547) (xy 63.094449 25.251052)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 63.134848 21.701368) (xy 63.125 21.75) (xy 63.125 24.56557) (xy 63.064095 24.741547) (xy 53.125 24.741547)
(xy 53.125 16.125) (xy 111.875 16.125)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
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Improve layout: Audio output
2017-08-17 04:33:41 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
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Improve layout: Audio output
2017-08-17 04:33:41 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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2017-09-09 23:31:40 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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2017-09-10 20:07:19 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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2017-09-09 23:31:40 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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2017-08-28 22:59:34 +02:00
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2017-09-09 23:31:40 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
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improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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2017-08-28 22:11:02 +02:00
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last changes. Stream out
2017-09-09 23:11:00 +02:00
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improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
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last changes. Stream out
2017-09-09 23:11:00 +02:00
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Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
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last changes. Stream out
2017-09-09 23:11:00 +02:00
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Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
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Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
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2017-08-17 04:24:37 +02:00
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improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
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Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
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(xy 22.138267 22.690731) (xy 21.959638 22.512103) (xy 21.726249 22.41543) (xy 20.63601 22.41543) (xy 20.47726 22.57418)
(xy 20.22326 22.57418) (xy 20.06451 22.41543) (xy 18.974271 22.41543) (xy 18.740882 22.512103) (xy 18.562253 22.690731)
(xy 18.46558 22.92412) (xy 16.73584 22.92412) (xy 16.639167 22.690731) (xy 16.460538 22.512103) (xy 16.227149 22.41543)
(xy 15.13691 22.41543) (xy 14.97816 22.57418) (xy 14.72416 22.57418) (xy 14.56541 22.41543) (xy 13.502 22.41543)
(xy 13.502 22.377) (xy 22.873 22.377)
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(zone (net 0) (net_name "") (layer F.Cu) (tstamp 5994FC9B) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(keepout (tracks allowed) (vias not_allowed) (copperpour not_allowed))
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(xy 100.75 41.5) (xy 103.75 41.5) (xy 103.75 45) (xy 100.75 45)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
(zone (net 0) (net_name "") (layer F.Cu) (tstamp 5994FCB0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
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(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(xy 100.75 51) (xy 100.75 54.5) (xy 103.75 54.5) (xy 103.75 51)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
)
)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(zone (net 0) (net_name "") (layer F.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.25)
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(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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(xy 56.75 61) (xy 52.25 56) (xy 53.75 54.25) (xy 54.75 54.75) (xy 56.25 56.25)
(xy 57.25 56.25)
)
)
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Layouted first draft
2017-06-09 00:41:36 +02:00
)
Reference in New Issue Copy Permalink