105 lines
3.0 KiB
C
105 lines
3.0 KiB
C
#include <stm32f0xx.h>
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static void __init_default_clocks(void)
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{
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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#if defined (STM32F051x8) || defined (STM32F058x8)
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/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
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RCC->CFGR &= (uint32_t)0xF8FFB80C;
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#else
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/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
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RCC->CFGR &= (uint32_t)0x08FFB80C;
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#endif /* STM32F051x8 or STM32F058x8 */
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
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RCC->CFGR &= (uint32_t)0xFFC0FFFF;
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/* Reset PREDIV[3:0] bits */
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RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
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#if defined (STM32F072xB) || defined (STM32F078xx)
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/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
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#elif defined (STM32F071xB)
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/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
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#elif defined (STM32F091xC) || defined (STM32F098xx)
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/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
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#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
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/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
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#elif defined (STM32F051x8) || defined (STM32F058xx)
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/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
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#elif defined (STM32F042x6) || defined (STM32F048xx)
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/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
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#elif defined (STM32F070x6) || defined (STM32F070xB)
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/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
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/* Set default USB clock to PLLCLK, since there is no HSI48 */
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RCC->CFGR3 |= (uint32_t)0x00000080;
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#else
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#warning "No target selected"
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#endif
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/* Reset HSI14 bit */
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RCC->CR2 &= (uint32_t)0xFFFFFFFE;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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}
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void __setup_clocks(void)
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{
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uint32_t tmp;
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/* Switch PLL source to HSE OSC */
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RCC->CFGR |= RCC_CFGR_PLLSRC;
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/* Divide HSE by 2 to match HSI */
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RCC->CFGR2 = 0x00000001;
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/* Enable HSE and wait for it to become ready */
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RCC->CR |= RCC_CR_HSEON;
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/* Wait for HSE to be ready */
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while (!(RCC->CR & RCC_CR_HSERDY));
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/* Set PLL multiplication to 12 (4 MHz * 12 = 48 MHz SysClk) */
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RCC->CFGR |= RCC_CFGR_PLLMUL_3 | RCC_CFGR_PLLMUL_1;
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/* HSI Already running. Switch on PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait for PLL to be ready */
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while (!(RCC->CR & RCC_CR_PLLRDY));
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/* Switch System Clock to PLL */
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tmp = RCC->CFGR;
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tmp &= ~0x3;
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tmp |= RCC_CFGR_SW_1;
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RCC->CFGR = tmp;
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/* Turn off HSI */
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RCC->CR &= ~RCC_CR_HSION;
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}
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void __system_init(void)
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{
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__init_default_clocks();
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__setup_clocks();
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}
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