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Config EEPROM CS Pull-Resistor #1

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opened 2021-05-17 20:15:24 +02:00 by mko · 0 comments
mko commented 2021-05-17 20:15:24 +02:00
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The FTDI config EEPROM has a pull-up on the chip select line, even though it is a high-active signal.

This is how FTDI specifies it in their example schematic, but it still seems wrong to me.

Feel free to reject, this is more food for thought than anything ;)

The FTDI config EEPROM has a pull-up on the chip select line, even though it is a high-active signal. This is how FTDI specifies it in their example schematic, but it still seems wrong to me. Feel free to reject, this is more food for thought than anything ;)
mhu closed this issue 2021-05-22 21:48:05 +02:00
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Reference: shimatta-team/shimatta-jtag-adapter#1
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