Config EEPROM CS Pull-Resistor #1
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Reference: shimatta-team/shimatta-jtag-adapter#1
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The FTDI config EEPROM has a pull-up on the chip select line, even though it is a high-active signal.
This is how FTDI specifies it in their example schematic, but it still seems wrong to me.
Feel free to reject, this is more food for thought than anything ;)