59 lines
1.2 KiB
VHDL
59 lines
1.2 KiB
VHDL
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library ieee;
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library design;
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use design.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity bench_led_demo is
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end entity bench_led_demo;
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architecture RTL of bench_led_demo is
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signal clk : std_logic;
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signal data_out : std_logic_vector(3 downto 0);
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signal rst_hw : std_logic;
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signal rmii_tx : std_logic_vector(1 downto 0);
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signal rmii_txen : std_logic;
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signal rmii_rx : std_logic_vector(1 downto 0);
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signal rmii_rxen : std_logic;
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signal mdc : std_logic_vector(1 downto 0);
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signal mdio : std_logic_vector(1 downto 0);
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begin
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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rmii_rx <= rmii_tx;
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rmii_rxen <= rmii_txen;
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rstegen : process is
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begin
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rst_hw <= '0';
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wait for 5 ns;
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rst_hw <= '1';
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wait;
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end process rstegen;
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leddemo_inst : entity design.leddemo
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port map(
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clk_tx => clk,
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clk_rx => clk,
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data_in => "1010",
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data_out => data_out,
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rst_hw => rst_hw,
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rmii_tx => rmii_tx,
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rmii_txen => rmii_txen,
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rmii_rx => rmii_rx,
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rmii_rxen => rmii_rxen,
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mdc => mdc,
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mdio => mdio
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);
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end architecture RTL;
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