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Make design MII compatible

This commit is contained in:
Mario Hüttel 2020-08-07 21:48:11 +02:00
parent a14dd6661e
commit 804ab415c3
9 changed files with 930 additions and 494 deletions
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3
.gitignore vendored
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@ -2,4 +2,5 @@
quartus
diamond
*.bak
sim/*
*.vhd~

82
bench/bench_ethmac_rx.vhd
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@ -2,7 +2,7 @@
-- Title : Bench for Ethernet RX Core
-- Project : EthMAC
-------------------------------------------------------------------------------
-- File : bench/bench_ethmac_rx.vhd
-- File : bench/bench_ethmac_rx.vhd
-- Author : Mario Hüttel <mario.huettel@gmx.net>
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@ -18,7 +18,7 @@
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
@ -37,22 +37,22 @@ entity bench_ethmac_rx is
end entity bench_ethmac_rx;
architecture RTL of bench_ethmac_rx is
signal clk_hw : std_logic;
signal rst_hw : std_logic;
signal dv_i : std_logic;
signal rxd_i : std_logic_vector(1 downto 0);
signal rst : std_logic;
signal clk_hw : std_logic;
signal rst_hw : std_logic;
signal dv_i : std_logic;
signal rxd_i : std_logic_vector(1 downto 0);
signal rst : std_logic;
signal start_of_frame : std_logic;
signal end_of_frame : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(7 downto 0);
signal data_strb : std_logic;
signal crc_check_valid : std_logic;
signal clock_fcs : std_logic;
signal crc : std_logic_vector(7 downto 0);
signal dvalid : std_logic;
signal calc : std_logic;
signal fcs_init : std_logic;
signal fcs_dat : std_logic_vector(7 downto 0);
signal crc : std_logic_vector(7 downto 0);
signal dvalid : std_logic;
signal calc : std_logic;
signal fcs_init : std_logic;
signal fcs_dat : std_logic_vector(7 downto 0);
begin
rst <= not rst_hw;
@ -66,29 +66,33 @@ begin
end process clock_driver;
ethmac_rx_inst : entity design.ethmac_rx
port map(
clk_50 => clk_hw,
rst => rst,
rmii_rx => rxd_i,
rmii_dv => dv_i,
start_of_frame => start_of_frame,
end_of_frame => end_of_frame,
data_out => data_out,
data_strb => data_strb,
crc_check_valid => crc_check_valid
generic map (
IFACE_WIDTH => 2);
port map(
clk_50 => clk_hw,
rst => rst,
rmii_rx => rxd_i,
rmii_dv => dv_i,
start_of_frame => start_of_frame,
end_of_frame => end_of_frame,
data_out => data_out,
data_strb => data_strb,
crc_check_valid => crc_check_valid
);
ethfcs_inst : entity design.ethfcs
port map(
CLOCK => clock_fcs,
RESET => rst,
DATA => fcs_dat,
LOAD_INIT => fcs_init,
CALC => calc,
D_VALID => dvalid,
CRC => crc,
CRC_REG => open,
CRC_VALID => open
generic map (
IFACE_WIDTH => 2);
port map(
CLOCK => clock_fcs,
RESET => rst,
DATA => fcs_dat,
LOAD_INIT => fcs_init,
CALC => calc,
D_VALID => dvalid,
CRC => crc,
CRC_REG => open,
CRC_VALID => open
);
sendphy : process is
@ -106,13 +110,13 @@ begin
end procedure sendRMII;
begin
rst_hw <= '0';
dv_i <= '0';
rxd_i <= "00";
calc <= '0';
fcs_dat <= x"00";
rst_hw <= '0';
dv_i <= '0';
rxd_i <= "00";
calc <= '0';
fcs_dat <= x"00";
wait for 2 ns;
rst_hw <= '1';
rst_hw <= '1';
fcs_init <= '1';
wait for 50 ns;
fcs_init <= '0';

744
bench/bench_ethmac_tx_rx_mii.vhd Normal file
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@ -0,0 +1,744 @@
-------------------------------------------------------------------------------
-- Title : Bench for Ethernet TX and RX Core
-- Project : EthMAC
-------------------------------------------------------------------------------
-- File : design/ethmac_tx_rx.vhd
-- Author : Mario Hüttel <mario.huettel@gmx.net>
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Testbench for communication between TX and RX core.
-------------------------------------------------------------------------------
-- Copyright (c) 2016
--
-- This file is part of EthMAC.
--
-- EthMAC is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 2 of the License.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library ieee;
library design;
use design.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bench_ethmac_tx_rx_mii is
end entity bench_ethmac_tx_rx_mii;
architecture bench of bench_ethmac_tx_rx_mii is
signal clk : std_logic;
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal end_of_frame : std_logic := '0';
signal data_ack : std_logic;
signal start_of_frame : std_logic := '0';
signal rst : std_logic;
signal tx_ready : std_logic;
signal rmii_tx : std_logic_vector(3 downto 0);
signal rmii_txen : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_strb : std_logic;
signal crc_check_valid : std_logic;
signal end_of_frame_rx : std_logic;
signal start_of_frame_rx : std_logic;
begin
clock_driver : process
constant period : time := 40 ns;
begin
clk <= '0';
wait for period / 2;
clk <= '1';
wait for period / 2;
end process clock_driver;
ethmac_tx_inst : entity design.ethmac_tx
generic map(
IFACE_WIDTH => 4)
port map(
clk_50 => clk,
rst => rst,
tx_ready => tx_ready,
start_of_frame => start_of_frame,
end_of_frame => end_of_frame,
data_in => data_in,
data_ack => data_ack,
abort => '0',
rmii_tx => rmii_tx,
rmii_txen => rmii_txen
);
ethmac_rx_inst : entity design.ethmac_rx
generic map(
IFACE_WIDTH => 4)
port map(
clk_50 => clk,
rst => rst,
rmii_rx => rmii_tx,
rmii_dv => rmii_txen,
start_of_frame => start_of_frame_rx,
end_of_frame => end_of_frame_rx,
data_out => data_out,
data_strb => data_strb,
crc_check_valid => crc_check_valid
);
sendpkg : process is
procedure sendByte(byte : std_logic_vector(7 downto 0); last : std_logic) is
begin
wait until rising_edge(clk);
data_in <= byte;
end_of_frame <= last;
wait until data_ack = '1';
end procedure sendByte;
begin
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 20 ns;
start_of_frame <= '1';
sendByte(x"FF", '0');
start_of_frame <= '0';
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '1');
wait for 100 ns;
end_of_frame <= '0';
wait for 1 us;
start_of_frame <= '1';
sendByte(x"FF", '0');
start_of_frame <= '0';
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '1');
wait for 100 ns;
end_of_frame <= '0';
wait for 1 us;
start_of_frame <= '1';
sendByte(x"FF", '0');
start_of_frame <= '0';
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '1');
wait for 100 ns;
end_of_frame <= '0';
wait for 1 us;
start_of_frame <= '1';
sendByte(x"FF", '0');
start_of_frame <= '0';
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '1');
wait;
end process sendpkg;
end architecture bench;

63
bench_ethmac_rx.gtkw
View File

@ -1,63 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
[*] Tue Jan 31 10:51:17 2017
[*]
[dumpfile] "/tmp/SigasiCompileCache5252176646134126361/ethmac/mentor/bench_ethmac_rx.ghw"
[dumpfile_mtime] "Tue Jan 31 10:48:01 2017"
[dumpfile_size] 18590
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_ethmac_rx.gtkw"
[timestart] 0
[size] 2880 1508
[pos] -1 -1
*-26.724226 2752900000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.bench_ethmac_rx.
[treeopen] top.bench_ethmac_rx.ethmac_rx_inst.
[treeopen] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo.
[treeopen] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.
[sst_width] 287
[signals_width] 283
[sst_expanded] 1
[sst_vpaned_height] 445
@28
top.bench_ethmac_rx.rst
top.bench_ethmac_rx.end_of_frame
top.bench_ethmac_rx.start_of_frame
top.bench_ethmac_rx.clk_hw
top.bench_ethmac_rx.dv_i
top.bench_ethmac_rx.crc_check_valid
#{top.bench_ethmac_rx.rxd_i[1:0]} top.bench_ethmac_rx.rxd_i[1] top.bench_ethmac_rx.rxd_i[0]
top.bench_ethmac_rx.ethmac_rx_inst.framestate
@200
-
-
-
@28
top.bench_ethmac_rx.data_strb
@22
#{top.bench_ethmac_rx.data_out[7:0]} top.bench_ethmac_rx.data_out[7] top.bench_ethmac_rx.data_out[6] top.bench_ethmac_rx.data_out[5] top.bench_ethmac_rx.data_out[4] top.bench_ethmac_rx.data_out[3] top.bench_ethmac_rx.data_out[2] top.bench_ethmac_rx.data_out[1] top.bench_ethmac_rx.data_out[0]
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][0]
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][0]
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][0]
@28
top.bench_ethmac_rx.ethmac_rx_inst.data_delay_truncate
top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in_strb
@22
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[0]
@200
-
@29
top.bench_ethmac_rx.clk_hw
@200
-
@28
top.bench_ethmac_rx.ethmac_rx_inst.crc_data_valid
top.bench_ethmac_rx.ethmac_rx_inst.crc_calc_en
top.bench_ethmac_rx.ethmac_rx_inst.crc_init
top.bench_ethmac_rx.ethmac_rx_inst.crc_valid
top.bench_ethmac_rx.ethmac_rx_inst.crc_check_valid
@22
#{top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[7:0]} top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[7] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[6] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[5] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[4] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[3] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[2] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[1] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[0]
#{top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31:0]} top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
[pattern_trace] 1
[pattern_trace] 0

42
bench_ethmac_tx.gtkw
View File

@ -1,42 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
[*] Tue Jan 31 17:38:47 2017
[*]
[dumpfile] "/tmp/SigasiCompileCache7754218395000362562/ethmac/mentor/bench_ethmac_tx.ghw"
[dumpfile_mtime] "Tue Jan 31 17:37:54 2017"
[dumpfile_size] 13513
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_ethmac_tx.gtkw"
[timestart] 489830000
[size] 2880 1508
[pos] -1 -1
*-23.703266 1550000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.bench_ethmac_tx.
[treeopen] top.bench_ethmac_tx.ethmac_tx_inst.
[sst_width] 287
[signals_width] 250
[sst_expanded] 1
[sst_vpaned_height] 445
@28
top.bench_ethmac_tx.rst
@29
top.bench_ethmac_tx.clk
@28
#{top.bench_ethmac_tx.rmii_tx[1:0]} top.bench_ethmac_tx.rmii_tx[1] top.bench_ethmac_tx.rmii_tx[0]
top.bench_ethmac_tx.tx_ready
top.bench_ethmac_tx.rmii_txen
top.bench_ethmac_tx.abort
top.bench_ethmac_tx.ethmac_tx_inst.tx_state
top.bench_ethmac_tx.ethmac_tx_inst.byte_counter_disable
top.bench_ethmac_tx.ethmac_tx_inst.byte_counter
@200
-
-
@28
top.bench_ethmac_tx.ethmac_tx_inst.crc_init
top.bench_ethmac_tx.ethmac_tx_inst.crc_calc
top.bench_ethmac_tx.ethmac_tx_inst.crc_data_valid
@22
#{top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[7:0]} top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[7] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[6] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[5] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[4] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[3] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[2] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[1] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[0]
[pattern_trace] 1
[pattern_trace] 0

130
bench_ethmac_tx_rx.gtkw
View File

@ -1,130 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
[*] Wed Feb 1 16:36:58 2017
[*]
[dumpfile] "/tmp/SigasiCompileCache2061063648462684657/ethmac/mentor/bench_ethmac_tx_rx.ghw"
[dumpfile_mtime] "Wed Feb 1 16:34:58 2017"
[dumpfile_size] 313392
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_ethmac_tx_rx.gtkw"
[timestart] 46144000000
[size] 2880 1508
[pos] -1 -1
*-26.708954 46844900000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.bench_ethmac_tx_rx.
[treeopen] top.bench_ethmac_tx_rx.ethmac_rx_inst.
[treeopen] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo.
[treeopen] top.bench_ethmac_tx_rx.ethmac_tx_inst.
[sst_width] 287
[signals_width] 283
[sst_expanded] 1
[sst_vpaned_height] 445
@28
top.bench_ethmac_tx_rx.clk
top.bench_ethmac_tx_rx.start_of_frame_rx
top.bench_ethmac_tx_rx.end_of_frame_rx
top.bench_ethmac_tx_rx.crc_check_valid
top.bench_ethmac_tx_rx.ethmac_rx_inst.framestate
top.bench_ethmac_tx_rx.data_strb
@22
#{top.bench_ethmac_tx_rx.data_out[7:0]} top.bench_ethmac_tx_rx.data_out[7] top.bench_ethmac_tx_rx.data_out[6] top.bench_ethmac_tx_rx.data_out[5] top.bench_ethmac_tx_rx.data_out[4] top.bench_ethmac_tx_rx.data_out[3] top.bench_ethmac_tx_rx.data_out[2] top.bench_ethmac_tx_rx.data_out[1] top.bench_ethmac_tx_rx.data_out[0]
@200
-
@22
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][0]
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][0]
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][0]
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][0]
@28
top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_truncate
top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_in_strb
@200
-
-
@28
top.bench_ethmac_tx_rx.start_of_frame
top.bench_ethmac_tx_rx.end_of_frame
@22
#{top.bench_ethmac_tx_rx.data_in[7:0]} top.bench_ethmac_tx_rx.data_in[7] top.bench_ethmac_tx_rx.data_in[6] top.bench_ethmac_tx_rx.data_in[5] top.bench_ethmac_tx_rx.data_in[4] top.bench_ethmac_tx_rx.data_in[3] top.bench_ethmac_tx_rx.data_in[2] top.bench_ethmac_tx_rx.data_in[1] top.bench_ethmac_tx_rx.data_in[0]
@28
top.bench_ethmac_tx_rx.data_ack
top.bench_ethmac_tx_rx.ethmac_tx_inst.tx_state
@22
#{top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[7:0]} top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[7] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[6] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[5] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[4] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[3] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[2] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[1] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[0]
@28
top.bench_ethmac_tx_rx.tx_ready
@200
-
@29
top.bench_ethmac_tx_rx.rst
@28
top.bench_ethmac_tx_rx.clk
#{top.bench_ethmac_tx_rx.rmii_tx[1:0]} top.bench_ethmac_tx_rx.rmii_tx[1] top.bench_ethmac_tx_rx.rmii_tx[0]
top.bench_ethmac_tx_rx.rmii_txen
@200
-
-
@28
top.bench_ethmac_tx_rx.ethmac_tx_inst.crc_init
top.bench_ethmac_tx_rx.ethmac_tx_inst.crc_data_valid
top.bench_ethmac_tx_rx.ethmac_tx_inst.crc_calc
@200
-
-
@800022
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[31:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[31] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[30] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[29] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[28] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[27] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[26] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[25] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[24] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[23] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[22] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[21] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[20] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[19] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[18] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[17] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[16] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[15] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[14] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[13] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[12] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[11] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[10] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[9] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[8] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[0]
@28
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[31]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[30]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[29]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[28]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[27]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[26]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[25]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[24]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[23]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[22]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[21]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[20]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[19]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[18]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[17]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[16]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[15]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[14]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[13]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[12]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[11]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[10]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[9]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[8]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[7]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[6]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[5]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[4]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[3]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[2]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[1]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[0]
@1001200
-group_end
@22
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
@c00022
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[0]
@28
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[7]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[6]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[5]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[4]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[3]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[2]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[1]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[0]
@1401200
-group_end
@22
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[31:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[31] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[30] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[29] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[28] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[27] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[26] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[25] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[24] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[23] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[22] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[21] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[20] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[19] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[18] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[17] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[16] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[15] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[14] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[13] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[12] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[11] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[10] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[9] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[8] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[0]
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[0]
[pattern_trace] 1
[pattern_trace] 0

93
bench_led_demo.gtkw
View File

@ -1,93 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
[*] Tue Feb 7 21:51:10 2017
[*]
[dumpfile] "(null)"
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_led_demo.gtkw"
[timestart] 103800000000
[size] 1920 1016
[pos] -1 -1
*-30.954296 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.bench_led_demo.
[treeopen] top.bench_led_demo.leddemo_inst.
[treeopen] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.
[treeopen] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.
[treeopen] top.bench_led_demo.leddemo_inst.ethmac_tx_inst.
[sst_width] 289
[signals_width] 150
[sst_expanded] 1
[sst_vpaned_height] 284
@28
#{top.bench_led_demo.rmii_rx[1:0]} top.bench_led_demo.rmii_rx[1] top.bench_led_demo.rmii_rx[0]
@22
#{top.bench_led_demo.data_out[3:0]} top.bench_led_demo.data_out[3] top.bench_led_demo.data_out[2] top.bench_led_demo.data_out[1] top.bench_led_demo.data_out[0]
@28
#{top.bench_led_demo.mdc[1:0]} top.bench_led_demo.mdc[1] top.bench_led_demo.mdc[0]
top.bench_led_demo.clk
top.bench_led_demo.leddemo_inst.rst_rxtx
top.bench_led_demo.leddemo_inst.initstate
@200
-
-
-RX Module
@28
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.crc_valid
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.end_of_frame
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.start_of_frame
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.rmii_dv
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_strb
@22
#{top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[7:0]} top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[7] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[6] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[5] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[4] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[3] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[2] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[1] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[0]
@200
-
-
-TX Module
@22
#{top.bench_led_demo.leddemo_inst.tx_data[7:0]} top.bench_led_demo.leddemo_inst.tx_data[7] top.bench_led_demo.leddemo_inst.tx_data[6] top.bench_led_demo.leddemo_inst.tx_data[5] top.bench_led_demo.leddemo_inst.tx_data[4] top.bench_led_demo.leddemo_inst.tx_data[3] top.bench_led_demo.leddemo_inst.tx_data[2] top.bench_led_demo.leddemo_inst.tx_data[1] top.bench_led_demo.leddemo_inst.tx_data[0]
@28
top.bench_led_demo.leddemo_inst.tx_sof
top.bench_led_demo.leddemo_inst.tx_eof
top.bench_led_demo.leddemo_inst.tx_ack
top.bench_led_demo.leddemo_inst.tx_state
top.bench_led_demo.leddemo_inst.clk_tx
top.bench_led_demo.leddemo_inst.ethmac_tx_inst.tx_state
@800023
#{top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31:0]} top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
@29
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
@1001201
-group_end
[pattern_trace] 1
[pattern_trace] 0

124
design/ehtmac_rx.vhd
View File

@ -2,7 +2,7 @@
-- Title : Ethernet RX Core
-- Project : EthMAC
-------------------------------------------------------------------------------
-- File : design/ethmac_rx.vhd
-- File : design/ethmac_rx.vhd
-- Author : Mario Hüttel <mario.huettel@gmx.net>
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@ -18,7 +18,7 @@
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
@ -33,32 +33,38 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ethmac_rx is
generic(
IFACE_WIDTH : natural := 2);
port(
clk_50 : in std_logic;
rst : in std_logic;
rmii_rx : in std_logic_vector(1 downto 0);
rmii_dv : in std_logic;
start_of_frame : out std_logic;
end_of_frame : out std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strb : out std_logic;
clk_50 : in std_logic;
rst : in std_logic;
rmii_rx : in std_logic_vector(IFACE_WIDTH - 1 downto 0);
rmii_dv : in std_logic;
start_of_frame : out std_logic;
end_of_frame : out std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strb : out std_logic;
crc_check_valid : out std_logic
);
);
end entity ethmac_rx;
architecture RTL of ethmac_rx is
constant DIBIT_COUNT : natural := 8 / IFACE_WIDTH;
type ethstate_t is (ETH_INIT, ETH_PREAMBLE, ETH_DATA);
signal framestate : ethstate_t;
signal crc_data_in : std_logic_vector(7 downto 0);
signal crc_init : std_logic;
signal crc_calc_en : std_logic;
signal crc_data_valid : std_logic;
signal crc_valid : std_logic;
signal dibit_counter : integer range 0 to 3 := 0;
signal data_delay_in : std_logic_vector(7 downto 0);
signal framestate : ethstate_t;
signal crc_data_in : std_logic_vector(7 downto 0);
signal crc_init : std_logic;
signal crc_calc_en : std_logic;
signal crc_data_valid : std_logic;
signal crc_valid : std_logic;
signal dibit_counter : integer range 0 to (DIBIT_COUNT - 1) := 0;
signal data_delay_in : std_logic_vector(7 downto 0);
signal data_delay_in_strb : std_logic;
signal data_delay_truncate : std_logic;
signal end_of_frame_s : std_logic;
signal end_of_frame_s : std_logic;
type data_fifo_t is array (0 to 3) of std_logic_vector(7 downto 0);
signal data_delay_fifo : data_fifo_t;
@ -68,14 +74,14 @@ architecture RTL of ethmac_rx is
begin
ethfcs_inst : entity work.ethfcs
port map(
CLOCK => clk_50,
RESET => rst,
DATA => crc_data_in,
CLOCK => clk_50,
RESET => rst,
DATA => crc_data_in,
LOAD_INIT => crc_init,
CALC => crc_calc_en,
D_VALID => crc_data_valid,
CRC => open,
CRC_REG => open,
CALC => crc_calc_en,
D_VALID => crc_data_valid,
CRC => open,
CRC_REG => open,
CRC_VALID => crc_valid);
rx_framefsm : process(clk_50, rst) is
@ -83,63 +89,63 @@ begin
begin
if rst = '1' then
framestate <= ETH_INIT;
dibit_counter <= 0;
recv_byte := (others => '0');
crc_calc_en <= '0';
framestate <= ETH_INIT;
dibit_counter <= 0;
recv_byte := (others => '0');
crc_calc_en <= '0';
data_delay_truncate <= '0';
data_delay_in_strb <= '0';
data_delay_in <= (others => '0');
crc_init <= '0';
crc_data_in <= (others => '0');
crc_data_valid <= '0';
crc_calc_en <= '0';
start_of_frame <= '0';
end_of_frame_s <= '0';
data_delay_in <= (others => '0');
crc_init <= '0';
crc_data_in <= (others => '0');
crc_data_valid <= '0';
crc_calc_en <= '0';
start_of_frame <= '0';
end_of_frame_s <= '0';
elsif rising_edge(clk_50) then
end_of_frame_s <= '0';
crc_calc_en <= '0';
start_of_frame <= '0';
end_of_frame_s <= '0';
crc_calc_en <= '0';
start_of_frame <= '0';
data_delay_truncate <= '0';
data_delay_in_strb <= '0';
crc_init <= '0';
crc_data_valid <= '0';
if dibit_counter = 3 then
crc_init <= '0';
crc_data_valid <= '0';
if dibit_counter = DIBIT_COUNT - 1 then
dibit_counter <= 0;
else
dibit_counter <= dibit_counter + 1;
end if;
-- input data shift register (LSB first)
recv_byte := rmii_rx & recv_byte(7 downto 2);
recv_byte := rmii_rx & recv_byte(7 downto IFACE_WIDTH);
case framestate is
when ETH_INIT =>
if rmii_dv = '0' then -- Wait for inter frame gap for sync
if rmii_dv = '0' then -- Wait for inter frame gap for sync
crc_init <= '1';
framestate <= ETH_PREAMBLE;
end if;
when ETH_PREAMBLE =>
if rmii_dv = '1' and rmii_rx = "11" then -- Data valid and last dibit of preamble recieved
-- reset dibit counter
if rmii_dv = '1' and rmii_rx(rmii_rx'left downto rmii_rx'left - 1) = "11" then -- Data valid and last dibit of preamble recieved
-- reset dibit counter
dibit_counter <= 0;
start_of_frame <= '1';
framestate <= ETH_DATA;
-- crc_init <= '1';
-- crc_init <= '1';
end if;
when ETH_DATA =>
crc_calc_en <= '1';
if rmii_dv = '1' then
if dibit_counter = 3 then -- Data word received
data_delay_in <= recv_byte;
if dibit_counter = DIBIT_COUNT -1 then -- Data word received
data_delay_in <= recv_byte;
data_delay_in_strb <= '1';
crc_data_in <= recv_byte;
crc_data_valid <= '1';
crc_data_in <= recv_byte;
crc_data_valid <= '1';
end if;
else
framestate <= ETH_INIT;
end_of_frame_s <= '1';
crc_calc_en <= '0';
framestate <= ETH_INIT;
end_of_frame_s <= '1';
crc_calc_en <= '0';
data_delay_truncate <= '1';
end if;
end case;
@ -147,7 +153,7 @@ begin
end if;
end process rx_framefsm;
data_delay : process(rst, clk_50) is -- This implements a four byte big delay buffer/FIFO used for removing the crc
data_delay : process(rst, clk_50) is -- This implements a four byte big delay buffer/FIFO used for removing the crc
variable data_count : integer range 0 to 4 := 0;
begin
if rst = '1' then
@ -161,7 +167,7 @@ begin
elsif rising_edge(clk_50) then
data_strb <= '0';
if data_delay_truncate = '1' then
data_count := 0; -- resetting counter is enough. FIFO itself has not to be cleared
data_count := 0; -- resetting counter is enough. FIFO itself has not to be cleared
elsif data_delay_in_strb = '1' then
data_delay_fifo(0) <= data_delay_in;
for i in 3 downto 1 loop
@ -170,7 +176,7 @@ begin
if data_count < 4 then
data_count := data_count + 1;
else -- Enable output
else -- Enable output
data_out <= data_delay_fifo(3);
data_strb <= '1';
end if;

143
design/ethmac_tx.vhd
View File

@ -2,7 +2,7 @@
-- Title : Ethernet TX Core
-- Project : EthMAC
-------------------------------------------------------------------------------
-- File : design/ethmac_tx.vhd
-- File : design/ethmac_tx.vhd
-- Author : Mario Hüttel <mario.huettel@gmx.net>
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@ -18,7 +18,7 @@
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
@ -33,50 +33,57 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ethmac_tx is
generic(
IFACE_WIDTH : natural := 2);
port(
clk_50 : in std_logic;
rst : in std_logic;
clk_50 : in std_logic;
rst : in std_logic;
tx_ready : out std_logic;
start_of_frame : in std_logic;
end_of_frame : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_ack : out std_logic;
abort : in std_logic;
abort : in std_logic;
--- RMII Interface
rmii_tx : out std_logic_vector(1 downto 0);
rmii_tx : out std_logic_vector(IFACE_WIDTH -1 downto 0);
rmii_txen : out std_logic
);
);
end entity ethmac_tx;
architecture RTL of ethmac_tx is
constant DIBIT_COUNT : natural := 8 / IFACE_WIDTH;
constant PREAMBLE_BYTE : std_logic_vector(7 downto 0) := x"55";
constant PREAMBLE_SFD : std_logic_vector(7 downto 0) := x"D5";
type eth_tx_state_t is (INIT, PREAMBLE, DATA, CRC, IPG);
signal crc_data_in : std_logic_vector(7 downto 0);
signal crc_init : std_logic;
signal crc_init : std_logic;
signal crc_data_out : std_logic_vector(7 downto 0);
signal crc_data_valid : std_logic;
signal crc_calc : std_logic;
signal dibit_counter : integer range 0 to 3 := 0;
signal byte_counter : integer range 0 to 15 := 0;
signal tx_state : eth_tx_state_t;
signal crc_calc : std_logic;
signal dibit_counter : integer range 0 to DIBIT_COUNT - 1 := 0;
signal byte_counter : integer range 0 to 15 := 0;
signal tx_state : eth_tx_state_t;
signal data_reg : std_logic_vector(7 downto 0);
signal eof_reg : std_logic;
signal data_reg : std_logic_vector(7 downto 0);
signal eof_reg : std_logic;
signal byte_counter_disable : std_logic;
begin
ethfcs_inst : entity work.ethfcs
port map(
CLOCK => clk_50,
RESET => rst,
DATA => crc_data_in,
CLOCK => clk_50,
RESET => rst,
DATA => crc_data_in,
LOAD_INIT => crc_init,
CALC => crc_calc,
D_VALID => crc_data_valid,
CRC => crc_data_out,
CRC_REG => open,
CALC => crc_calc,
D_VALID => crc_data_valid,
CRC => crc_data_out,
CRC_REG => open,
CRC_VALID => open
);
);
eth_tx_fsm : process(clk_50, rst) is
begin
@ -88,7 +95,7 @@ begin
dibit_counter <= 0;
byte_counter <= 0;
rmii_txen <= '0';
rmii_tx <= "00";
rmii_tx <= (others => '0');
tx_state <= INIT;
data_reg <= (others => '0');
data_ack <= '0';
@ -100,10 +107,10 @@ begin
crc_data_valid <= '0';
-- Shift data register
data_reg <= "00" & data_reg(7 downto 2);
data_reg <= std_logic_vector(to_unsigned(0, IFACE_WIDTH)) & data_reg(7 downto IFACE_WIDTH);
-- Increment counters:
if dibit_counter = 3 then
if dibit_counter = DIBIT_COUNT - 1 then
dibit_counter <= 0;
if byte_counter_disable /= '1' then
if byte_counter = 15 then
@ -123,73 +130,75 @@ begin
case tx_state is
when INIT =>
byte_counter_disable <= '1';
-- Wait for start of frame
-- Wait for start of frame
if start_of_frame = '1' then
crc_init <= '1';
tx_state <= PREAMBLE;
crc_init <= '1';
tx_state <= PREAMBLE;
byte_counter_disable <= '0';
dibit_counter <= 0;
byte_counter <= 0;
eof_reg <= '0';
dibit_counter <= 0;
byte_counter <= 0;
eof_reg <= '0';
end if;
when PREAMBLE =>
rmii_txen <= '1';
rmii_txen <= '1';
byte_counter_disable <= '0';
if (byte_counter = 7 and dibit_counter = 3) then -- Last dibit of preamble+SFD
rmii_tx <= "11";
-- latch data_in and continue to data phase
data_reg <= data_in;
data_ack <= '1';
tx_state <= DATA;
eof_reg <= end_of_frame;
if (byte_counter = 7 and dibit_counter = DIBIT_COUNT -1) then -- Last dibit of preamble+SFD
rmii_tx <= PREAMBLE_SFD(7 downto 8 - IFACE_WIDTH);
-- latch data_in and continue to data phase
data_reg <= data_in;
data_ack <= '1';
tx_state <= DATA;
eof_reg <= end_of_frame;
crc_data_valid <= '1';
crc_calc <= '1';
crc_data_in <= data_in;
else
rmii_tx <= "01";
rmii_tx <= PREAMBLE_BYTE(IFACE_WIDTH -1 downto 0);
end if;
when DATA =>
rmii_txen <= '1';
crc_calc <= '1';
rmii_txen <= '1';
crc_calc <= '1';
byte_counter_disable <= '1';
rmii_tx <= data_reg(1 downto 0);
if dibit_counter = 0 then -- first dibit to transmit => shift register yet intact => Load crc;
crc_data_in <= data_reg;
rmii_tx <= data_reg(IFACE_WIDTH - 1 downto 0);
if dibit_counter = DIBIT_COUNT - 1 and eof_reg = '0' then -- Ladt dibit sent => latch new data
data_reg <= data_in;
data_ack <= '1';
eof_reg <= end_of_frame;
crc_data_valid <= '1';
end if;
-- Output Least significant dibit of data reg
if dibit_counter = 3 and eof_reg = '0' then -- Ladt dibit sent => latch new data
data_reg <= data_in;
data_ack <= '1';
eof_reg <= end_of_frame;
elsif dibit_counter = 3 and eof_reg = '1' then -- Last dibit sent, no further data => CRC
tx_state <= CRC;
data_reg <= crc_data_out;
byte_counter <= 0;
crc_data_in <= data_in;
elsif dibit_counter = DIBIT_COUNT - 1 and eof_reg = '1' then -- Last dibit sent, no further data => CRC
tx_state <= CRC;
data_reg <= crc_data_out;
crc_data_valid <= '1';
byte_counter <= 0;
byte_counter_disable <= '0';
crc_calc <= '0';
crc_calc <= '0';
end if;
when CRC =>
byte_counter_disable <= '0';
rmii_txen <= '1';
rmii_tx <= data_reg(1 downto 0);
if dibit_counter = 1 and byte_counter /= 3 then -- Request new data byte
crc_data_valid <= '1';
elsif dibit_counter = 3 then -- Either latch new CRC data or proceed to IPG when CRC is finished.
rmii_txen <= '1';
rmii_tx <= data_reg(IFACE_WIDTH - 1 downto 0);
if dibit_counter = DIBIT_COUNT - 1 then -- Either latch new CRC data or proceed to IPG when CRC is finished.
if byte_counter = 3 then
byte_counter <= 0;
tx_state <= IPG;
else
data_reg <= crc_data_out;
data_reg <= crc_data_out;
crc_data_valid <= '1';
end if;
end if;
when IPG =>
rmii_txen <= '0';
rmii_txen <= '0';
byte_counter_disable <= '0';
if byte_counter = 11 and dibit_counter = 3 then
if byte_counter = 11 and dibit_counter = DIBIT_COUNT - 1 then
tx_state <= INIT;
end if;
end case;
end if; -- abort condition
end if; -- rising edge end process eth_tx_fsm;
end if; -- abort condition
end if; -- rising edge end process eth_tx_fsm;
end process eth_tx_fsm;
tx_ready <= '1' when tx_state = INIT else '0';