218 lines
11 KiB
VHDL
218 lines
11 KiB
VHDL
--------------------------------------------------------------------------------
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-- CRC GENERATOR
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-- Computes the CRC32 (802.3) for the input byte stream. Assert D_VALID to load
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-- each byte for calculation. LOAD_INIT should be asserted at the beginning of a
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-- data stream in order to prime with CRC generator with 32'hFFFFFFFF
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-- which will cause the initial 32 bits in to be complemented as per 802.3.
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--
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-- IO DESCRIPTION
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-- Clock: 100MHz Clock
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-- Reset: Active high reset
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-- Data: 8Bit Data In
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-- Load Init: Asserted for one clock period, loads the CRC gen with 32'hFFFFFFFF
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-- Calc: Asserted to enable calculation of the CRC.
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-- D_valid: Asserted for one clock period, loads in the next byte on DATA.
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--
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-- @author Peter A Bennett
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-- @copyright (c) 2012 Peter A Bennett
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-- @version $Rev: 2 $
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-- @lastrevision $Date: 2012-03-11 15:19:25 +0000 (Sun, 11 Mar 2012) $
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-- @license LGPL
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-- @email pab850@googlemail.com
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-- @contact www.bytebash.com
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ethfcs is
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Port ( CLOCK : in std_logic;
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RESET : in std_logic;
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DATA : in std_logic_vector(7 downto 0);
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LOAD_INIT : in std_logic;
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CALC : in std_logic;
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D_VALID : in std_logic;
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CRC : out std_logic_vector(7 downto 0);
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CRC_REG : out std_logic_vector(31 downto 0);
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CRC_VALID : out std_logic
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);
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end ethfcs;
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architecture RTL of ethfcs is
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-- Block Diagram for Parallel CRC-32 generation.
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-- (Based on Xilinx CRC App Note)
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-- http://www.xilinx.com/support/documentation/application_notes/xapp209.pdf
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-- Data In is byte reversed internally as per the requirements of the easics comb CRC block.
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--
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-- The "8-bit CRC Out" register always contains the bit-reversed and complimented most
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-- significant bits of the "32-bit CRC" register. The final IEEE 802.3 FCS can be read from the
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-- "8-bit CRC Out" register by asserting d_valid four times after the de-assertion of calc
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--
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-- +--------------------------------------+-----------------------------------+
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-- | | _____ |
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-- | comb_crc_gen next_crc(23:0) | | \ +--->CRC_REG(31:0)
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-- | +---------------+ & x"FF" +-->|00 \ +-----+ |
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-- +-->| Combinatorial |--------------------->|01 \__________|D Q|______|
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--D(7:0) >--->| Next CRC Gen | xFFFFFFFF---->|10 / +--|---|En |
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-- +---------------+ xFFFFFFFF---->|11 / | | +-----+ ____ +-----+
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-- (complements first |_____/ | +------------>| = |-->|D Q|--> VALID_REG
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-- 32 bits of frame) | | | residue ---->|____| +-|En |
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--load_init >----------------------+------------------+ | | xC704DD7B | +-----+
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--calc >-----------+ | | | |
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--d_valid >-------+ | _ | | |-----------------------+
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-- | +---|x\____|____________________| |
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-- +---|---|_/ | _ |
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-- | | +---|+\_______________________|
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-- +---|----------+---|_/
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-- | |
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-- | +------------------------------------+
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-- | ________ ____ | +-----+
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-- | crc_reg (16:23)>-----|0 \ +--|En |
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-- | ________ | \___|D Q|------>CRC(7:0)
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-- | next_crc(24:31)>-----|1 / +-----+
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-- | |_____/
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-- | |
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-- +------------------------------------------+
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-- First, the data stream and CRC of the received frame are sent through the circuit.
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-- Then the value left in the CRC-32 registers can be compared with a constant, commonly
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-- referred to as the residue. In this implementation, the value of the residue is 0xC704DD7B
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-- when no CRC errors are detected. (Xilinx CRC App Note).
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-- CRC32 (Easics generator).
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function comb_crc_gen
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(
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data_in : std_logic_vector(7 downto 0);
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crc_in : std_logic_vector(31 downto 0)
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)
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return std_logic_vector is
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variable d: std_logic_vector(7 downto 0);
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variable c: std_logic_vector(31 downto 0);
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variable newcrc: std_logic_vector(31 downto 0);
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begin
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d := data_in;
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c := crc_in;
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-- Easics
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newcrc(0) := d(6) xor d(0) xor c(24) xor c(30);
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newcrc(1) := d(7) xor d(6) xor d(1) xor d(0) xor c(24) xor c(25) xor c(30) xor c(31);
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newcrc(2) := d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor c(24) xor c(25) xor c(26) xor c(30) xor c(31);
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newcrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor c(25) xor c(26) xor c(27) xor c(31);
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newcrc(4) := d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor c(24) xor c(26) xor c(27) xor c(28) xor c(30);
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newcrc(5) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor c(24) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor c(31);
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newcrc(6) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31);
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newcrc(7) := d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31);
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newcrc(8) := d(4) xor d(3) xor d(1) xor d(0) xor c(0) xor c(24) xor c(25) xor c(27) xor c(28);
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newcrc(9) := d(5) xor d(4) xor d(2) xor d(1) xor c(1) xor c(25) xor c(26) xor c(28) xor c(29);
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newcrc(10) := d(5) xor d(3) xor d(2) xor d(0) xor c(2) xor c(24) xor c(26) xor c(27) xor c(29);
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newcrc(11) := d(4) xor d(3) xor d(1) xor d(0) xor c(3) xor c(24) xor c(25) xor c(27) xor c(28);
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newcrc(12) := d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor c(4) xor c(24) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30);
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newcrc(13) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor c(5) xor c(25) xor c(26) xor c(27) xor c(29) xor c(30) xor c(31);
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newcrc(14) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor c(6) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31);
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newcrc(15) := d(7) xor d(5) xor d(4) xor d(3) xor c(7) xor c(27) xor c(28) xor c(29) xor c(31);
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newcrc(16) := d(5) xor d(4) xor d(0) xor c(8) xor c(24) xor c(28) xor c(29);
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newcrc(17) := d(6) xor d(5) xor d(1) xor c(9) xor c(25) xor c(29) xor c(30);
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newcrc(18) := d(7) xor d(6) xor d(2) xor c(10) xor c(26) xor c(30) xor c(31);
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newcrc(19) := d(7) xor d(3) xor c(11) xor c(27) xor c(31);
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newcrc(20) := d(4) xor c(12) xor c(28);
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newcrc(21) := d(5) xor c(13) xor c(29);
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newcrc(22) := d(0) xor c(14) xor c(24);
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newcrc(23) := d(6) xor d(1) xor d(0) xor c(15) xor c(24) xor c(25) xor c(30);
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newcrc(24) := d(7) xor d(2) xor d(1) xor c(16) xor c(25) xor c(26) xor c(31);
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newcrc(25) := d(3) xor d(2) xor c(17) xor c(26) xor c(27);
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newcrc(26) := d(6) xor d(4) xor d(3) xor d(0) xor c(18) xor c(24) xor c(27) xor c(28) xor c(30);
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newcrc(27) := d(7) xor d(5) xor d(4) xor d(1) xor c(19) xor c(25) xor c(28) xor c(29) xor c(31);
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newcrc(28) := d(6) xor d(5) xor d(2) xor c(20) xor c(26) xor c(29) xor c(30);
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newcrc(29) := d(7) xor d(6) xor d(3) xor c(21) xor c(27) xor c(30) xor c(31);
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newcrc(30) := d(7) xor d(4) xor c(22) xor c(28) xor c(31);
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newcrc(31) := d(5) xor c(23) xor c(29);
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return newcrc;
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end comb_crc_gen;
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-- Reverse the input vector.
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function reversed(slv: std_logic_vector) return std_logic_vector is
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variable result: std_logic_vector(slv'reverse_range);
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begin
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for i in slv'range loop
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result(i) := slv(i);
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end loop;
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return result;
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end reversed;
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-- Magic number for the CRC generator.
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constant c_crc_residue : std_logic_vector(31 downto 0) := x"C704DD7B";
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signal s_next_crc : std_logic_vector(31 downto 0) := (others => '0');
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signal s_crc_reg : std_logic_vector(31 downto 0) := (others => '0');
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signal s_crc : std_logic_vector(7 downto 0) := (others => '0');
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signal s_reversed_byte : std_logic_vector(7 downto 0) := (others => '0');
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signal s_crc_valid : std_logic := '0';
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begin
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CRC <= s_crc;
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CRC_REG <= s_crc_reg;
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CRC_VALID <= s_crc_valid;
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BYTE_REVERSE : process (DATA)
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-- Nibble swapped and Bit reversed version of DATA
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begin
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--s_reversed_byte <= reversed(DATA(3 downto 0) & DATA(7 downto 4));
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s_reversed_byte <= reversed(DATA);
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end process;
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COMB_NEXT_CRC_GEN : process (s_reversed_byte, s_crc_reg)
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begin
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s_next_crc <= comb_crc_gen(s_reversed_byte, s_crc_reg);
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end process COMB_NEXT_CRC_GEN;
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CRC_GEN : process (CLOCK)
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variable state : std_logic_vector(2 downto 0);
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begin
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if rising_edge(CLOCK) then
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if RESET = '1' then
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s_crc_reg <= (others => '0');
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s_crc <= (others => '0');
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s_crc_valid <= '0';
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state := (others => '0');
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else
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state := LOAD_INIT & CALC & D_VALID;
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case state is
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when "000" =>
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-- No change.
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when "001" =>
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s_crc_reg <= s_crc_reg(23 downto 0) & x"FF";
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s_crc <= not reversed(s_crc_reg(23 downto 16));
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when "010" =>
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-- No Change
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when "011" =>
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s_crc_reg <= s_next_crc;
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s_crc <= not reversed(s_next_crc(31 downto 24));
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when "100" =>
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s_crc_reg <= x"FFFFFFFF";
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when "101" =>
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s_crc_reg <= x"FFFFFFFF";
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s_crc <= not reversed(s_crc_reg(23 downto 16));
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when "110" =>
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s_crc_reg <= x"FFFFFFFF";
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when "111" =>
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s_crc_reg <= x"FFFFFFFF";
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s_crc <= not reversed(s_next_crc(31 downto 24));
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when others =>
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null;
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end case;
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if c_crc_residue = s_crc_reg then
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s_crc_valid <= '1';
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else
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s_crc_valid <= '0';
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end if;
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end if;
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end if;
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end process CRC_GEN;
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end RTL;
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