EthMac/bench/bench_ethmac_rx.vhd

-------------------------------------------------------------------------------
-- Title      : Bench for Ethernet RX Core
-- Project    : EthMAC
-------------------------------------------------------------------------------
-- File       : bench/bench_ethmac_rx.vhd
-- Author     : Mario Hüttel <mario.huettel@gmx.net>
-- Standard   : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Test bench for RX core. 
-------------------------------------------------------------------------------
-- Copyright (c) 2016
--
-- This file is part of EthMAC.
--
-- EthMAC is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 2 of the License.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library design;
use design.all;

entity bench_ethmac_rx is
end entity bench_ethmac_rx;

architecture RTL of bench_ethmac_rx is
	signal clk_hw          : std_logic;
	signal rst_hw          : std_logic;
	signal dv_i            : std_logic;
	signal rxd_i           : std_logic_vector(1 downto 0);
	signal rst             : std_logic;
	signal start_of_frame  : std_logic;
	signal end_of_frame    : std_logic;
	signal data_out        : std_logic_vector(7 downto 0);
	signal data_strb       : std_logic;
	signal crc_check_valid : std_logic;
	signal clock_fcs       : std_logic;
	signal crc             : std_logic_vector(7 downto 0);
	signal dvalid          : std_logic;
	signal calc            : std_logic;
	signal fcs_init        : std_logic;
	signal fcs_dat         : std_logic_vector(7 downto 0);
begin
	rst <= not rst_hw;

	clock_driver : process
		constant period : time := 20 ns;
	begin
		clk_hw <= '0';
		wait for period / 2;
		clk_hw <= '1';
		wait for period / 2;
	end process clock_driver;

	ethmac_rx_inst : entity design.ethmac_rx
		port map(
			clk_50          => clk_hw,
			rst             => rst,
			rmii_rx         => rxd_i,
			rmii_dv         => dv_i,
			start_of_frame  => start_of_frame,
			end_of_frame    => end_of_frame,
			data_out        => data_out,
			data_strb       => data_strb,
			crc_check_valid => crc_check_valid
		);

	ethfcs_inst : entity design.ethfcs
		port map(
			CLOCK     => clock_fcs,
			RESET     => rst,
			DATA      => fcs_dat,
			LOAD_INIT => fcs_init,
			CALC      => calc,
			D_VALID   => dvalid,
			CRC       => crc,
			CRC_REG   => open,
			CRC_VALID => open
		);

	sendphy : process is
		procedure sendRMII(byte : in std_logic_vector(7 downto 0)) is
		begin
			wait until falling_edge(clk_hw);
			dv_i  <= '1';
			rxd_i <= byte(1 downto 0);
			wait until falling_edge(clk_hw);
			rxd_i <= byte(3 downto 2);
			wait until falling_edge(clk_hw);
			rxd_i <= byte(5 downto 4);
			wait until falling_edge(clk_hw);
			rxd_i <= byte(7 downto 6);

		end procedure sendRMII;
	begin
		rst_hw  <= '0';
		dv_i    <= '0';
		rxd_i   <= "00";
		calc    <= '0';
		fcs_dat <= x"00";
		wait for 2 ns;
		rst_hw   <= '1';
		fcs_init <= '1';
		wait for 50 ns;
		fcs_init <= '0';

		wait for 50 ns;

		wait for 10 ns;
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"D5");

		sendRMII(x"FF");
		sendRMII(x"DE");
		sendRMII(x"AD");
		sendRMII(x"BE");
		sendRMII(x"EF");
		sendRMII(x"00");

		sendRMII(x"01");
		sendRMII(x"02");
		sendRMII(x"03");
		sendRMII(x"04");
		sendRMII(x"05");
		sendRMII(x"06");

		sendRMII(x"01");
		sendRMII(x"02");

		sendRMII(x"AA");

		sendRMII(x"01");
		sendRMII(x"02");
		sendRMII(x"03");

		-- Send FCS
		sendRMII(x"BD");
		sendRMII(x"9B");
		sendRMII(x"AC");
		sendRMII(x"54");

		-- sendRMII(x"AB");

		wait until falling_edge(clk_hw);
		wait for 10 ns;
		dv_i <= '0';
		wait for 200 ns;
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"55");
		sendRMII(x"D5");

		sendRMII(x"00");
		sendRMII(x"DE");
		sendRMII(x"AD");
		sendRMII(x"BE");
		sendRMII(x"EF");
		sendRMII(x"00");

		sendRMII(x"01");
		sendRMII(x"02");
		sendRMII(x"03");
		sendRMII(x"04");
		sendRMII(x"05");
		sendRMII(x"06");

		sendRMII(x"01");
		sendRMII(x"02");

		sendRMII(x"FA");
		wait until falling_edge(clk_hw);
		dv_i <= '0';
		wait;
	end process sendphy;

end architecture RTL;