EthMac/bench/bench_led_demo.vhd

86 lines
2.5 KiB
VHDL

-------------------------------------------------------------------------------
-- Title : Bench for LED-Demo
-- Project : EthMAC
-------------------------------------------------------------------------------
-- File : bench/bench_led_demo.vhd
-- Author : Mario Hüttel <mario.huettel@gmx.net>
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Test bench for LED Demonstration for Ethernet RX + TX.
-------------------------------------------------------------------------------
-- Copyright (c) 2016
--
-- This file is part of EthMAC.
--
-- EthMAC is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 2 of the License.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library ieee;
library design;
use design.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bench_led_demo is
end entity bench_led_demo;
architecture RTL of bench_led_demo is
signal clk : std_logic;
signal data_out : std_logic_vector(3 downto 0);
signal rst_hw : std_logic;
signal rmii_tx : std_logic_vector(1 downto 0);
signal rmii_txen : std_logic;
signal rmii_rx : std_logic_vector(1 downto 0);
signal rmii_rxen : std_logic;
signal mdc : std_logic_vector(1 downto 0);
signal mdio : std_logic_vector(1 downto 0);
begin
clock_driver : process
constant period : time := 20 ns;
begin
clk <= '0';
wait for period / 2;
clk <= '1';
wait for period / 2;
end process clock_driver;
rmii_rx <= rmii_tx;
rmii_rxen <= rmii_txen;
rstegen : process is
begin
rst_hw <= '0';
wait for 5 ns;
rst_hw <= '1';
wait;
end process rstegen;
leddemo_inst : entity design.leddemo
port map(
clk_tx => clk,
clk_rx => clk,
data_in => "1010",
data_out => data_out,
rst_hw => rst_hw,
rmii_tx => rmii_tx,
rmii_txen => rmii_txen,
rmii_rx => rmii_rx,
rmii_rxen => rmii_rxen,
mdc => mdc,
mdio => mdio
);
end architecture RTL;