174 lines
3.5 KiB
VHDL
174 lines
3.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library design;
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use design.all;
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entity bench_ethmac_rx is
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end entity bench_ethmac_rx;
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architecture RTL of bench_ethmac_rx is
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signal clk_hw : std_logic;
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signal rst_hw : std_logic;
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signal dv_i : std_logic;
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signal rxd_i : std_logic_vector(1 downto 0);
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signal rst : std_logic;
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signal start_of_frame : std_logic;
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signal end_of_frame : std_logic;
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signal data_out : std_logic_vector(7 downto 0);
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signal data_strb : std_logic;
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signal crc_check_valid : std_logic;
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signal clock_fcs : std_logic;
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signal crc : std_logic_vector(7 downto 0);
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signal dvalid : std_logic;
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signal calc : std_logic;
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signal fcs_init : std_logic;
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signal fcs_dat : std_logic_vector(7 downto 0);
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begin
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rst <= not rst_hw;
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk_hw <= '0';
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wait for period / 2;
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clk_hw <= '1';
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wait for period / 2;
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end process clock_driver;
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ethmac_rx_inst : entity design.ethmac_rx
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port map(
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clk_50 => clk_hw,
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rst => rst,
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rmii_rx => rxd_i,
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rmii_dv => dv_i,
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start_of_frame => start_of_frame,
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end_of_frame => end_of_frame,
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data_out => data_out,
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data_strb => data_strb,
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crc_check_valid => crc_check_valid
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);
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ethfcs_inst : entity design.ethfcs
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port map(
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CLOCK => clock_fcs,
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RESET => rst,
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DATA => fcs_dat,
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LOAD_INIT => fcs_init,
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CALC => calc,
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D_VALID => dvalid,
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CRC => crc,
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CRC_REG => open,
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CRC_VALID => open
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);
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sendphy : process is
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procedure sendRMII(byte : in std_logic_vector(7 downto 0)) is
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begin
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wait until falling_edge(clk_hw);
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dv_i <= '1';
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rxd_i <= byte(1 downto 0);
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wait until falling_edge(clk_hw);
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rxd_i <= byte(3 downto 2);
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wait until falling_edge(clk_hw);
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rxd_i <= byte(5 downto 4);
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wait until falling_edge(clk_hw);
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rxd_i <= byte(7 downto 6);
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end procedure sendRMII;
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begin
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rst_hw <= '0';
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dv_i <= '0';
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rxd_i <= "00";
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calc <= '0';
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fcs_dat <= x"00";
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wait for 2 ns;
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rst_hw <= '1';
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fcs_init <= '1';
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wait for 50 ns;
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fcs_init <= '0';
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wait for 50 ns;
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wait for 10 ns;
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"D5");
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sendRMII(x"FF");
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sendRMII(x"DE");
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sendRMII(x"AD");
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sendRMII(x"BE");
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sendRMII(x"EF");
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sendRMII(x"00");
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sendRMII(x"01");
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sendRMII(x"02");
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sendRMII(x"03");
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sendRMII(x"04");
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sendRMII(x"05");
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sendRMII(x"06");
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sendRMII(x"01");
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sendRMII(x"02");
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sendRMII(x"AA");
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sendRMII(x"01");
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sendRMII(x"02");
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sendRMII(x"03");
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-- Send FCS
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sendRMII(x"BD");
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sendRMII(x"9B");
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sendRMII(x"AC");
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sendRMII(x"54");
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-- sendRMII(x"AB");
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wait until falling_edge(clk_hw);
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wait for 10 ns;
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dv_i <= '0';
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wait for 200 ns;
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"D5");
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sendRMII(x"00");
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sendRMII(x"DE");
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sendRMII(x"AD");
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sendRMII(x"BE");
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sendRMII(x"EF");
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sendRMII(x"00");
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sendRMII(x"01");
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sendRMII(x"02");
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sendRMII(x"03");
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sendRMII(x"04");
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sendRMII(x"05");
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sendRMII(x"06");
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sendRMII(x"01");
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sendRMII(x"02");
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sendRMII(x"FA");
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wait until falling_edge(clk_hw);
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dv_i <= '0';
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wait;
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end process sendphy;
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end architecture RTL;
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