325 lines
11 KiB
VHDL
325 lines
11 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dma_31ch is
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generic(
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channel_config_g : std_logic_vector(3 downto 0) := "1011";
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channel_count_g : integer range 1 to 31 := 31
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);
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port(
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-- Generic I/O
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dma_clk : in std_logic;
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dma_rst : in std_logic;
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-- Trigger inputs (only valid if dma channel is inactive)
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dma_trig : in std_logic_vector(channel_count_g - 1 downto 0);
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-- Interrupt output
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inta : out std_logic;
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-- Config interface (Avalon slave)
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dma_conf_write : in std_logic;
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dma_conf_read : in std_logic;
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dma_conf_cs : in std_logic;
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dma_conf_waitrequest : out std_logic;
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dma_conf_data_from_dma : out std_logic_vector(31 downto 0);
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dma_conf_data_to_dma : in std_logic_vector(31 downto 0);
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dma_conf_addr : in std_logic_vector(15 downto 0);
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dma_conf_response : out std_logic_vector(1 downto 0);
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-- DMA Master Interface 0
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dma_mst0_write : out std_logic;
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dma_mst0_read : out std_logic;
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dma_mst0_cs : out std_logic;
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dma_mst0_waitrequest : in std_logic;
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dma_mst0_data_to_dma : in std_logic_vector(31 downto 0);
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dma_mst0_data_from_dma : out std_logic_vector(31 downto 0);
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dma_mst0_addr : out std_logic_vector(31 downto 0);
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-- DMA Master Interface 1
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dma_mst1_write : out std_logic;
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dma_mst1_read : out std_logic;
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dma_mst1_cs : out std_logic;
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dma_mst1_waitrequest : in std_logic;
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dma_mst1_data_to_dma : in std_logic_vector(31 downto 0);
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dma_mst1_data_from_dma : out std_logic_vector(31 downto 0);
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dma_mst1_addr : out std_logic_vector(31 downto 0)
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);
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end entity dma_31ch;
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architecture RTL of dma_31ch is
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constant ch_conf : std_logic_vector(3 downto 0) := channel_config_g;
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component avalon2wb
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generic(
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ADDR_WIDTH_G : natural := 32;
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DATA_WIDTH_G : natural := 32
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);
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port(
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avalon_write : in std_logic;
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avalon_read : in std_logic;
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avalon_cs : in std_logic;
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avalon_waitrequest : out std_logic;
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avalon_data_in : in std_logic_vector(DATA_WIDTH_G - 1 downto 0);
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avalon_data_out : out std_logic_vector(DATA_WIDTH_G - 1 downto 0);
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avalon_address : in std_logic_vector(ADDR_WIDTH_G - 1 downto 0);
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avalon_response : out std_logic_vector(1 downto 0);
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wb_cyc : out std_logic;
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wb_we : out std_logic;
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wb_stb : out std_logic;
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wb_ack : in std_logic;
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wb_address : out std_logic_vector(ADDR_WIDTH_G - 1 downto 0);
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wb_data_out : out std_logic_vector(DATA_WIDTH_G - 1 downto 0);
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wb_data_in : in std_logic_vector(DATA_WIDTH_G - 1 downto 0);
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wb_err_i : in std_logic;
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wb_rty_i : in std_logic
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);
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end component avalon2wb;
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component wb2avalon
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generic(
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ADDR_WIDTH_G : natural := 32;
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DATA_WIDTH_G : natural := 32
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);
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port(
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avalon_write : out std_logic;
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avalon_read : out std_logic;
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avalon_cs : out std_logic;
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avalon_waitrequest : in std_logic;
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avalon_data_in : in std_logic_vector(DATA_WIDTH_G - 1 downto 0);
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avalon_data_out : out std_logic_vector(DATA_WIDTH_G - 1 downto 0);
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avalon_address : out std_logic_vector(ADDR_WIDTH_G - 1 downto 0);
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wb_cyc : in std_logic;
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wb_we : in std_logic;
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wb_stb : in std_logic;
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wb_ack : out std_logic;
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wb_address : in std_logic_vector(ADDR_WIDTH_G - 1 downto 0);
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wb_data_out : out std_logic_vector(DATA_WIDTH_G - 1 downto 0);
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wb_data_in : in std_logic_vector(DATA_WIDTH_G - 1 downto 0);
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wb_err : out std_logic;
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wb_rty : out std_logic
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);
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end component wb2avalon;
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-- Wishbone Config interface
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signal wb_conf_addr : std_logic_vector(31 downto 0);
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signal wb_conf_data_to_dma : std_logic_vector(31 downto 0);
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signal wb_conf_data_from_dma : std_logic_vector(31 downto 0);
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signal wb_conf_sel : std_logic_vector(3 downto 0);
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signal wb_conf_we : std_logic;
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signal wb_conf_cyc : std_logic;
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signal wb_conf_stb : std_logic;
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signal wb_conf_ack : std_logic;
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signal wb_conf_err : std_logic;
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signal wb_conf_rty : std_logic;
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-- Wishbone Master Interface 0
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signal wb_m0_addr : std_logic_vector(31 downto 0);
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signal wb_m0_data_to_dma : std_logic_vector(31 downto 0);
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signal wb_m0_data_from_dma : std_logic_vector(31 downto 0);
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signal wb_m0_sel : std_logic_vector(3 downto 0);
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signal wb_m0_we : std_logic;
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signal wb_m0_cyc : std_logic;
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signal wb_m0_stb : std_logic;
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signal wb_m0_ack : std_logic;
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signal wb_m0_err : std_logic;
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signal wb_m0_rty : std_logic;
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-- Wishbone Master Interface 1
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signal wb_m1_addr : std_logic_vector(31 downto 0);
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signal wb_m1_data_to_dma : std_logic_vector(31 downto 0);
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signal wb_m1_data_from_dma : std_logic_vector(31 downto 0);
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signal wb_m1_sel : std_logic_vector(3 downto 0);
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signal wb_m1_we : std_logic;
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signal wb_m1_cyc : std_logic;
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signal wb_m1_stb : std_logic;
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signal wb_m1_ack : std_logic;
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signal wb_m1_err : std_logic;
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signal wb_m1_rty : std_logic;
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-- DMA trigger/request signals
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signal dma_req : std_logic_vector(channel_count_g - 1 downto 0);
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signal dma_req_ack : std_logic_vector(channel_count_g - 1 downto 0);
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-- DMA Config address Signals
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signal wb_conf_addr_premask : std_logic_vector(15 downto 0);
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begin
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-- DMA instance
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wb_dma_top_inst : entity work.wb_dma_top
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generic map(
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rf_addr => x"F", -- Top address width. Will be remapped by wrapper
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pri_sel => "00", -- Only 1 priority
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ch_count => channel_count_g,
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ch0_conf => ch_conf,
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ch1_conf => ch_conf,
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ch2_conf => ch_conf,
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ch3_conf => ch_conf,
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ch4_conf => ch_conf,
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ch5_conf => ch_conf,
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ch6_conf => ch_conf,
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ch7_conf => ch_conf,
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ch8_conf => ch_conf,
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ch9_conf => ch_conf,
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ch10_conf => ch_conf,
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ch11_conf => ch_conf,
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ch12_conf => ch_conf,
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ch13_conf => ch_conf,
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ch14_conf => ch_conf,
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ch15_conf => ch_conf,
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ch16_conf => ch_conf,
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ch17_conf => ch_conf,
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ch18_conf => ch_conf,
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ch19_conf => ch_conf,
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ch20_conf => ch_conf,
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ch21_conf => ch_conf,
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ch22_conf => ch_conf,
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ch23_conf => ch_conf,
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ch24_conf => ch_conf,
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ch25_conf => ch_conf,
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ch26_conf => ch_conf,
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ch27_conf => ch_conf,
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ch28_conf => ch_conf,
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ch29_conf => ch_conf,
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ch30_conf => ch_conf
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)
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port map(
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clk_i => dma_clk,
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rst_i => dma_rst,
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wb0s_data_i => wb_conf_data_to_dma,
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wb0s_data_o => wb_conf_data_from_dma,
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wb0_addr_i => wb_conf_addr,
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wb0_sel_i => wb_conf_sel,
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wb0_we_i => wb_conf_we,
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wb0_cyc_i => wb_conf_cyc,
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wb0_stb_i => wb_conf_stb,
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wb0_ack_o => wb_conf_ack,
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wb0_err_o => wb_conf_err,
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wb0_rty_o => wb_conf_rty,
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wb0m_data_i => wb_m0_data_to_dma,
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wb0m_data_o => wb_m0_data_from_dma,
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wb0_addr_o => wb_m0_addr,
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wb0_sel_o => wb_m0_sel,
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wb0_we_o => wb_m0_we,
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wb0_cyc_o => wb_m0_cyc,
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wb0_stb_o => wb_m0_stb,
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wb0_ack_i => wb_m0_ack,
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wb0_err_i => wb_m0_err,
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wb0_rty_i => wb_m0_rty,
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wb1s_data_i => (others => '0'),
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wb1s_data_o => open,
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wb1_addr_i => open,
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wb1_sel_i => open,
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wb1_we_i => open,
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wb1_cyc_i => open,
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wb1_stb_i => open,
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wb1_ack_o => open,
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wb1_err_o => open,
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wb1_rty_o => open,
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wb1m_data_i => wb_m1_data_to_dma,
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wb1m_data_o => wb_m1_data_from_dma,
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wb1_addr_o => wb_m1_addr,
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wb1_sel_o => wb_m1_sel,
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wb1_we_o => wb_m1_we,
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wb1_cyc_o => wb_m1_cyc,
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wb1_stb_o => wb_m1_stb,
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wb1_ack_i => wb_m1_ack,
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wb1_err_i => wb_m1_err,
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wb1_rty_i => wb_m1_rty,
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dma_req_i => dma_req,
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dma_nd_i => (others => '0'),
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dma_ack_o => dma_req_ack,
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dma_rest_i => (others => '0'),
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inta_o => inta,
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intb_o => open
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);
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config_iface: avalon2wb
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generic map(
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ADDR_WIDTH_G => 16,
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DATA_WIDTH_G => 32
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)
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port map(
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avalon_write => dma_conf_write,
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avalon_read => dma_conf_read,
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avalon_cs => dma_conf_cs,
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avalon_waitrequest => dma_conf_waitrequest,
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avalon_data_in => dma_conf_data_to_dma,
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avalon_data_out => dma_conf_data_from_dma,
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avalon_address => dma_conf_addr,
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avalon_response => dma_conf_response,
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wb_cyc => wb_conf_cyc,
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wb_we => wb_conf_we,
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wb_stb => wb_conf_stb,
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wb_ack => wb_conf_ack,
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wb_address => wb_conf_addr_premask,
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wb_data_out => wb_conf_data_to_dma,
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wb_data_in => wb_conf_data_from_dma,
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wb_err_i => wb_conf_err,
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wb_rty_i => wb_conf_rty
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);
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master_ifac0: wb2avalon
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generic map(
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ADDR_WIDTH_G => 32,
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DATA_WIDTH_G => 32
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)
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port map(
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avalon_write => dma_mst0_write,
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avalon_read => dma_mst0_read,
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avalon_cs => dma_mst0_cs,
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avalon_waitrequest => dma_mst0_waitrequest,
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avalon_data_in => dma_mst0_data_to_dma,
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avalon_data_out => dma_mst0_data_from_dma,
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avalon_address => dma_mst0_addr,
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wb_cyc => wb_m0_cyc,
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wb_we => wb_m0_we,
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wb_stb => wb_m0_stb,
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wb_ack => wb_m0_ack,
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wb_address => wb_m0_addr,
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wb_data_out => wb_m0_data_to_dma,
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wb_data_in => wb_m0_data_from_dma,
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wb_err => wb_m0_err,
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wb_rty => wb_m0_rty
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);
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master_iface1: wb2avalon
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generic map(
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ADDR_WIDTH_G => 32,
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DATA_WIDTH_G => 32
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)
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port map(
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avalon_write => dma_mst1_write,
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avalon_read => dma_mst1_read,
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avalon_cs => dma_mst1_cs,
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avalon_waitrequest => dma_mst1_waitrequest,
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avalon_data_in => dma_mst1_data_to_dma,
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avalon_data_out => dma_mst1_data_from_dma,
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avalon_address => dma_mst1_addr,
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wb_cyc => wb_m1_cyc,
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wb_we => wb_m1_we,
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wb_stb => wb_m1_stb,
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wb_ack => wb_m1_ack,
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wb_address => wb_m1_addr,
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wb_data_out => wb_m1_data_to_dma,
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wb_data_in => wb_m1_data_from_dma,
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wb_err => wb_m1_err,
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wb_rty => wb_m1_rty
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);
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-- DMA config address range is at the "top" of 32-bit address space beginning at 0xF0000000
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wb_conf_addr <= x"F000" & wb_conf_addr_premask;
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trigger_handshake : for i in 0 to channel_count_g - 1 generate
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handshake_proc : process(dma_clk, dma_rst) is
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begin
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if dma_rst = '1' then
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dma_req <= (others => '0');
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elsif rising_edge(dma_clk) then
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if dma_req_ack(i) = '1' and dma_req(i) = '1' then
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dma_req(i) <= '0';
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elsif dma_trig(i) = '1' then
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dma_req(i) <= '1';
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end if;
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end if;
|
||
|
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end process handshake_proc;
|
||
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|
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||
|
|
end generate trigger_handshake;
|
||
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|
|
||
|
|
end architecture RTL;
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