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Mario Hüttel 2018-03-06 15:11:37 +01:00
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<projectDescription>
<name>dma31ch_avalon</name>
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eclipse.preferences.version=1
encoding//Common\ Libraries/IEEE=utf-8
encoding//Common\ Libraries/IEEE/Synopsys=utf-8
encoding//Common\ Libraries/STD=utf-8
encoding/Common\ Libraries=utf-8

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity avalon2wb is
generic (
ADDR_WIDTH_G : natural := 32;
DATA_WIDTH_G : natural := 32
);
port(
-- Avalon Signals
avalon_write : in std_logic;
avalon_read : in std_logic;
avalon_cs : in std_logic;
avalon_waitrequest : out std_logic;
avalon_data_in : in std_logic_vector(DATA_WIDTH_G-1 downto 0);
avalon_data_out : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
avalon_address : in std_logic_vector(ADDR_WIDTH_G-1 downto 0);
avalon_response : out std_logic_vector(1 downto 0);
-- Wishbone Signals
wb_cyc : out std_logic;
wb_we : out std_logic;
wb_stb : out std_logic;
wb_ack : in std_logic;
wb_address : out std_logic_vector(ADDR_WIDTH_G-1 downto 0);
wb_data_out : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
wb_data_in : in std_logic_vector(DATA_WIDTH_G-1 downto 0);
wb_err_i : in std_logic;
wb_rty_i : in std_logic
);
end entity avalon2wb;
architecture RTL of avalon2wb is
constant RESP_OKAY : std_logic_vector(1 downto 0) := "00";
constant RESP_SLV_ERR : std_logic_vector(1 downto 0) := "10";
begin
wb_address <= avalon_address;
wb_data_out <= avalon_data_in;
avalon_data_out <= wb_data_in;
wb_cyc <= avalon_write or avalon_read;
wb_stb <= avalon_cs;
wb_we <= avalon_write and (not avalon_read);
wait_gen : process(wb_ack, wb_rty_i, wb_err_i) is
begin
avalon_waitrequest <= '1';
avalon_response <= RESP_OKAY;
if wb_ack = '1' then
avalon_waitrequest <= '0';
elsif (wb_err_i = '1') or (wb_rty_i = '1') then
avalon_waitrequest <= '0';
avalon_response <= RESP_SLV_ERR;
end if;
end process wait_gen;
end architecture RTL;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_31ch is
generic(
channel_config_g : std_logic_vector(3 downto 0) := "1011";
channel_count_g : integer range 1 to 31 := 31
);
port(
-- Generic I/O
dma_clk : in std_logic;
dma_rst : in std_logic;
-- Trigger inputs (only valid if dma channel is inactive)
dma_trig : in std_logic_vector(channel_count_g - 1 downto 0);
-- Interrupt output
inta : out std_logic;
-- Config interface (Avalon slave)
dma_conf_write : in std_logic;
dma_conf_read : in std_logic;
dma_conf_cs : in std_logic;
dma_conf_waitrequest : out std_logic;
dma_conf_data_from_dma : out std_logic_vector(31 downto 0);
dma_conf_data_to_dma : in std_logic_vector(31 downto 0);
dma_conf_addr : in std_logic_vector(15 downto 0);
dma_conf_response : out std_logic_vector(1 downto 0);
-- DMA Master Interface 0
dma_mst0_write : out std_logic;
dma_mst0_read : out std_logic;
dma_mst0_cs : out std_logic;
dma_mst0_waitrequest : in std_logic;
dma_mst0_data_to_dma : in std_logic_vector(31 downto 0);
dma_mst0_data_from_dma : out std_logic_vector(31 downto 0);
dma_mst0_addr : out std_logic_vector(31 downto 0);
-- DMA Master Interface 1
dma_mst1_write : out std_logic;
dma_mst1_read : out std_logic;
dma_mst1_cs : out std_logic;
dma_mst1_waitrequest : in std_logic;
dma_mst1_data_to_dma : in std_logic_vector(31 downto 0);
dma_mst1_data_from_dma : out std_logic_vector(31 downto 0);
dma_mst1_addr : out std_logic_vector(31 downto 0)
);
end entity dma_31ch;
architecture RTL of dma_31ch is
constant ch_conf : std_logic_vector(3 downto 0) := channel_config_g;
component avalon2wb
generic(
ADDR_WIDTH_G : natural := 32;
DATA_WIDTH_G : natural := 32
);
port(
avalon_write : in std_logic;
avalon_read : in std_logic;
avalon_cs : in std_logic;
avalon_waitrequest : out std_logic;
avalon_data_in : in std_logic_vector(DATA_WIDTH_G - 1 downto 0);
avalon_data_out : out std_logic_vector(DATA_WIDTH_G - 1 downto 0);
avalon_address : in std_logic_vector(ADDR_WIDTH_G - 1 downto 0);
avalon_response : out std_logic_vector(1 downto 0);
wb_cyc : out std_logic;
wb_we : out std_logic;
wb_stb : out std_logic;
wb_ack : in std_logic;
wb_address : out std_logic_vector(ADDR_WIDTH_G - 1 downto 0);
wb_data_out : out std_logic_vector(DATA_WIDTH_G - 1 downto 0);
wb_data_in : in std_logic_vector(DATA_WIDTH_G - 1 downto 0);
wb_err_i : in std_logic;
wb_rty_i : in std_logic
);
end component avalon2wb;
component wb2avalon
generic(
ADDR_WIDTH_G : natural := 32;
DATA_WIDTH_G : natural := 32
);
port(
avalon_write : out std_logic;
avalon_read : out std_logic;
avalon_cs : out std_logic;
avalon_waitrequest : in std_logic;
avalon_data_in : in std_logic_vector(DATA_WIDTH_G - 1 downto 0);
avalon_data_out : out std_logic_vector(DATA_WIDTH_G - 1 downto 0);
avalon_address : out std_logic_vector(ADDR_WIDTH_G - 1 downto 0);
wb_cyc : in std_logic;
wb_we : in std_logic;
wb_stb : in std_logic;
wb_ack : out std_logic;
wb_address : in std_logic_vector(ADDR_WIDTH_G - 1 downto 0);
wb_data_out : out std_logic_vector(DATA_WIDTH_G - 1 downto 0);
wb_data_in : in std_logic_vector(DATA_WIDTH_G - 1 downto 0);
wb_err : out std_logic;
wb_rty : out std_logic
);
end component wb2avalon;
-- Wishbone Config interface
signal wb_conf_addr : std_logic_vector(31 downto 0);
signal wb_conf_data_to_dma : std_logic_vector(31 downto 0);
signal wb_conf_data_from_dma : std_logic_vector(31 downto 0);
signal wb_conf_sel : std_logic_vector(3 downto 0);
signal wb_conf_we : std_logic;
signal wb_conf_cyc : std_logic;
signal wb_conf_stb : std_logic;
signal wb_conf_ack : std_logic;
signal wb_conf_err : std_logic;
signal wb_conf_rty : std_logic;
-- Wishbone Master Interface 0
signal wb_m0_addr : std_logic_vector(31 downto 0);
signal wb_m0_data_to_dma : std_logic_vector(31 downto 0);
signal wb_m0_data_from_dma : std_logic_vector(31 downto 0);
signal wb_m0_sel : std_logic_vector(3 downto 0);
signal wb_m0_we : std_logic;
signal wb_m0_cyc : std_logic;
signal wb_m0_stb : std_logic;
signal wb_m0_ack : std_logic;
signal wb_m0_err : std_logic;
signal wb_m0_rty : std_logic;
-- Wishbone Master Interface 1
signal wb_m1_addr : std_logic_vector(31 downto 0);
signal wb_m1_data_to_dma : std_logic_vector(31 downto 0);
signal wb_m1_data_from_dma : std_logic_vector(31 downto 0);
signal wb_m1_sel : std_logic_vector(3 downto 0);
signal wb_m1_we : std_logic;
signal wb_m1_cyc : std_logic;
signal wb_m1_stb : std_logic;
signal wb_m1_ack : std_logic;
signal wb_m1_err : std_logic;
signal wb_m1_rty : std_logic;
-- DMA trigger/request signals
signal dma_req : std_logic_vector(channel_count_g - 1 downto 0);
signal dma_req_ack : std_logic_vector(channel_count_g - 1 downto 0);
-- DMA Config address Signals
signal wb_conf_addr_premask : std_logic_vector(15 downto 0);
begin
-- DMA instance
wb_dma_top_inst : entity work.wb_dma_top
generic map(
rf_addr => x"F", -- Top address width. Will be remapped by wrapper
pri_sel => "00", -- Only 1 priority
ch_count => channel_count_g,
ch0_conf => ch_conf,
ch1_conf => ch_conf,
ch2_conf => ch_conf,
ch3_conf => ch_conf,
ch4_conf => ch_conf,
ch5_conf => ch_conf,
ch6_conf => ch_conf,
ch7_conf => ch_conf,
ch8_conf => ch_conf,
ch9_conf => ch_conf,
ch10_conf => ch_conf,
ch11_conf => ch_conf,
ch12_conf => ch_conf,
ch13_conf => ch_conf,
ch14_conf => ch_conf,
ch15_conf => ch_conf,
ch16_conf => ch_conf,
ch17_conf => ch_conf,
ch18_conf => ch_conf,
ch19_conf => ch_conf,
ch20_conf => ch_conf,
ch21_conf => ch_conf,
ch22_conf => ch_conf,
ch23_conf => ch_conf,
ch24_conf => ch_conf,
ch25_conf => ch_conf,
ch26_conf => ch_conf,
ch27_conf => ch_conf,
ch28_conf => ch_conf,
ch29_conf => ch_conf,
ch30_conf => ch_conf
)
port map(
clk_i => dma_clk,
rst_i => dma_rst,
wb0s_data_i => wb_conf_data_to_dma,
wb0s_data_o => wb_conf_data_from_dma,
wb0_addr_i => wb_conf_addr,
wb0_sel_i => wb_conf_sel,
wb0_we_i => wb_conf_we,
wb0_cyc_i => wb_conf_cyc,
wb0_stb_i => wb_conf_stb,
wb0_ack_o => wb_conf_ack,
wb0_err_o => wb_conf_err,
wb0_rty_o => wb_conf_rty,
wb0m_data_i => wb_m0_data_to_dma,
wb0m_data_o => wb_m0_data_from_dma,
wb0_addr_o => wb_m0_addr,
wb0_sel_o => wb_m0_sel,
wb0_we_o => wb_m0_we,
wb0_cyc_o => wb_m0_cyc,
wb0_stb_o => wb_m0_stb,
wb0_ack_i => wb_m0_ack,
wb0_err_i => wb_m0_err,
wb0_rty_i => wb_m0_rty,
wb1s_data_i => (others => '0'),
wb1s_data_o => open,
wb1_addr_i => open,
wb1_sel_i => open,
wb1_we_i => open,
wb1_cyc_i => open,
wb1_stb_i => open,
wb1_ack_o => open,
wb1_err_o => open,
wb1_rty_o => open,
wb1m_data_i => wb_m1_data_to_dma,
wb1m_data_o => wb_m1_data_from_dma,
wb1_addr_o => wb_m1_addr,
wb1_sel_o => wb_m1_sel,
wb1_we_o => wb_m1_we,
wb1_cyc_o => wb_m1_cyc,
wb1_stb_o => wb_m1_stb,
wb1_ack_i => wb_m1_ack,
wb1_err_i => wb_m1_err,
wb1_rty_i => wb_m1_rty,
dma_req_i => dma_req,
dma_nd_i => (others => '0'),
dma_ack_o => dma_req_ack,
dma_rest_i => (others => '0'),
inta_o => inta,
intb_o => open
);
config_iface: avalon2wb
generic map(
ADDR_WIDTH_G => 16,
DATA_WIDTH_G => 32
)
port map(
avalon_write => dma_conf_write,
avalon_read => dma_conf_read,
avalon_cs => dma_conf_cs,
avalon_waitrequest => dma_conf_waitrequest,
avalon_data_in => dma_conf_data_to_dma,
avalon_data_out => dma_conf_data_from_dma,
avalon_address => dma_conf_addr,
avalon_response => dma_conf_response,
wb_cyc => wb_conf_cyc,
wb_we => wb_conf_we,
wb_stb => wb_conf_stb,
wb_ack => wb_conf_ack,
wb_address => wb_conf_addr_premask,
wb_data_out => wb_conf_data_to_dma,
wb_data_in => wb_conf_data_from_dma,
wb_err_i => wb_conf_err,
wb_rty_i => wb_conf_rty
);
master_ifac0: wb2avalon
generic map(
ADDR_WIDTH_G => 32,
DATA_WIDTH_G => 32
)
port map(
avalon_write => dma_mst0_write,
avalon_read => dma_mst0_read,
avalon_cs => dma_mst0_cs,
avalon_waitrequest => dma_mst0_waitrequest,
avalon_data_in => dma_mst0_data_to_dma,
avalon_data_out => dma_mst0_data_from_dma,
avalon_address => dma_mst0_addr,
wb_cyc => wb_m0_cyc,
wb_we => wb_m0_we,
wb_stb => wb_m0_stb,
wb_ack => wb_m0_ack,
wb_address => wb_m0_addr,
wb_data_out => wb_m0_data_to_dma,
wb_data_in => wb_m0_data_from_dma,
wb_err => wb_m0_err,
wb_rty => wb_m0_rty
);
master_iface1: wb2avalon
generic map(
ADDR_WIDTH_G => 32,
DATA_WIDTH_G => 32
)
port map(
avalon_write => dma_mst1_write,
avalon_read => dma_mst1_read,
avalon_cs => dma_mst1_cs,
avalon_waitrequest => dma_mst1_waitrequest,
avalon_data_in => dma_mst1_data_to_dma,
avalon_data_out => dma_mst1_data_from_dma,
avalon_address => dma_mst1_addr,
wb_cyc => wb_m1_cyc,
wb_we => wb_m1_we,
wb_stb => wb_m1_stb,
wb_ack => wb_m1_ack,
wb_address => wb_m1_addr,
wb_data_out => wb_m1_data_to_dma,
wb_data_in => wb_m1_data_from_dma,
wb_err => wb_m1_err,
wb_rty => wb_m1_rty
);
-- DMA config address range is at the "top" of 32-bit address space beginning at 0xF0000000
wb_conf_addr <= x"F000" & wb_conf_addr_premask;
trigger_handshake : for i in 0 to channel_count_g - 1 generate
handshake_proc : process(dma_clk, dma_rst) is
begin
if dma_rst = '1' then
dma_req <= (others => '0');
elsif rising_edge(dma_clk) then
if dma_req_ack(i) = '1' and dma_req(i) = '1' then
dma_req(i) <= '0';
elsif dma_trig(i) = '1' then
dma_req(i) <= '1';
end if;
end if;
end process handshake_proc;
end generate trigger_handshake;
end architecture RTL;

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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA Priority Encoder ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_ch_pri_enc.v,v 1.5 2002-02-01 01:54:44 rudi Exp $
//
// $Date: 2002-02-01 01:54:44 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/10/19 04:35:04 rudi
//
// - Made the core parameterized
//
// Revision 1.3 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.2 2001/08/07 08:00:43 rudi
//
//
// Split up priority encoder modules to separate files
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.2 2001/06/05 10:22:36 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:10:50 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
// Priority Encoder
//
// Determines the channel with the highest priority, also takes
// the valid bit in consideration
module wb_dma_ch_pri_enc(clk, valid,
pri0, pri1, pri2, pri3,
pri4, pri5, pri6, pri7,
pri8, pri9, pri10, pri11,
pri12, pri13, pri14, pri15,
pri16, pri17, pri18, pri19,
pri20, pri21, pri22, pri23,
pri24, pri25, pri26, pri27,
pri28, pri29, pri30,
pri_out);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
// chXX_conf = { CBUF, ED, ARS, EN }
parameter [1:0] pri_sel = 2'd0;
parameter [3:0] ch0_conf = 4'h1;
parameter [3:0] ch1_conf = 4'h0;
parameter [3:0] ch2_conf = 4'h0;
parameter [3:0] ch3_conf = 4'h0;
parameter [3:0] ch4_conf = 4'h0;
parameter [3:0] ch5_conf = 4'h0;
parameter [3:0] ch6_conf = 4'h0;
parameter [3:0] ch7_conf = 4'h0;
parameter [3:0] ch8_conf = 4'h0;
parameter [3:0] ch9_conf = 4'h0;
parameter [3:0] ch10_conf = 4'h0;
parameter [3:0] ch11_conf = 4'h0;
parameter [3:0] ch12_conf = 4'h0;
parameter [3:0] ch13_conf = 4'h0;
parameter [3:0] ch14_conf = 4'h0;
parameter [3:0] ch15_conf = 4'h0;
parameter [3:0] ch16_conf = 4'h0;
parameter [3:0] ch17_conf = 4'h0;
parameter [3:0] ch18_conf = 4'h0;
parameter [3:0] ch19_conf = 4'h0;
parameter [3:0] ch20_conf = 4'h0;
parameter [3:0] ch21_conf = 4'h0;
parameter [3:0] ch22_conf = 4'h0;
parameter [3:0] ch23_conf = 4'h0;
parameter [3:0] ch24_conf = 4'h0;
parameter [3:0] ch25_conf = 4'h0;
parameter [3:0] ch26_conf = 4'h0;
parameter [3:0] ch27_conf = 4'h0;
parameter [3:0] ch28_conf = 4'h0;
parameter [3:0] ch29_conf = 4'h0;
parameter [3:0] ch30_conf = 4'h0;
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk;
input [30:0] valid; // Channel Valid bits
input [2:0] pri0, pri1, pri2, pri3; // Channel Priorities
input [2:0] pri4, pri5, pri6, pri7;
input [2:0] pri8, pri9, pri10, pri11;
input [2:0] pri12, pri13, pri14, pri15;
input [2:0] pri16, pri17, pri18, pri19;
input [2:0] pri20, pri21, pri22, pri23;
input [2:0] pri24, pri25, pri26, pri27;
input [2:0] pri28, pri29, pri30;
output [2:0] pri_out; // Highest unserviced priority
wire [7:0] pri0_out, pri1_out, pri2_out, pri3_out;
wire [7:0] pri4_out, pri5_out, pri6_out, pri7_out;
wire [7:0] pri8_out, pri9_out, pri10_out, pri11_out;
wire [7:0] pri12_out, pri13_out, pri14_out, pri15_out;
wire [7:0] pri16_out, pri17_out, pri18_out, pri19_out;
wire [7:0] pri20_out, pri21_out, pri22_out, pri23_out;
wire [7:0] pri24_out, pri25_out, pri26_out, pri27_out;
wire [7:0] pri28_out, pri29_out, pri30_out;
wire [7:0] pri_out_tmp;
reg [2:0] pri_out;
reg [2:0] pri_out2;
reg [2:0] pri_out1;
reg [2:0] pri_out0;
wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u0( // Use channel config 1 for channel 0 encoder
.valid( valid[0] ),
.pri_in( pri0 ),
.pri_out( pri0_out )
);
wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u1(
.valid( valid[1] ),
.pri_in( pri1 ),
.pri_out( pri1_out )
);
wb_dma_pri_enc_sub #(ch2_conf,pri_sel) u2(
.valid( valid[2] ),
.pri_in( pri2 ),
.pri_out( pri2_out )
);
wb_dma_pri_enc_sub #(ch3_conf,pri_sel) u3(
.valid( valid[3] ),
.pri_in( pri3 ),
.pri_out( pri3_out )
);
wb_dma_pri_enc_sub #(ch4_conf,pri_sel) u4(
.valid( valid[4] ),
.pri_in( pri4 ),
.pri_out( pri4_out )
);
wb_dma_pri_enc_sub #(ch5_conf,pri_sel) u5(
.valid( valid[5] ),
.pri_in( pri5 ),
.pri_out( pri5_out )
);
wb_dma_pri_enc_sub #(ch6_conf,pri_sel) u6(
.valid( valid[6] ),
.pri_in( pri6 ),
.pri_out( pri6_out )
);
wb_dma_pri_enc_sub #(ch7_conf,pri_sel) u7(
.valid( valid[7] ),
.pri_in( pri7 ),
.pri_out( pri7_out )
);
wb_dma_pri_enc_sub #(ch8_conf,pri_sel) u8(
.valid( valid[8] ),
.pri_in( pri8 ),
.pri_out( pri8_out )
);
wb_dma_pri_enc_sub #(ch9_conf,pri_sel) u9(
.valid( valid[9] ),
.pri_in( pri9 ),
.pri_out( pri9_out )
);
wb_dma_pri_enc_sub #(ch10_conf,pri_sel) u10(
.valid( valid[10] ),
.pri_in( pri10 ),
.pri_out( pri10_out )
);
wb_dma_pri_enc_sub #(ch11_conf,pri_sel) u11(
.valid( valid[11] ),
.pri_in( pri11 ),
.pri_out( pri11_out )
);
wb_dma_pri_enc_sub #(ch12_conf,pri_sel) u12(
.valid( valid[12] ),
.pri_in( pri12 ),
.pri_out( pri12_out )
);
wb_dma_pri_enc_sub #(ch13_conf,pri_sel) u13(
.valid( valid[13] ),
.pri_in( pri13 ),
.pri_out( pri13_out )
);
wb_dma_pri_enc_sub #(ch14_conf,pri_sel) u14(
.valid( valid[14] ),
.pri_in( pri14 ),
.pri_out( pri14_out )
);
wb_dma_pri_enc_sub #(ch15_conf,pri_sel) u15(
.valid( valid[15] ),
.pri_in( pri15 ),
.pri_out( pri15_out )
);
wb_dma_pri_enc_sub #(ch16_conf,pri_sel) u16(
.valid( valid[16] ),
.pri_in( pri16 ),
.pri_out( pri16_out )
);
wb_dma_pri_enc_sub #(ch17_conf,pri_sel) u17(
.valid( valid[17] ),
.pri_in( pri17 ),
.pri_out( pri17_out )
);
wb_dma_pri_enc_sub #(ch18_conf,pri_sel) u18(
.valid( valid[18] ),
.pri_in( pri18 ),
.pri_out( pri18_out )
);
wb_dma_pri_enc_sub #(ch19_conf,pri_sel) u19(
.valid( valid[19] ),
.pri_in( pri19 ),
.pri_out( pri19_out )
);
wb_dma_pri_enc_sub #(ch20_conf,pri_sel) u20(
.valid( valid[20] ),
.pri_in( pri20 ),
.pri_out( pri20_out )
);
wb_dma_pri_enc_sub #(ch21_conf,pri_sel) u21(
.valid( valid[21] ),
.pri_in( pri21 ),
.pri_out( pri21_out )
);
wb_dma_pri_enc_sub #(ch22_conf,pri_sel) u22(
.valid( valid[22] ),
.pri_in( pri22 ),
.pri_out( pri22_out )
);
wb_dma_pri_enc_sub #(ch23_conf,pri_sel) u23(
.valid( valid[23] ),
.pri_in( pri23 ),
.pri_out( pri23_out )
);
wb_dma_pri_enc_sub #(ch24_conf,pri_sel) u24(
.valid( valid[24] ),
.pri_in( pri24 ),
.pri_out( pri24_out )
);
wb_dma_pri_enc_sub #(ch25_conf,pri_sel) u25(
.valid( valid[25] ),
.pri_in( pri25 ),
.pri_out( pri25_out )
);
wb_dma_pri_enc_sub #(ch26_conf,pri_sel) u26(
.valid( valid[26] ),
.pri_in( pri26 ),
.pri_out( pri26_out )
);
wb_dma_pri_enc_sub #(ch27_conf,pri_sel) u27(
.valid( valid[27] ),
.pri_in( pri27 ),
.pri_out( pri27_out )
);
wb_dma_pri_enc_sub #(ch28_conf,pri_sel) u28(
.valid( valid[28] ),
.pri_in( pri28 ),
.pri_out( pri28_out )
);
wb_dma_pri_enc_sub #(ch29_conf,pri_sel) u29(
.valid( valid[29] ),
.pri_in( pri29 ),
.pri_out( pri29_out )
);
wb_dma_pri_enc_sub #(ch30_conf,pri_sel) u30(
.valid( valid[30] ),
.pri_in( pri30 ),
.pri_out( pri30_out )
);
assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out |
pri4_out | pri5_out | pri6_out | pri7_out |
pri8_out | pri9_out | pri10_out | pri11_out |
pri12_out | pri13_out | pri14_out | pri15_out |
pri16_out | pri17_out | pri18_out | pri19_out |
pri20_out | pri21_out | pri22_out | pri23_out |
pri24_out | pri25_out | pri26_out | pri27_out |
pri28_out | pri29_out | pri30_out;
// 8 Priority Levels
always @(posedge clk)
if(pri_out_tmp[7]) pri_out2 <= #1 3'h7;
else
if(pri_out_tmp[6]) pri_out2 <= #1 3'h6;
else
if(pri_out_tmp[5]) pri_out2 <= #1 3'h5;
else
if(pri_out_tmp[4]) pri_out2 <= #1 3'h4;
else
if(pri_out_tmp[3]) pri_out2 <= #1 3'h3;
else
if(pri_out_tmp[2]) pri_out2 <= #1 3'h2;
else
if(pri_out_tmp[1]) pri_out2 <= #1 3'h1;
else pri_out2 <= #1 3'h0;
// 4 Priority Levels
always @(posedge clk)
if(pri_out_tmp[3]) pri_out1 <= #1 3'h3;
else
if(pri_out_tmp[2]) pri_out1 <= #1 3'h2;
else
if(pri_out_tmp[1]) pri_out1 <= #1 3'h1;
else pri_out1 <= #1 3'h0;
// 2 Priority Levels
always @(posedge clk)
if(pri_out_tmp[1]) pri_out0 <= #1 3'h1;
else pri_out0 <= #1 3'h0;
// Select configured priority
always @(pri_sel or pri_out0 or pri_out1 or pri_out2)
case(pri_sel) // synopsys parallel_case full_case
2'd0: pri_out = pri_out0;
2'd1: pri_out = pri_out1;
2'd2: pri_out = pri_out2;
endcase
endmodule

583
design/dma_verilog/wb_dma_ch_rf.v Normal file
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@ -0,0 +1,583 @@
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA One Channel Register File ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_ch_rf.v,v 1.5 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/10/30 02:06:17 rudi
//
// - Fixed problem where synthesis tools would instantiate latches instead of flip-flops
//
// Revision 1.3 2001/10/19 04:35:04 rudi
//
// - Made the core parameterized
//
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.3 2001/06/14 08:50:01 rudi
//
// Changed Module Name to match file name.
//
// Revision 1.2 2001/06/13 02:26:48 rudi
//
//
// Small changes after running lint.
//
// Revision 1.1 2001/06/05 10:25:27 rudi
//
//
// Initial checkin of register file for one channel.
//
//
//
//
`include "wb_dma_defines.v"
module wb_dma_ch_rf( clk, rst,
pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,
ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,
wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,
// DMA Registers Write Back Channel Select
ch_sel, ndnr,
// DMA Engine Status
dma_busy, dma_err, dma_done, dma_done_all,
// DMA Engine Reg File Update ctrl signals
de_csr, de_txsz, de_adr0, de_adr1,
de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,
de_fetch_descr, dma_rest,
ptr_set
);
parameter [4:0] CH_NO = 5'h0; // This Instances Channel ID
parameter [0:0] CH_EN = 1'b1; // This channel exists
parameter [0:0] HAVE_ARS = 1'b1; // 1=this Instance Supports ARS
parameter [0:0] HAVE_ED = 1'b1; // 1=this Instance Supports External Descriptors
parameter [0:0] HAVE_CBUF= 1'b1; // 1=this Instance Supports Cyclic Buffers
input clk, rst;
output [31:0] pointer;
output [31:0] pointer_s;
output [31:0] ch_csr;
output [31:0] ch_txsz;
output [31:0] ch_adr0;
output [31:0] ch_adr1;
output [31:0] ch_am0;
output [31:0] ch_am1;
output [31:0] sw_pointer;
output ch_stop;
output ch_dis;
output int;
input [31:0] wb_rf_din;
input [7:0] wb_rf_adr;
input wb_rf_we;
input wb_rf_re;
input [4:0] ch_sel;
input ndnr;
// DMA Engine Status
input dma_busy, dma_err, dma_done, dma_done_all;
// DMA Engine Reg File Update ctrl signals
input [31:0] de_csr;
input [11:0] de_txsz;
input [31:0] de_adr0;
input [31:0] de_adr1;
input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;
input de_fetch_descr;
input dma_rest;
////////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
wire [31:0] pointer;
reg [27:0] pointer_r;
reg [27:0] pointer_sr;
reg ptr_valid;
reg ch_eol;
wire [31:0] ch_csr, ch_txsz;
reg [8:0] ch_csr_r;
reg [2:0] ch_csr_r2;
reg [2:0] ch_csr_r3;
reg [2:0] int_src_r;
reg ch_err_r;
reg ch_stop;
reg ch_busy;
reg ch_done;
reg ch_err;
reg rest_en;
reg [10:0] ch_chk_sz_r;
reg [11:0] ch_tot_sz_r;
reg [22:0] ch_txsz_s;
reg ch_sz_inf;
wire [31:0] ch_adr0, ch_adr1;
reg [29:0] ch_adr0_r, ch_adr1_r;
wire [31:0] ch_am0, ch_am1;
reg [27:0] ch_am0_r, ch_am1_r;
reg [29:0] ch_adr0_s, ch_adr1_s;
reg [29:0] sw_pointer_r;
wire sw_pointer_we;
wire [28:0] cmp_adr;
reg ch_dis;
wire ch_enable;
wire pointer_we;
wire ch_csr_we, ch_csr_re, ch_txsz_we, ch_adr0_we, ch_adr1_we;
wire ch_am0_we, ch_am1_we;
reg ch_rl;
wire ch_done_we;
wire ch_err_we;
wire chunk_done_we;
wire ch_csr_dewe, ch_txsz_dewe, ch_adr0_dewe, ch_adr1_dewe;
wire this_ptr_set;
wire ptr_inv;
////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign ch_adr0 = CH_EN ? {ch_adr0_r, 2'h0} : 32'h0;
assign ch_adr1 = CH_EN ? {ch_adr1_r, 2'h0} : 32'h0;
assign ch_am0 = (CH_EN & HAVE_CBUF) ? {ch_am0_r, 4'h0} : 32'hffff_fff0;
assign ch_am1 = (CH_EN & HAVE_CBUF) ? {ch_am1_r, 4'h0} : 32'hffff_fff0;
assign sw_pointer = (CH_EN & HAVE_CBUF) ? {sw_pointer_r,2'h0} : 32'h0;
assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0;
assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0;
assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,
ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0;
assign ch_txsz = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r} : 32'h0;
assign ch_enable = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0;
////////////////////////////////////////////////////////////////////
//
// CH0 control signals
//
parameter [4:0] CH_ADR = CH_NO + 5'h1;
assign ch_csr_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
assign ch_csr_re = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
assign ch_txsz_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1);
assign ch_adr0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2);
assign ch_am0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3);
assign ch_adr1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4);
assign ch_am1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5);
assign pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6);
assign sw_pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);
assign ch_done_we = CH_EN & (((ch_sel==CH_NO) & dma_done_all) | ndnr) &
(ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]);
assign chunk_done_we = CH_EN & (ch_sel==CH_NO) & dma_done;
assign ch_err_we = CH_EN & (ch_sel==CH_NO) & dma_err;
assign ch_csr_dewe = CH_EN & de_csr_we & (ch_sel==CH_NO);
assign ch_txsz_dewe = CH_EN & de_txsz_we & (ch_sel==CH_NO);
assign ch_adr0_dewe = CH_EN & de_adr0_we & (ch_sel==CH_NO);
assign ch_adr1_dewe = CH_EN & de_adr1_we & (ch_sel==CH_NO);
assign ptr_inv = CH_EN & ((ch_sel==CH_NO) & dma_done_all) | ndnr;
assign this_ptr_set = CH_EN & ptr_set & (ch_sel==CH_NO);
always @(posedge clk)
ch_rl <= #1 CH_EN & HAVE_ARS & (
(rest_en & dma_rest) |
((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED])
);
// ---------------------------------------------------
// Pointers
always @(posedge clk or negedge rst)
if(!rst) ptr_valid <= #1 1'b0;
else
if(CH_EN & HAVE_ED)
begin
if( this_ptr_set | (rest_en & dma_rest) )
ptr_valid <= #1 1'b1;
else
if(ptr_inv) ptr_valid <= #1 1'b0;
end
else ptr_valid <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) ch_eol <= #1 1'b0;
else
if(CH_EN & HAVE_ED)
begin
if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL];
else
if(ch_done_we) ch_eol <= #1 1'b0;
end
else ch_eol <= #1 1'b0;
always @(posedge clk)
if(CH_EN & HAVE_ED)
begin
if(pointer_we) pointer_r <= #1 wb_rf_din[31:4];
else
if(this_ptr_set) pointer_r <= #1 de_csr[31:4];
end
else pointer_r <= #1 1'b0;
always @(posedge clk)
if(CH_EN & HAVE_ED)
begin
if(this_ptr_set) pointer_sr <= #1 pointer_r;
end
else pointer_sr <= #1 1'b0;
// ---------------------------------------------------
// CSR
always @(posedge clk or negedge rst)
if(!rst) ch_csr_r <= #1 1'b0;
else
if(CH_EN)
begin
if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0];
else
begin
if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;
if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];
end
end
// done bit
always @(posedge clk or negedge rst)
if(!rst) ch_done <= #1 1'b0;
else
if(CH_EN)
begin
if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];
else
if(ch_done_we) ch_done <= #1 1'b1;
end
// busy bit
always @(posedge clk)
ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy;
// stop bit
always @(posedge clk)
ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP];
// error bit
always @(posedge clk or negedge rst)
if(!rst) ch_err <= #1 1'b0;
else
if(CH_EN)
begin
if(ch_err_we) ch_err <= #1 1'b1;
else
if(ch_csr_re) ch_err <= #1 1'b0;
end
// Priority Bits
always @(posedge clk or negedge rst)
if(!rst) ch_csr_r2 <= #1 3'h0;
else
if(CH_EN & ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13];
// Restart Enable Bit (REST)
always @(posedge clk or negedge rst)
if(!rst) rest_en <= #1 1'b0;
else
if(CH_EN & ch_csr_we) rest_en <= #1 wb_rf_din[16];
// INT Mask
always @(posedge clk or negedge rst)
if(!rst) ch_csr_r3 <= #1 3'h0;
else
if(CH_EN & ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17];
// INT Source
always @(posedge clk or negedge rst)
if(!rst) int_src_r[2] <= #1 1'b0;
else
if(CH_EN)
begin
if(chunk_done_we) int_src_r[2] <= #1 1'b1;
else
if(ch_csr_re) int_src_r[2] <= #1 1'b0;
end
always @(posedge clk or negedge rst)
if(!rst) int_src_r[1] <= #1 1'b0;
else
if(CH_EN)
begin
if(ch_done_we) int_src_r[1] <= #1 1'b1;
else
if(ch_csr_re) int_src_r[1] <= #1 1'b0;
end
always @(posedge clk or negedge rst)
if(!rst) int_src_r[0] <= #1 1'b0;
else
if(CH_EN)
begin
if(ch_err_we) int_src_r[0] <= #1 1'b1;
else
if(ch_csr_re) int_src_r[0] <= #1 1'b0;
end
// Interrupt Output
assign int = |(int_src_r & ch_csr_r3) & CH_EN;
// ---------------------------------------------------
// TXZS
always @(posedge clk)
if(CH_EN)
begin
if(ch_txsz_we)
{ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
else
if(ch_txsz_dewe)
ch_tot_sz_r <= #1 de_txsz;
else
if(ch_rl)
{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;
end
// txsz shadow register
always @(posedge clk)
if(CH_EN & HAVE_ARS)
begin
if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
else
if(rest_en & ch_txsz_dewe & de_fetch_descr)
ch_txsz_s[11:0] <= #1 de_txsz[11:0];
end
// Infinite Size indicator
always @(posedge clk)
if(CH_EN)
begin
if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15];
end
// ---------------------------------------------------
// ADR0
always @(posedge clk)
if(CH_EN)
begin
if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:2];
else
if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2];
else
if(ch_rl) ch_adr0_r <= #1 ch_adr0_s;
end
// Adr0 shadow register
always @(posedge clk)
if(CH_EN & HAVE_ARS)
begin
if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2];
else
if(rest_en & ch_adr0_dewe & de_fetch_descr)
ch_adr0_s <= #1 de_adr0[31:2];
end
// ---------------------------------------------------
// AM0
always @(posedge clk or negedge rst)
if(!rst) ch_am0_r <= #1 28'hfffffff;
else
if(ch_am0_we) ch_am0_r <= #1 wb_rf_din[31:4];
// ---------------------------------------------------
// ADR1
always @(posedge clk)
if(CH_EN)
begin
if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:2];
else
if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2];
else
if(ch_rl) ch_adr1_r <= #1 ch_adr1_s;
end
// Adr1 shadow register
always @(posedge clk)
if(CH_EN & HAVE_ARS)
begin
if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2];
else
if(rest_en & ch_adr1_dewe & de_fetch_descr)
ch_adr1_s <= #1 de_adr1[31:2];
end
// ---------------------------------------------------
// AM1
always @(posedge clk or negedge rst)
if(!rst) ch_am1_r <= #1 28'hfffffff;
else
if(ch_am1_we & CH_EN & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4];
// ---------------------------------------------------
// Software Pointer
always @(posedge clk or negedge rst)
if(!rst) sw_pointer_r <= #1 28'h0;
else
if(sw_pointer_we & CH_EN & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4];
// ---------------------------------------------------
// Software Pointer Match logic
assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];
always @(posedge clk)
ch_dis <= #1 CH_EN & HAVE_CBUF & (sw_pointer[30:2] == cmp_adr) & sw_pointer[31];
endmodule
module wb_dma_ch_rf_dummy(clk, rst,
pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,
ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,
wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,
// DMA Registers Write Back Channel Select
ch_sel, ndnr,
// DMA Engine Status
dma_busy, dma_err, dma_done, dma_done_all,
// DMA Engine Reg File Update ctrl signals
de_csr, de_txsz, de_adr0, de_adr1,
de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,
de_fetch_descr, dma_rest,
ptr_set
);
parameter CH_NO = 0;
parameter HAVE_ARS = 1;
parameter HAVE_ED = 1;
parameter HAVE_CBUF= 1;
input clk, rst;
output [31:0] pointer;
output [31:0] pointer_s;
output [31:0] ch_csr;
output [31:0] ch_txsz;
output [31:0] ch_adr0;
output [31:0] ch_adr1;
output [31:0] ch_am0;
output [31:0] ch_am1;
output [31:0] sw_pointer;
output ch_stop;
output ch_dis;
output int;
input [31:0] wb_rf_din;
input [7:0] wb_rf_adr;
input wb_rf_we;
input wb_rf_re;
input [4:0] ch_sel;
input ndnr;
// DMA Engine Status
input dma_busy, dma_err, dma_done, dma_done_all;
// DMA Engine Reg File Update ctrl signals
input [31:0] de_csr;
input [11:0] de_txsz;
input [31:0] de_adr0;
input [31:0] de_adr1;
input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;
input de_fetch_descr;
input dma_rest;
assign pointer = 32'h0;
assign pointer_s = 32'h0;
assign ch_csr = 32'h0;
assign ch_txsz = 32'h0;
assign ch_adr0 = 32'h0;
assign ch_adr1 = 32'h0;
assign ch_am0 = 32'h0;
assign ch_am1 = 32'h0;
assign sw_pointer = 32'h0;
assign ch_stop = 1'b0;
assign ch_dis = 1'b0;
assign int = 1'b0;
endmodule

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design/dma_verilog/wb_dma_ch_sel.v Normal file
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design/dma_verilog/wb_dma_de.v Normal file
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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA DMA Engine Core ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_de.v,v 1.3 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.3 2001/06/13 02:26:48 rudi
//
//
// Small changes after running lint.
//
// Revision 1.2 2001/06/05 10:22:36 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:10:44 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
module wb_dma_de(clk, rst,
// WISHBONE MASTER INTERFACE 0
mast0_go, mast0_we, mast0_adr, mast0_din,
mast0_dout, mast0_err, mast0_drdy, mast0_wait,
// WISHBONE MASTER INTERFACE 1
mast1_go, mast1_we, mast1_adr, mast1_din,
mast1_dout, mast1_err, mast1_drdy, mast1_wait,
// DMA Engine Init & Setup
de_start, nd, csr, pointer, pointer_s, txsz,
adr0, adr1, am0, am1,
// DMA Engine Register File Update Outputs
de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set,
de_csr, de_txsz, de_adr0, de_adr1, de_fetch_descr,
// DMA Engine Control Outputs
next_ch, de_ack,
// DMA Engine Status
pause_req, paused,
dma_abort, dma_busy, dma_err, dma_done, dma_done_all
);
input clk, rst;
// --------------------------------------
// WISHBONE MASTER INTERFACE 0
output mast0_go; // Perform a Master Cycle
output mast0_we; // Read/Write
output [31:0] mast0_adr; // Address for the transfer
input [31:0] mast0_din; // Internal Input Data
output [31:0] mast0_dout; // Internal Output Data
input mast0_err; // Indicates an error has occurred
input mast0_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
output mast0_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// --------------------------------------
// WISHBONE MASTER INTERFACE 1
output mast1_go; // Perform a Master Cycle
output mast1_we; // Read/Write
output [31:0] mast1_adr; // Address for the transfer
input [31:0] mast1_din; // Internal Input Data
output [31:0] mast1_dout; // Internal Output Data
input mast1_err; // Indicates an error has occurred
input mast1_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
output mast1_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// --------------------------------------
// DMA Engine Signals
// DMA Engine Init & Setup
input de_start; // Start DMA Engine Indicator
input nd; // Next Descriptor Indicator
input [31:0] csr; // Selected Channel CSR
input [31:0] pointer; // Linked List Descriptor pointer
input [31:0] pointer_s; // Previous Pointer
input [31:0] txsz; // Selected Channel Transfer Size
input [31:0] adr0, adr1; // Selected Channel Addresses
input [31:0] am0, am1; // Selected Channel Address Masks
// DMA Engine Register File Update Outputs
output de_csr_we; // Write enable for csr register
output de_txsz_we; // Write enable for txsz register
output de_adr0_we; // Write enable for adr0 register
output de_adr1_we; // Write enable for adr1 register
output ptr_set; // Set Pointer as Valid
output [31:0] de_csr; // Write Data for CSR when loading External Desc.
output [11:0] de_txsz; // Write back data for txsz register
output [31:0] de_adr0; // Write back data for adr0 register
output [31:0] de_adr1; // Write back data for adr1 register
output de_fetch_descr; // Indicates that we are fetching a descriptor
// DMA Engine Control Outputs
output next_ch; // Indicates the DMA Engine is done
output de_ack;
// DMA Abort from RF (software forced abort)
input dma_abort;
// DMA Engine Status
input pause_req;
output paused;
output dma_busy, dma_err, dma_done, dma_done_all;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
parameter [10:0] // synopsys enum state
IDLE = 11'b000_0000_0001,
READ = 11'b000_0000_0010,
WRITE = 11'b000_0000_0100,
UPDATE = 11'b000_0000_1000,
LD_DESC1 = 11'b000_0001_0000,
LD_DESC2 = 11'b000_0010_0000,
LD_DESC3 = 11'b000_0100_0000,
LD_DESC4 = 11'b000_1000_0000,
LD_DESC5 = 11'b001_0000_0000,
WB = 11'b010_0000_0000,
PAUSE = 11'b100_0000_0000;
reg [10:0] /* synopsys enum state */ state, next_state;
// synopsys state_vector state
reg [31:0] mast0_adr, mast1_adr;
reg [29:0] adr0_cnt, adr1_cnt;
wire [29:0] adr0_cnt_next, adr1_cnt_next;
wire [29:0] adr0_cnt_next1, adr1_cnt_next1;
reg adr0_inc, adr1_inc;
reg [8:0] chunk_cnt;
reg chunk_dec;
reg [11:0] tsz_cnt;
reg tsz_dec;
reg de_txsz_we;
reg de_csr_we;
reg de_adr0_we;
reg de_adr1_we;
reg ld_desc_sel;
wire chunk_cnt_is_0_d;
reg chunk_cnt_is_0_r;
wire tsz_cnt_is_0_d;
reg tsz_cnt_is_0_r;
reg read, write;
reg read_r, write_r;
wire rd_ack, wr_ack;
reg rd_ack_r;
reg chunk_0;
wire done;
reg dma_done_d;
reg dma_done_r;
reg dma_abort_r;
reg next_ch;
wire read_hold, write_hold;
reg write_hold_r;
reg [1:0] ptr_adr_low;
reg m0_go;
reg m0_we;
reg ptr_set;
// Aliases
wire a0_inc_en = csr[4]; // Source Address (Adr 0) increment enable
wire a1_inc_en = csr[3]; // Dest. Address (Adr 1) increment enable
wire ptr_valid = pointer[0];
wire use_ed = csr[`WDMA_USE_ED];
reg mast0_drdy_r;
reg paused;
reg de_fetch_descr; // Indicates that we are fetching a descriptor
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
dma_done_r <= #1 dma_done;
// Address Counter 0 (Source Address)
always @(posedge clk)
if(de_start | ptr_set) adr0_cnt <= #1 adr0[31:2];
else
if(adr0_inc & a0_inc_en) adr0_cnt <= #1 adr0_cnt_next;
// 30 Bit Incrementor (registered)
wb_dma_inc30r u0( .clk( clk ),
.in( adr0_cnt ),
.out( adr0_cnt_next1 ) );
assign adr0_cnt_next[1:0] = adr0_cnt_next1[1:0];
assign adr0_cnt_next[2] = am0[4] ? adr0_cnt_next1[2] : adr0_cnt[2];
assign adr0_cnt_next[3] = am0[5] ? adr0_cnt_next1[3] : adr0_cnt[3];
assign adr0_cnt_next[4] = am0[6] ? adr0_cnt_next1[4] : adr0_cnt[4];
assign adr0_cnt_next[5] = am0[7] ? adr0_cnt_next1[5] : adr0_cnt[5];
assign adr0_cnt_next[6] = am0[8] ? adr0_cnt_next1[6] : adr0_cnt[6];
assign adr0_cnt_next[7] = am0[9] ? adr0_cnt_next1[7] : adr0_cnt[7];
assign adr0_cnt_next[8] = am0[10] ? adr0_cnt_next1[8] : adr0_cnt[8];
assign adr0_cnt_next[9] = am0[11] ? adr0_cnt_next1[9] : adr0_cnt[9];
assign adr0_cnt_next[10] = am0[12] ? adr0_cnt_next1[10] : adr0_cnt[10];
assign adr0_cnt_next[11] = am0[13] ? adr0_cnt_next1[11] : adr0_cnt[11];
assign adr0_cnt_next[12] = am0[14] ? adr0_cnt_next1[12] : adr0_cnt[12];
assign adr0_cnt_next[13] = am0[15] ? adr0_cnt_next1[13] : adr0_cnt[13];
assign adr0_cnt_next[14] = am0[16] ? adr0_cnt_next1[14] : adr0_cnt[14];
assign adr0_cnt_next[15] = am0[17] ? adr0_cnt_next1[15] : adr0_cnt[15];
assign adr0_cnt_next[16] = am0[18] ? adr0_cnt_next1[16] : adr0_cnt[16];
assign adr0_cnt_next[17] = am0[19] ? adr0_cnt_next1[17] : adr0_cnt[17];
assign adr0_cnt_next[18] = am0[20] ? adr0_cnt_next1[18] : adr0_cnt[18];
assign adr0_cnt_next[19] = am0[21] ? adr0_cnt_next1[19] : adr0_cnt[19];
assign adr0_cnt_next[20] = am0[22] ? adr0_cnt_next1[20] : adr0_cnt[20];
assign adr0_cnt_next[21] = am0[23] ? adr0_cnt_next1[21] : adr0_cnt[21];
assign adr0_cnt_next[22] = am0[24] ? adr0_cnt_next1[22] : adr0_cnt[22];
assign adr0_cnt_next[23] = am0[25] ? adr0_cnt_next1[23] : adr0_cnt[23];
assign adr0_cnt_next[24] = am0[26] ? adr0_cnt_next1[24] : adr0_cnt[24];
assign adr0_cnt_next[25] = am0[27] ? adr0_cnt_next1[25] : adr0_cnt[25];
assign adr0_cnt_next[26] = am0[28] ? adr0_cnt_next1[26] : adr0_cnt[26];
assign adr0_cnt_next[27] = am0[29] ? adr0_cnt_next1[27] : adr0_cnt[27];
assign adr0_cnt_next[28] = am0[30] ? adr0_cnt_next1[28] : adr0_cnt[28];
assign adr0_cnt_next[29] = am0[31] ? adr0_cnt_next1[29] : adr0_cnt[29];
// Address Counter 1 (Destination Address)
always @(posedge clk)
if(de_start | ptr_set) adr1_cnt <= #1 adr1[31:2];
else
if(adr1_inc & a1_inc_en) adr1_cnt <= #1 adr1_cnt_next;
// 30 Bit Incrementor (registered)
wb_dma_inc30r u1( .clk( clk ),
.in( adr1_cnt ),
.out( adr1_cnt_next1 ) );
assign adr1_cnt_next[1:0] = adr1_cnt_next1[1:0];
assign adr1_cnt_next[2] = am1[4] ? adr1_cnt_next1[2] : adr1_cnt[2];
assign adr1_cnt_next[3] = am1[5] ? adr1_cnt_next1[3] : adr1_cnt[3];
assign adr1_cnt_next[4] = am1[6] ? adr1_cnt_next1[4] : adr1_cnt[4];
assign adr1_cnt_next[5] = am1[7] ? adr1_cnt_next1[5] : adr1_cnt[5];
assign adr1_cnt_next[6] = am1[8] ? adr1_cnt_next1[6] : adr1_cnt[6];
assign adr1_cnt_next[7] = am1[9] ? adr1_cnt_next1[7] : adr1_cnt[7];
assign adr1_cnt_next[8] = am1[10] ? adr1_cnt_next1[8] : adr1_cnt[8];
assign adr1_cnt_next[9] = am1[11] ? adr1_cnt_next1[9] : adr1_cnt[9];
assign adr1_cnt_next[10] = am1[12] ? adr1_cnt_next1[10] : adr1_cnt[10];
assign adr1_cnt_next[11] = am1[13] ? adr1_cnt_next1[11] : adr1_cnt[11];
assign adr1_cnt_next[12] = am1[14] ? adr1_cnt_next1[12] : adr1_cnt[12];
assign adr1_cnt_next[13] = am1[15] ? adr1_cnt_next1[13] : adr1_cnt[13];
assign adr1_cnt_next[14] = am1[16] ? adr1_cnt_next1[14] : adr1_cnt[14];
assign adr1_cnt_next[15] = am1[17] ? adr1_cnt_next1[15] : adr1_cnt[15];
assign adr1_cnt_next[16] = am1[18] ? adr1_cnt_next1[16] : adr1_cnt[16];
assign adr1_cnt_next[17] = am1[19] ? adr1_cnt_next1[17] : adr1_cnt[17];
assign adr1_cnt_next[18] = am1[20] ? adr1_cnt_next1[18] : adr1_cnt[18];
assign adr1_cnt_next[19] = am1[21] ? adr1_cnt_next1[19] : adr1_cnt[19];
assign adr1_cnt_next[20] = am1[22] ? adr1_cnt_next1[20] : adr1_cnt[20];
assign adr1_cnt_next[21] = am1[23] ? adr1_cnt_next1[21] : adr1_cnt[21];
assign adr1_cnt_next[22] = am1[24] ? adr1_cnt_next1[22] : adr1_cnt[22];
assign adr1_cnt_next[23] = am1[25] ? adr1_cnt_next1[23] : adr1_cnt[23];
assign adr1_cnt_next[24] = am1[26] ? adr1_cnt_next1[24] : adr1_cnt[24];
assign adr1_cnt_next[25] = am1[27] ? adr1_cnt_next1[25] : adr1_cnt[25];
assign adr1_cnt_next[26] = am1[28] ? adr1_cnt_next1[26] : adr1_cnt[26];
assign adr1_cnt_next[27] = am1[29] ? adr1_cnt_next1[27] : adr1_cnt[27];
assign adr1_cnt_next[28] = am1[30] ? adr1_cnt_next1[28] : adr1_cnt[28];
assign adr1_cnt_next[29] = am1[31] ? adr1_cnt_next1[29] : adr1_cnt[29];
// Chunk Counter
always @(posedge clk)
if(de_start) chunk_cnt <= #1 txsz[24:16];
else
if(chunk_dec & !chunk_cnt_is_0_r) chunk_cnt <= #1 chunk_cnt - 9'h1;
assign chunk_cnt_is_0_d = (chunk_cnt == 9'h0);
always @(posedge clk)
chunk_cnt_is_0_r <= #1 chunk_cnt_is_0_d;
// Total Size Counter
always @(posedge clk)
if(de_start | ptr_set) tsz_cnt <= #1 txsz[11:0];
else
if(tsz_dec & !tsz_cnt_is_0_r) tsz_cnt <= #1 tsz_cnt - 12'h1;
assign tsz_cnt_is_0_d = (tsz_cnt == 12'h0) & !txsz[15];
always @(posedge clk)
tsz_cnt_is_0_r <= #1 tsz_cnt_is_0_d;
// Counter Control Logic
always @(posedge clk)
chunk_dec <= #1 read & !read_r;
always @(posedge clk)
tsz_dec <= #1 read & !read_r;
//always @(posedge clk)
always @(rd_ack or read_r)
adr0_inc = rd_ack & read_r;
//always @(posedge clk)
always @(wr_ack or write_r)
adr1_inc = wr_ack & write_r;
// Done logic
always @(posedge clk)
chunk_0 <= #1 (txsz[24:16] == 9'h0);
assign done = chunk_0 ? tsz_cnt_is_0_d : (tsz_cnt_is_0_d | chunk_cnt_is_0_d);
assign dma_done = dma_done_d & done;
assign dma_done_all = dma_done_d & (tsz_cnt_is_0_r | (nd & chunk_cnt_is_0_d));
always @(posedge clk)
next_ch <= #1 dma_done;
// Register Update Outputs
assign de_txsz = ld_desc_sel ? mast0_din[11:0] : tsz_cnt;
assign de_adr0 = ld_desc_sel ? mast0_din : {adr0_cnt, 2'b00};
assign de_adr1 = ld_desc_sel ? mast0_din : {adr1_cnt, 2'b00};
assign de_csr = mast0_din;
// Abort logic
always @(posedge clk)
dma_abort_r <= #1 dma_abort | mast0_err | mast1_err;
assign dma_err = dma_abort_r;
assign dma_busy = (state != IDLE);
////////////////////////////////////////////////////////////////////
//
// WISHBONE Interface Logic
//
always @(posedge clk)
read_r <= #1 read;
always @(posedge clk)
write_r <= #1 write;
always @(posedge clk)
rd_ack_r <= #1 read_r;
// Data Path
assign mast0_dout = m0_we ? {20'h0, tsz_cnt} : csr[2] ? mast1_din : mast0_din;
assign mast1_dout = csr[2] ? mast1_din : mast0_din;
// Address Path
always @(posedge clk)
mast0_adr <= #1 m0_go ?
(m0_we ? pointer_s : {pointer[31:4], ptr_adr_low, 2'b00}) :
read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00};
always @(posedge clk)
mast1_adr <= #1 read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00};
// CTRL
assign write_hold = (read | write) & write_hold_r;
always @(posedge clk)
write_hold_r <= #1 read | write;
assign read_hold = done ? read : (read | write);
assign mast0_go = (!csr[2] & read_hold) | (!csr[1] & write_hold) | m0_go;
assign mast1_go = ( csr[2] & read_hold) | ( csr[1] & write_hold);
assign mast0_we = m0_go ? m0_we : (!csr[1] & write);
assign mast1_we = csr[1] & write;
assign rd_ack = (csr[2] ? mast1_drdy : mast0_drdy);
assign wr_ack = (csr[1] ? mast1_drdy : mast0_drdy);
assign mast0_wait = !((!csr[2] & read) | (!csr[1] & write)) & !m0_go;
assign mast1_wait = !(( csr[2] & read) | ( csr[1] & write));
always @(posedge clk)
mast0_drdy_r <= #1 mast0_drdy;
assign de_ack = dma_done;
////////////////////////////////////////////////////////////////////
//
// State Machine
//
always @(posedge clk or negedge rst)
if(!rst) state <= #1 IDLE;
else state <= #1 next_state;
always @(state or pause_req or dma_abort_r or de_start or rd_ack or wr_ack or
done or ptr_valid or use_ed or mast0_drdy or mast0_drdy_r or csr or nd)
begin
next_state = state; // Default keep state
read = 1'b0;
write = 1'b0;
dma_done_d = 1'b0;
de_csr_we = 1'b0;
de_txsz_we = 1'b0;
de_adr0_we = 1'b0;
de_adr1_we = 1'b0;
de_fetch_descr = 1'b0;
m0_go = 1'b0;
m0_we = 1'b0;
ptr_adr_low = 2'h0;
ptr_set = 1'b0;
ld_desc_sel = 1'b0;
paused = 1'b0;
case(state) // synopsys parallel_case full_case
IDLE:
begin
if(pause_req) next_state = PAUSE;
else
if(de_start & !csr[`WDMA_ERR])
begin
if(use_ed & !ptr_valid) next_state = LD_DESC1;
else next_state = READ;
end
end
PAUSE:
begin
paused = 1'b1;
if(!pause_req) next_state = IDLE;
end
READ: // Read From Source
begin
if(dma_abort_r) next_state = UPDATE;
else
if(!rd_ack) read = 1'b1;
else
begin
write = 1'b1;
next_state = WRITE;
end
end
WRITE: // Write To Destination
begin
if(dma_abort_r) next_state = UPDATE;
else
if(!wr_ack) write = 1'b1;
else
begin
if(done) next_state = UPDATE;
else
begin
read = 1'b1;
next_state = READ;
end
end
end
UPDATE: // Update Registers
begin
dma_done_d = 1'b1;
de_txsz_we = 1'b1;
de_adr0_we = 1'b1;
de_adr1_we = 1'b1;
if(use_ed & csr[`WDMA_WRB] & nd)
begin
m0_we = 1'b1;
m0_go = 1'b1;
next_state = WB;
end
else next_state = IDLE;
end
WB:
begin
m0_we = 1'b1;
if(mast0_drdy)
begin
next_state = IDLE;
end
else m0_go = 1'b1;
end
LD_DESC1: // Load Descriptor from memory to registers
begin
ptr_adr_low = 2'h0;
ld_desc_sel = 1'b1;
m0_go = 1'b1;
de_csr_we = 1'b1;
de_txsz_we = 1'b1;
de_fetch_descr = 1'b1;
if(mast0_drdy)
begin
ptr_adr_low = 2'h1;
next_state = LD_DESC2;
end
end
LD_DESC2:
begin
de_fetch_descr = 1'b1;
if(mast0_drdy_r) de_csr_we = 1'b1;
if(mast0_drdy_r) de_txsz_we = 1'b1;
ptr_adr_low = 2'h1;
ld_desc_sel = 1'b1;
m0_go = 1'b1;
if(mast0_drdy)
begin
ptr_adr_low = 2'h2;
next_state = LD_DESC3;
end
end
LD_DESC3:
begin
de_fetch_descr = 1'b1;
if(mast0_drdy_r) de_adr0_we = 1'b1;
ptr_adr_low = 2'h2;
ld_desc_sel = 1'b1;
m0_go = 1'b1;
if(mast0_drdy)
begin
ptr_adr_low = 2'h3;
next_state = LD_DESC4;
end
end
LD_DESC4:
begin
de_fetch_descr = 1'b1;
if(mast0_drdy_r) de_adr1_we = 1'b1;
ptr_adr_low = 2'h3;
ld_desc_sel = 1'b1;
if(mast0_drdy)
begin
next_state = LD_DESC5;
end
else m0_go = 1'b1;
end
LD_DESC5:
begin
de_fetch_descr = 1'b1;
ptr_set = 1'b1;
next_state = READ;
end
endcase
end
endmodule

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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA Definitions ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_defines.v,v 1.5 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/10/19 04:35:04 rudi
//
// - Made the core parameterized
//
// Revision 1.3 2001/09/07 15:34:38 rudi
//
// Changed reset to active high.
//
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.2 2001/06/05 10:22:37 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:11:09 rudi
// Initial Release
//
//
//
`timescale 1ns / 10ps
// This define selects how the slave interface determines if
// the internal register file or pass through mode are selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
// NOTE: The entire pass-through mode is implemented in combinatorial
// logic only. So the more address lines we look at and compare here
// the higher will be the initial delay when pass-through mode is selected.
// Here we look at the top 8 address bit. If they are all 1, the
// register file is selected. Use this with caution !!!
`define WDMA_REG_SEL (wb_addr_i[31:28] == rf_addr)
// DO NOT MODIFY BEYOND THIS POINT
// CSR Bits
`define WDMA_CH_EN 0
`define WDMA_DST_SEL 1
`define WDMA_SRC_SEL 2
`define WDMA_INC_DST 3
`define WDMA_INC_SRC 4
`define WDMA_MODE 5
`define WDMA_ARS 6
`define WDMA_USE_ED 7
`define WDMA_WRB 8
`define WDMA_STOP 9
`define WDMA_BUSY 10
`define WDMA_DONE 11
`define WDMA_ERR 12
`define WDMA_ED_EOL 20

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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA Primitives ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_inc30r.v,v 1.2 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.2 2001/06/05 10:22:37 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:11:12 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
module wb_dma_inc30r(clk, in, out);
input clk;
input [29:0] in;
output [29:0] out;
// INC30_CENTER indicates the center bit of the 30 bit incrementor
// so it can be easily manually optimized for best performance
parameter INC30_CENTER = 16;
reg [INC30_CENTER:0] out_r;
always @(posedge clk)
out_r <= #1 in[(INC30_CENTER - 1):0] + 1;
assign out[29:INC30_CENTER] = in[29:INC30_CENTER] + out_r[INC30_CENTER];
assign out[(INC30_CENTER - 1):0] = out_r;
endmodule

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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA Priority Encoder Sub-Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_pri_enc_sub.v,v 1.4 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/10/19 04:35:04 rudi
//
// - Made the core parameterized
//
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/08/07 08:00:43 rudi
//
//
// Split up priority encoder modules to separate files
//
//
//
//
//
//
`include "wb_dma_defines.v"
// Priority Encoder
//
// Determines the channel with the highest priority, also takes
// the valid bit in consideration
module wb_dma_pri_enc_sub(valid, pri_in, pri_out);
parameter [3:0] ch_conf = 4'b0000;
parameter [1:0] pri_sel = 2'd0;
input valid;
input [2:0] pri_in;
output [7:0] pri_out;
wire [7:0] pri_out;
reg [7:0] pri_out_d;
reg [7:0] pri_out_d0;
reg [7:0] pri_out_d1;
reg [7:0] pri_out_d2;
assign pri_out = ch_conf[0] ? pri_out_d : 8'h0;
// Select Configured Priority
always @(pri_sel or pri_out_d0 or pri_out_d1 or pri_out_d2)
case(pri_sel) // synopsys parallel_case full_case
2'd0: pri_out_d = pri_out_d0;
2'd1: pri_out_d = pri_out_d1;
2'd2: pri_out_d = pri_out_d2;
endcase
// 8 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d2 = 8'b0000_0001;
else
if(pri_in==3'h0) pri_out_d2 = 8'b0000_0001;
else
if(pri_in==3'h1) pri_out_d2 = 8'b0000_0010;
else
if(pri_in==3'h2) pri_out_d2 = 8'b0000_0100;
else
if(pri_in==3'h3) pri_out_d2 = 8'b0000_1000;
else
if(pri_in==3'h4) pri_out_d2 = 8'b0001_0000;
else
if(pri_in==3'h5) pri_out_d2 = 8'b0010_0000;
else
if(pri_in==3'h6) pri_out_d2 = 8'b0100_0000;
else pri_out_d2 = 8'b1000_0000;
// 4 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d1 = 8'b0000_0001;
else
if(pri_in==3'h0) pri_out_d1 = 8'b0000_0001;
else
if(pri_in==3'h1) pri_out_d1 = 8'b0000_0010;
else
if(pri_in==3'h2) pri_out_d1 = 8'b0000_0100;
else pri_out_d1 = 8'b0000_1000;
// 2 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d0 = 8'b0000_0001;
else
if(pri_in==3'h0) pri_out_d0 = 8'b0000_0001;
else pri_out_d0 = 8'b0000_0010;
endmodule

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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA WISHBONE Interface ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_wb_if.v,v 1.3 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/10/19 04:35:04 rudi
//
// - Made the core parameterized
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.2 2001/06/05 10:22:37 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:10:54 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
module wb_dma_wb_if(clk, rst,
// Wishbone
wbs_data_i, wbs_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o,
wbm_data_i, wbm_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
// Master
mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err,
mast_drdy, mast_wait, pt_sel_i, mast_pt_in, mast_pt_out,
// Slave
slv_adr, slv_din, slv_dout, slv_re, slv_we,
pt_sel_o, slv_pt_out, slv_pt_in
);
parameter rf_addr = 0;
input clk, rst;
// --------------------------------------
// WISHBONE INTERFACE
// Slave Interface
input [31:0] wbs_data_i;
output [31:0] wbs_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
// Master Interface
input [31:0] wbm_data_i;
output [31:0] wbm_data_o;
output [31:0] wb_addr_o;
output [3:0] wb_sel_o;
output wb_we_o;
output wb_cyc_o;
output wb_stb_o;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
// --------------------------------------
// MASTER INTERFACE
input mast_go; // Perform a Master Cycle (as long as this
// line is asserted)
input mast_we; // Read/Write
input [31:0] mast_adr; // Address for the transfer
input [31:0] mast_din; // Internal Input Data
output [31:0] mast_dout; // Internal Output Data
output mast_err; // Indicates an error has occurred
output mast_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
input mast_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// Pass Through Interface
input pt_sel_i; // Pass Through Mode Selected
input [70:0] mast_pt_in; // Grouped WISHBONE inputs
output [34:0] mast_pt_out; // Grouped WISHBONE outputs
// --------------------------------------
// Slave INTERFACE
// This is the register File Interface
output [31:0] slv_adr; // Slave Address
input [31:0] slv_din; // Slave Input Data
output [31:0] slv_dout; // Slave Output Data
output slv_re; // Slave Read Enable
output slv_we; // Slave Write Enable
// Pass through Interface
output pt_sel_o; // Pass Through Mode Active
output [70:0] slv_pt_out; // Grouped WISHBONE out signals
input [34:0] slv_pt_in; // Grouped WISHBONE in signals
////////////////////////////////////////////////////////////////////
//
// Modules
//
wb_dma_wb_mast u0(
.clk( clk ),
.rst( rst ),
.wb_data_i( wbs_data_i ),
.wb_data_o( wbs_data_o ),
.wb_addr_o( wb_addr_o ),
.wb_sel_o( wb_sel_o ),
.wb_we_o( wb_we_o ),
.wb_cyc_o( wb_cyc_o ),
.wb_stb_o( wb_stb_o ),
.wb_ack_i( wb_ack_i ),
.wb_err_i( wb_err_i ),
.wb_rty_i( wb_rty_i ),
.mast_go( mast_go ),
.mast_we( mast_we ),
.mast_adr( mast_adr ),
.mast_din( mast_din ),
.mast_dout( mast_dout ),
.mast_err( mast_err ),
.mast_drdy( mast_drdy ),
.mast_wait( mast_wait ),
.pt_sel( pt_sel_i ),
.mast_pt_in( mast_pt_in ),
.mast_pt_out( mast_pt_out )
);
wb_dma_wb_slv #(rf_addr) u1(
.clk( clk ),
.rst( rst ),
.wb_data_i( wbm_data_i ),
.wb_data_o( wbm_data_o ),
.wb_addr_i( wb_addr_i ),
.wb_sel_i( wb_sel_i ),
.wb_we_i( wb_we_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( wb_ack_o ),
.wb_err_o( wb_err_o ),
.wb_rty_o( wb_rty_o ),
.slv_adr( slv_adr ),
.slv_din( slv_din ),
.slv_dout( slv_dout ),
.slv_re( slv_re ),
.slv_we( slv_we ),
.pt_sel( pt_sel_o ),
.slv_pt_out( slv_pt_out ),
.slv_pt_in( slv_pt_in )
);
endmodule

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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA WISHBONE Master Interface ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_wb_mast.v,v 1.2 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.2 2001/06/05 10:22:37 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:11:05 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
module wb_dma_wb_mast(clk, rst,
wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err,
mast_drdy, mast_wait,
pt_sel, mast_pt_in, mast_pt_out
);
input clk, rst;
// --------------------------------------
// WISHBONE INTERFACE
input [31:0] wb_data_i;
output [31:0] wb_data_o;
output [31:0] wb_addr_o;
output [3:0] wb_sel_o;
output wb_we_o;
output wb_cyc_o;
output wb_stb_o;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
// --------------------------------------
// INTERNAL DMA INTERFACE
input mast_go; // Perform a Master Cycle (as long as this
// line is asserted)
input mast_we; // Read/Write
input [31:0] mast_adr; // Address for the transfer
input [31:0] mast_din; // Internal Input Data
output [31:0] mast_dout; // Internal Output Data
output mast_err; // Indicates an error has occurred
output mast_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
input mast_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// Pass Through Interface
input pt_sel; // Pass Through Mode Selected
input [70:0] mast_pt_in; // Grouped WISHBONE inputs
output [34:0] mast_pt_out; // Grouped WISHBONE outputs
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg mast_cyc, mast_stb;
reg mast_we_r;
reg [3:0] mast_be;
reg [31:0] mast_dout;
////////////////////////////////////////////////////////////////////
//
// Pass-Through Interface
//
assign {wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o} =
pt_sel ? mast_pt_in :
{mast_din, mast_adr, mast_be, mast_we_r, mast_cyc, mast_stb};
assign mast_pt_out = {wb_data_i, wb_ack_i, wb_err_i, wb_rty_i};
////////////////////////////////////////////////////////////////////
//
// DMA Engine Interface
//
always @(posedge clk)
if(wb_ack_i) mast_dout <= #1 wb_data_i;
always @(posedge clk)
mast_be <= #1 4'hf;
always @(posedge clk)
mast_we_r <= #1 mast_we;
always @(posedge clk)
mast_cyc <= #1 mast_go;
always @(posedge clk)
mast_stb <= #1 mast_go & !mast_wait;
assign mast_drdy = wb_ack_i;
assign mast_err = wb_err_i;
endmodule

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design/dma_verilog/wb_dma_wb_slv.v Normal file
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@ -0,0 +1,176 @@
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA WISHBONE Slave Interface ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_wb_slv.v,v 1.4 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/10/19 04:35:04 rudi
//
// - Made the core parameterized
//
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.2 2001/06/05 10:22:37 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:10:59 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
module wb_dma_wb_slv(clk, rst,
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o,
// This is the register File Interface
slv_adr, slv_din, slv_dout, slv_re, slv_we,
// Pass through Interface
pt_sel, slv_pt_out, slv_pt_in
);
parameter rf_addr = 0;
input clk, rst;
// --------------------------------------
// WISHBONE INTERFACE
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
// This is the register File Interface
output [31:0] slv_adr; // Slave Address
input [31:0] slv_din; // Slave Input Data
output [31:0] slv_dout; // Slave Output Data
output slv_re; // Slave Read Enable
output slv_we; // Slave Write Enable
// Pass through Interface
output pt_sel; // Pass Through Mode Active
output [70:0] slv_pt_out; // Grouped WISHBONE out signals
input [34:0] slv_pt_in; // Grouped WISHBONE in signals
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg slv_re, slv_we;
wire rf_sel;
reg rf_ack;
reg [31:0] slv_adr, slv_dout;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign rf_sel = `WDMA_REG_SEL ;
////////////////////////////////////////////////////////////////////
//
// Pass Through Logic
//
//assign pt_sel = !rf_sel;
assign pt_sel = !rf_sel & wb_cyc_i;
assign slv_pt_out = {wb_data_i, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i};
assign {wb_data_o, wb_ack_o, wb_err_o, wb_rty_o} = pt_sel ? slv_pt_in :
{slv_din, rf_ack, 1'b0, 1'b0};
////////////////////////////////////////////////////////////////////
//
// Register File Logic
//
always @(posedge clk)
slv_adr <= #1 wb_addr_i;
always @(posedge clk)
slv_re <= #1 rf_sel & wb_cyc_i & wb_stb_i & !wb_we_i & !rf_ack & !slv_re;
always @(posedge clk)
slv_we <= #1 rf_sel & wb_cyc_i & wb_stb_i & wb_we_i & !rf_ack;
always @(posedge clk)
slv_dout <= #1 wb_data_i;
always @(posedge clk)
rf_ack <= #1 (slv_re | slv_we) & wb_cyc_i & wb_stb_i & !rf_ack ;
endmodule

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design/wb2avalon.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb2avalon is
generic (
ADDR_WIDTH_G : natural := 32;
DATA_WIDTH_G : natural := 32
);
port(
-- Avalon Signals
avalon_write : out std_logic;
avalon_read : out std_logic;
avalon_cs : out std_logic;
avalon_waitrequest : in std_logic;
avalon_data_in : in std_logic_vector(DATA_WIDTH_G-1 downto 0);
avalon_data_out : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
avalon_address : out std_logic_vector(ADDR_WIDTH_G-1 downto 0);
-- avalon_response : std_logic_vector(1 downto 0);
-- Wishbone Signals
wb_cyc : in std_logic;
wb_we : in std_logic;
wb_stb : in std_logic;
wb_ack : out std_logic;
wb_address : in std_logic_vector(ADDR_WIDTH_G-1 downto 0);
wb_data_out : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
wb_data_in : in std_logic_vector(DATA_WIDTH_G-1 downto 0);
wb_err : out std_logic;
wb_rty : out std_logic
);
end entity wb2avalon;
architecture RTL of wb2avalon is
begin
avalon_address <= wb_address;
avalon_data_out <= wb_data_in;
wb_data_out <= avalon_data_in;
avalon_cs <= wb_stb;
avalon_write <= wb_cyc and wb_we;
avalon_read <= wb_cyc and (not wb_we);
wb_ack <= not avalon_waitrequest;
wb_err <= '0';
wb_rty <= '0';
end architecture RTL;