49 lines
1.4 KiB
VHDL
49 lines
1.4 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity wb2avalon is
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generic (
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ADDR_WIDTH_G : natural := 32;
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DATA_WIDTH_G : natural := 32
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);
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port(
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-- Avalon Signals
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avalon_write : out std_logic;
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avalon_read : out std_logic;
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avalon_cs : out std_logic;
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avalon_waitrequest : in std_logic;
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avalon_data_in : in std_logic_vector(DATA_WIDTH_G-1 downto 0);
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avalon_data_out : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
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avalon_address : out std_logic_vector(ADDR_WIDTH_G-1 downto 0);
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-- avalon_response : std_logic_vector(1 downto 0);
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-- Wishbone Signals
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wb_cyc : in std_logic;
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wb_we : in std_logic;
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wb_stb : in std_logic;
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wb_ack : out std_logic;
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wb_address : in std_logic_vector(ADDR_WIDTH_G-1 downto 0);
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wb_data_out : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
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wb_data_in : in std_logic_vector(DATA_WIDTH_G-1 downto 0);
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wb_err : out std_logic;
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wb_rty : out std_logic
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);
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end entity wb2avalon;
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architecture RTL of wb2avalon is
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begin
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avalon_address <= wb_address;
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avalon_data_out <= wb_data_in;
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wb_data_out <= avalon_data_in;
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avalon_cs <= wb_stb;
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avalon_write <= wb_cyc and wb_we;
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avalon_read <= wb_cyc and (not wb_we);
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wb_ack <= not avalon_waitrequest;
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wb_err <= '0';
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wb_rty <= '0';
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end architecture RTL;
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