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fpga
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avalon-dma
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master
avalon-dma
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design
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Mario Hüttel
9d67bb6b01
init commit
2018-03-06 15:11:37 +01:00
..
dma_verilog
init commit
2018-03-06 15:11:37 +01:00
avalon2wb.vhd
init commit
2018-03-06 15:11:37 +01:00
dma_31ch.vhd
init commit
2018-03-06 15:11:37 +01:00
wb2avalon.vhd
init commit
2018-03-06 15:11:37 +01:00